arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/errno.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
  12
  13 #ifdef CONFIG_SYS_FSL_SRDS_1
  14 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
  15 #endif
  16 #ifdef CONFIG_SYS_FSL_SRDS_2
  17 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
  18 #endif
  19
  20 int is_serdes_configured(enum srds_prtcl device)
  21 {
  22         int ret = 0;
  23
  24 #ifdef CONFIG_SYS_FSL_SRDS_1
  25         ret |= serdes1_prtcl_map[device];
  26 #endif
  27 #ifdef CONFIG_SYS_FSL_SRDS_2
  28         ret |= serdes2_prtcl_map[device];
  29 #endif
  30
  31         return !!ret;
  32 }
  33
  34 int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
  35 {
  36         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  37         u32 cfg = in_le32(&gur->rcwsr[28]);
  38         int i;
  39
  40         switch (sd) {
  41 #ifdef CONFIG_SYS_FSL_SRDS_1
  42         case FSL_SRDS_1:
  43                 cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  44                 cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  45                 break;
  46 #endif
  47 #ifdef CONFIG_SYS_FSL_SRDS_2
  48         case FSL_SRDS_2:
  49                 cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
  50                 cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  51                 break;
  52 #endif
  53         default:
  54                 printf("invalid SerDes%d\n", sd);
  55                 break;
  56         }
  57         /* Is serdes enabled at all? */
  58         if (cfg == 0)
  59                 return -ENODEV;
  60
  61         for (i = 0; i < SRDS_MAX_LANES; i++) {
  62                 if (serdes_get_prtcl(sd, cfg, i) == device)
  63                         return i;
  64         }
  65
  66         return -ENODEV;
  67 }
  68
  69 void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
  70                 u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
  71 {
  72         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  73         u32 cfg;
  74         int lane;
  75
  76         memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
  77
  78         cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
  79         cfg >>= sd_prctl_shift;
  80         printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
  81
  82         if (!is_serdes_prtcl_valid(sd, cfg))
  83                 printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
  84
  85         for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  86                 enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
  87                 if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
  88                         debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
  89                 else
  90                         serdes_prtcl_map[lane_prtcl] = 1;
  91         }
  92 }
  93
  94 void fsl_serdes_init(void)
  95 {
  96 #ifdef CONFIG_SYS_FSL_SRDS_1
  97         serdes_init(FSL_SRDS_1,
  98                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
  99                     FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
 100                     FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
 101                     serdes1_prtcl_map);
 102 #endif
 103 #ifdef CONFIG_SYS_FSL_SRDS_2
 104         serdes_init(FSL_SRDS_2,
 105                     CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
 106                     FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
 107                     FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
 108                     serdes2_prtcl_map);
 109 #endif
 110 }