1 /* vi: set ts=8 sw=8 noet: */
3 * u-boot - Startup Code for XScale IXP
5 * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
7 * Based on startup code example contained in the
8 * Intel IXP4xx Programmer's Guide and past u-boot Start.S
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm-offsets.h>
33 #include <asm/arch/ixp425.h>
35 #define MMU_Control_M 0x001 /* Enable MMU */
36 #define MMU_Control_A 0x002 /* Enable address alignment faults */
37 #define MMU_Control_C 0x004 /* Enable cache */
38 #define MMU_Control_W 0x008 /* Enable write-buffer */
39 #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
40 #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
41 #define MMU_Control_L 0x040 /* Compatability: */
42 #define MMU_Control_B 0x080 /* Enable Big-Endian */
43 #define MMU_Control_S 0x100 /* Enable system protection */
44 #define MMU_Control_R 0x200 /* Enable ROM protection */
45 #define MMU_Control_I 0x1000 /* Enable Instruction cache */
46 #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
47 #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
54 .macro DELAY_FOR cycles, reg0
60 /* wait for coprocessor write complete */
62 mrc p15,0,\reg,c2,c0,0
70 ldr pc, _undefined_instruction
71 ldr pc, _software_interrupt
72 ldr pc, _prefetch_abort
79 _undefined_instruction: .word undefined_instruction
80 _software_interrupt: .word software_interrupt
81 _prefetch_abort: .word prefetch_abort
82 _data_abort: .word data_abort
83 _not_used: .word not_used
87 .balignl 16,0xdeadbeef
91 * Startup Code (reset vector)
93 * do important init only if we don't start from memory!
94 * - relocate armboot to ram
96 * - jump to second stage
101 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
102 .word CONFIG_SPL_TEXT_BASE
104 .word CONFIG_SYS_TEXT_BASE
108 * These are defined in the board-specific linker script.
109 * Subtracting _start from them lets the linker put their
110 * relative position in the executable instead of leaving
113 .globl _bss_start_ofs
115 .word __bss_start - _start
117 .globl _image_copy_end_ofs
119 .word __image_copy_end - _start
123 .word __bss_end - _start
129 #ifdef CONFIG_USE_IRQ
130 /* IRQ stack memory (calculated at run-time) */
131 .globl IRQ_STACK_START
135 /* IRQ stack memory (calculated at run-time) */
136 .globl FIQ_STACK_START
141 /* IRQ stack memory (calculated at run-time) + 8 bytes */
142 .globl IRQ_STACK_START_IN
147 * the actual reset code
151 /* disable mmu, set big-endian */
153 mcr p15, 0, r0, c1, c0, 0
156 /* invalidate I & D caches & BTB */
157 mcr p15, 0, r0, c7, c7, 0
160 /* invalidate I & Data TLB */
161 mcr p15, 0, r0, c8, c7, 0
164 /* drain write and fill buffers */
165 mcr p15, 0, r0, c7, c10, 4
168 /* disable write buffer coalescing */
169 mrc p15, 0, r0, c1, c0, 1
171 mcr p15, 0, r0, c1, c0, 1
174 /* set EXP CS0 to the optimum timing */
175 ldr r1, =CONFIG_SYS_EXP_CS0
176 ldr r2, =IXP425_EXP_CS0
179 /* make sure flash is visible at 0 */
180 mov r1, #CONFIG_SYS_SDR_CONFIG
181 ldr r2, =IXP425_SDR_CONFIG
184 /* disable refresh cycles */
186 ldr r3, =IXP425_SDR_REFRESH
189 /* send nop command */
191 ldr r4, =IXP425_SDR_IR
195 /* set SDRAM internal refresh val */
196 ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
200 /* send precharge-all command to close all open banks */
205 /* provide 8 auto-refresh cycles */
213 /* set mode register in sdram */
214 mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
218 /* send normal operation command */
223 /* invalidate I & D caches & BTB */
224 mcr p15, 0, r0, c7, c7, 0
227 /* invalidate I & Data TLB */
228 mcr p15, 0, r0, c8, c7, 0
231 /* drain write and fill buffers */
232 mcr p15, 0, r0, c7, c10, 4
235 /* remove flash mirror at 0x00000000 */
236 ldr r2, =IXP425_EXP_CFG0
238 bic r1, r1, #0x80000000
241 /* invalidate I & Data TLB */
242 mcr p15, 0, r0, c8, c7, 0
246 mrc p15, 0, r0, c1, c0, 0
247 orr r0, r0, #MMU_Control_I
248 mcr p15, 0, r0, c1, c0, 0
251 mrs r0,cpsr /* set the cpu to SVC32 mode */
252 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
258 /*------------------------------------------------------------------------------*/
261 * void relocate_code (addr_sp, gd, addr_moni)
263 * This function relocates the monitor code.
267 mov r4, r0 /* save addr_sp */
268 mov r5, r1 /* save addr of gd */
269 mov r6, r2 /* save addr of destination */
272 subs r9, r6, r0 /* r9 <- relocation offset */
273 beq relocate_done /* skip relocation */
274 mov r1, r6 /* r1 <- scratch for copy_loop */
275 ldr r3, _image_copy_end_ofs
276 add r2, r0, r3 /* r2 <- source end address */
279 ldmia r0!, {r10-r11} /* copy from source address [r0] */
280 stmia r1!, {r10-r11} /* copy to target address [r1] */
281 cmp r0, r2 /* until source end address [r2] */
284 #ifndef CONFIG_SPL_BUILD
286 * fix .rel.dyn relocations
288 ldr r0, _TEXT_BASE /* r0 <- Text base */
289 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
290 add r10, r10, r0 /* r10 <- sym table in FLASH */
291 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
292 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
293 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
294 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
296 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
297 add r0, r0, r9 /* r0 <- location to fix up in RAM */
300 cmp r7, #23 /* relative fixup? */
302 cmp r7, #2 /* absolute fixup? */
304 /* ignore unknown type of fixup */
307 /* absolute fix: set location to (offset) symbol value */
308 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
309 add r1, r10, r1 /* r1 <- address of symbol in table */
310 ldr r1, [r1, #4] /* r1 <- symbol value */
311 add r1, r1, r9 /* r1 <- relocated sym addr */
314 /* relative fix: increase location by offset */
319 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
329 .word __rel_dyn_start - _start
331 .word __rel_dyn_end - _start
333 .word __dynsym_start - _start
335 .globl c_runtime_cpu_setup
340 /****************************************************************************/
342 /* Interrupt handling */
344 /****************************************************************************/
346 /* IRQ stack frame */
348 #define S_FRAME_SIZE 72
370 #define MODE_SVC 0x13
372 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
374 .macro bad_save_user_regs
375 sub sp, sp, #S_FRAME_SIZE
376 stmia sp, {r0 - r12} /* Calling r0-r12 */
379 ldr r2, IRQ_STACK_START_IN
380 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
381 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
385 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
390 /* use irq_save_user_regs / irq_restore_user_regs for */
391 /* IRQ/FIQ handling */
393 .macro irq_save_user_regs
394 sub sp, sp, #S_FRAME_SIZE
395 stmia sp, {r0 - r12} /* Calling r0-r12 */
397 stmdb r8, {sp, lr}^ /* Calling SP, LR */
398 str lr, [r8, #0] /* Save calling PC */
400 str r6, [r8, #4] /* Save CPSR */
401 str r0, [r8, #8] /* Save OLD_R0 */
405 .macro irq_restore_user_regs
406 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
408 ldr lr, [sp, #S_PC] @ Get PC
409 add sp, sp, #S_FRAME_SIZE
410 subs pc, lr, #4 @ return & move spsr_svc into cpsr
414 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
416 str lr, [r13] @ save caller lr / spsr
420 mov r13, #MODE_SVC @ prepare SVC-Mode
426 .macro get_irq_stack @ setup IRQ stack
427 ldr sp, IRQ_STACK_START
430 .macro get_fiq_stack @ setup FIQ stack
431 ldr sp, FIQ_STACK_START
435 /****************************************************************************/
437 /* exception handlers */
439 /****************************************************************************/
442 undefined_instruction:
445 bl do_undefined_instruction
451 bl do_software_interrupt
471 #ifdef CONFIG_USE_IRQ
478 irq_restore_user_regs
483 irq_save_user_regs /* someone ought to write a more */
484 bl do_fiq /* effiction fiq_save_user_regs */
485 irq_restore_user_regs
503 /****************************************************************************/
505 /* Reset function: Use Watchdog to reset */
507 /****************************************************************************/