2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra20 Clock control functions */
26 #include <asm/arch/clock.h>
27 #include <asm/arch/tegra.h>
28 #include <asm/arch-tegra/clk_rst.h>
29 #include <asm/arch-tegra/timer.h>
34 * This is our record of the current clock rate of each clock. We don't
35 * fill all of these in since we are only really interested in clocks which
38 static unsigned pll_rate[CLOCK_ID_COUNT];
41 * The oscillator frequency is fixed to one of four set values. Based on this
42 * the other clocks are set up appropriately.
44 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
52 * Clock types that we can use as a source. The Tegra20 has muxes for the
53 * peripheral clocks, and in most cases there are four options for the clock
54 * source. This gives us a clock 'type' and exploits what commonality exists
57 * Letters are obvious, except for T which means CLK_M, and S which means the
58 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
59 * datasheet) and PLL_M are different things. The former is the basic
60 * clock supplied to the SOC from an external oscillator. The latter is the
63 * See definitions in clock_id in the header file.
66 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
67 CLOCK_TYPE_MCPA, /* and so on */
71 CLOCK_TYPE_PCMT16, /* CLOCK_TYPE_PCMT with 16-bit divider */
76 CLOCK_TYPE_NONE = -1, /* invalid clock type */
79 /* return 1 if a peripheral ID is in range */
80 #define clock_type_id_isvalid(id) ((id) >= 0 && \
81 (id) < CLOCK_TYPE_COUNT)
83 char pllp_valid = 1; /* PLLP is set up correctly */
86 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
90 * Clock source mux for each clock type. This just converts our enum into
91 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
92 * is special as it has 5 sources. Since it also has a different number of
93 * bits in its register for the source, we just handle it with a special
96 #define CLK(x) CLOCK_ID_ ## x
97 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
98 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
99 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
100 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
101 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
102 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
103 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
104 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
105 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
109 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
110 * not in the header file since it is for purely internal use - we want
111 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
112 * confusion bewteen PERIPH_ID_... and PERIPHC_...
114 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
117 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
118 * use it for reset, clock enable, clock source/divider and even pinmuxing
121 enum periphc_internal_id {
138 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
195 /* return 1 if a periphc_internal_id is in range */
196 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
197 (id) < PERIPHC_COUNT)
200 * Clock type for each peripheral clock source. We put the name in each
201 * record just so it is easy to match things up
203 #define TYPE(name, type) type
204 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
206 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
207 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
208 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
209 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
210 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
211 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
212 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
213 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
216 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
217 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
218 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
219 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
220 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
221 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
222 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
223 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
226 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
227 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
228 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
229 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
231 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
232 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
233 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
236 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
237 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
238 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
239 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
240 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
241 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
242 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
243 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
246 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
247 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
248 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
249 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
250 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
251 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
252 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
253 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
256 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
257 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
258 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
259 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
260 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
262 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
263 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
266 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
267 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
268 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
269 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
270 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
271 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
275 * This array translates a periph_id to a periphc_internal_id
277 * Not present/matched up:
278 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
279 * SPDIF - which is both 0x08 and 0x0c
282 #define NONE(name) (-1)
283 #define OFFSET(name, value) PERIPHC_ ## name
284 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
293 PERIPHC_UART2, /* and vfir 0x68 */
298 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
325 /* Middle word: 63:32 */
337 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
347 PERIPHC_TVO, /* also CVE 0x40 */
365 /* Upper word 95:64 */
400 * Get the oscillator frequency, from the corresponding hardware configuration
403 enum clock_osc_freq clock_get_osc_freq(void)
405 struct clk_rst_ctlr *clkrst =
406 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
409 reg = readl(&clkrst->crc_osc_ctrl);
410 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
413 int clock_get_osc_bypass(void)
415 struct clk_rst_ctlr *clkrst =
416 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
419 reg = readl(&clkrst->crc_osc_ctrl);
420 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
423 /* Returns a pointer to the registers of the given pll */
424 static struct clk_pll *get_pll(enum clock_id clkid)
426 struct clk_rst_ctlr *clkrst =
427 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
429 assert(clock_id_is_pll(clkid));
430 return &clkrst->crc_pll[clkid];
433 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
434 u32 *divp, u32 *cpcon, u32 *lfcon)
436 struct clk_pll *pll = get_pll(clkid);
439 assert(clkid != CLOCK_ID_USB);
441 /* Safety check, adds to code size but is small */
442 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
444 data = readl(&pll->pll_base);
445 *divm = (data & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
446 *divn = (data & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT;
447 *divp = (data & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
448 data = readl(&pll->pll_misc);
449 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
450 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
455 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
456 u32 divp, u32 cpcon, u32 lfcon)
458 struct clk_pll *pll = get_pll(clkid);
462 * We cheat by treating all PLL (except PLLU) in the same fashion.
463 * This works only because:
464 * - same fields are always mapped at same offsets, except DCCON
465 * - DCCON is always 0, doesn't conflict
466 * - M,N, P of PLLP values are ignored for PLLP
468 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
469 writel(data, &pll->pll_misc);
471 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
472 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
474 if (clkid == CLOCK_ID_USB)
475 data |= divp << PLLU_VCO_FREQ_SHIFT;
477 data |= divp << PLL_DIVP_SHIFT;
478 writel(data, &pll->pll_base);
480 /* calculate the stable time */
481 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
484 /* return 1 if a peripheral ID is in range and valid */
485 static int clock_periph_id_isvalid(enum periph_id id)
487 if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
488 printf("Peripheral id %d out of range\n", id);
491 case PERIPH_ID_RESERVED1:
492 case PERIPH_ID_RESERVED2:
493 case PERIPH_ID_RESERVED30:
494 case PERIPH_ID_RESERVED35:
495 case PERIPH_ID_RESERVED56:
496 case PERIPH_ID_RESERVED74:
497 case PERIPH_ID_RESERVED76:
498 case PERIPH_ID_RESERVED77:
499 case PERIPH_ID_RESERVED78:
500 case PERIPH_ID_RESERVED79:
501 case PERIPH_ID_RESERVED80:
502 case PERIPH_ID_RESERVED81:
503 case PERIPH_ID_RESERVED82:
504 case PERIPH_ID_RESERVED83:
505 case PERIPH_ID_RESERVED91:
506 printf("Peripheral id %d is reserved\n", id);
515 /* Returns a pointer to the clock source register for a peripheral */
516 static u32 *get_periph_source_reg(enum periph_id periph_id)
518 struct clk_rst_ctlr *clkrst =
519 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
520 enum periphc_internal_id internal_id;
522 assert(clock_periph_id_isvalid(periph_id));
523 internal_id = periph_id_to_internal_id[periph_id];
524 assert(internal_id != -1);
525 return &clkrst->crc_clk_src[internal_id];
528 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
531 u32 *reg = get_periph_source_reg(periph_id);
536 value &= ~OUT_CLK_SOURCE_MASK;
537 value |= source << OUT_CLK_SOURCE_SHIFT;
539 value &= ~OUT_CLK_DIVISOR_MASK;
540 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
545 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
547 u32 *reg = get_periph_source_reg(periph_id);
549 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
550 source << OUT_CLK_SOURCE_SHIFT);
554 * Given the parent's rate and the required rate for the children, this works
555 * out the peripheral clock divider to use, in 7.1 binary format.
557 * @param divider_bits number of divider bits (8 or 16)
558 * @param parent_rate clock rate of parent clock in Hz
559 * @param rate required clock rate for this clock
560 * @return divider which should be used
562 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
565 u64 divider = parent_rate * 2;
566 unsigned max_divider = 1 << divider_bits;
569 do_div(divider, rate);
571 if ((s64)divider - 2 < 0)
574 if ((s64)divider - 2 >= max_divider)
581 * Given the parent's rate and the divider in 7.1 format, this works out the
582 * resulting peripheral clock rate.
584 * @param parent_rate clock rate of parent clock in Hz
585 * @param divider which should be used in 7.1 format
586 * @return effective clock rate of peripheral
588 static unsigned long get_rate_from_divider(unsigned long parent_rate,
593 rate = (u64)parent_rate * 2;
594 do_div(rate, divider + 2);
598 unsigned long clock_get_periph_rate(enum periph_id periph_id,
599 enum clock_id parent)
601 u32 *reg = get_periph_source_reg(periph_id);
603 return get_rate_from_divider(pll_rate[parent],
604 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
608 * Find the best available 7.1 format divisor given a parent clock rate and
609 * required child clock rate. This function assumes that a second-stage
610 * divisor is available which can divide by powers of 2 from 1 to 256.
612 * @param divider_bits number of divider bits (8 or 16)
613 * @param parent_rate clock rate of parent clock in Hz
614 * @param rate required clock rate for this clock
615 * @param extra_div value for the second-stage divisor (not set if this
616 * function returns -1.
617 * @return divider which should be used, or -1 if nothing is valid
620 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
621 unsigned long rate, int *extra_div)
624 int best_divider = -1;
625 int best_error = rate;
627 /* try dividers from 1 to 256 and find closest match */
628 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
629 unsigned divided_parent = parent_rate >> shift;
630 int divider = clk_get_divider(divider_bits, divided_parent,
632 unsigned effective_rate = get_rate_from_divider(divided_parent,
634 int error = rate - effective_rate;
636 /* Given a valid divider, look for the lowest error */
637 if (divider != -1 && error < best_error) {
639 *extra_div = 1 << shift;
640 best_divider = divider;
644 /* return what we found - *extra_div will already be set */
649 * Given a peripheral ID and the required source clock, this returns which
650 * value should be programmed into the source mux for that peripheral.
652 * There is special code here to handle the one source type with 5 sources.
654 * @param periph_id peripheral to start
655 * @param source PLL id of required parent clock
656 * @param mux_bits Set to number of bits in mux register: 2 or 4
657 * @param divider_bits Set to number of divider bits (8 or 16)
658 * @return mux value (0-4, or -1 if not found)
660 static int get_periph_clock_source(enum periph_id periph_id,
661 enum clock_id parent, int *mux_bits, int *divider_bits)
663 enum clock_type_id type;
664 enum periphc_internal_id internal_id;
667 assert(clock_periph_id_isvalid(periph_id));
669 internal_id = periph_id_to_internal_id[periph_id];
670 assert(periphc_internal_id_isvalid(internal_id));
672 type = clock_periph_type[internal_id];
673 assert(clock_type_id_isvalid(type));
676 * Special cases here for the clock with a 4-bit source mux and I2C
677 * with its 16-bit divisor
679 if (type == CLOCK_TYPE_PCXTS)
683 if (type == CLOCK_TYPE_PCMT16)
688 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
689 if (clock_source[type][mux] == parent)
693 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
694 * which is not in our table. If not, then they are asking for a
695 * source which this peripheral can't access through its mux.
697 assert(type == CLOCK_TYPE_PCXTS);
698 assert(parent == CLOCK_ID_SFROM32KHZ);
699 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
700 return 4; /* mux value for this clock */
702 /* if we get here, either us or the caller has made a mistake */
703 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
709 * Adjust peripheral PLL to use the given divider and source.
711 * @param periph_id peripheral to adjust
712 * @param source Source number (0-3 or 0-7)
713 * @param mux_bits Number of mux bits (2 or 4)
714 * @param divider Required divider in 7.1 or 15.1 format
715 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
716 * for this peripheral)
718 static int adjust_periph_pll(enum periph_id periph_id, int source,
719 int mux_bits, unsigned divider)
721 u32 *reg = get_periph_source_reg(periph_id);
723 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
724 divider << OUT_CLK_DIVISOR_SHIFT);
727 /* work out the source clock and set it */
731 clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
732 source << OUT_CLK_SOURCE4_SHIFT);
734 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
735 source << OUT_CLK_SOURCE_SHIFT);
741 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
742 enum clock_id parent, unsigned rate, int *extra_div)
744 unsigned effective_rate;
745 int mux_bits, divider_bits, source;
748 /* work out the source clock and set it */
749 source = get_periph_clock_source(periph_id, parent, &mux_bits,
753 divider = find_best_divider(divider_bits, pll_rate[parent],
756 divider = clk_get_divider(divider_bits, pll_rate[parent],
758 assert(divider >= 0);
759 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
761 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
762 get_periph_source_reg(periph_id),
763 readl(get_periph_source_reg(periph_id)));
765 /* Check what we ended up with. This shouldn't matter though */
766 effective_rate = clock_get_periph_rate(periph_id, parent);
768 effective_rate /= *extra_div;
769 if (rate != effective_rate)
770 debug("Requested clock rate %u not honored (got %u)\n",
771 rate, effective_rate);
772 return effective_rate;
775 unsigned clock_start_periph_pll(enum periph_id periph_id,
776 enum clock_id parent, unsigned rate)
778 unsigned effective_rate;
780 reset_set_enable(periph_id, 1);
781 clock_enable(periph_id);
783 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
786 reset_set_enable(periph_id, 0);
787 return effective_rate;
790 void clock_set_enable(enum periph_id periph_id, int enable)
792 struct clk_rst_ctlr *clkrst =
793 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
794 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
797 /* Enable/disable the clock to this peripheral */
798 assert(clock_periph_id_isvalid(periph_id));
801 reg |= PERIPH_MASK(periph_id);
803 reg &= ~PERIPH_MASK(periph_id);
807 void clock_enable(enum periph_id clkid)
809 clock_set_enable(clkid, 1);
812 void clock_disable(enum periph_id clkid)
814 clock_set_enable(clkid, 0);
817 void reset_set_enable(enum periph_id periph_id, int enable)
819 struct clk_rst_ctlr *clkrst =
820 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
821 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
824 /* Enable/disable reset to the peripheral */
825 assert(clock_periph_id_isvalid(periph_id));
828 reg |= PERIPH_MASK(periph_id);
830 reg &= ~PERIPH_MASK(periph_id);
834 void reset_periph(enum periph_id periph_id, int us_delay)
836 /* Put peripheral into reset */
837 reset_set_enable(periph_id, 1);
841 reset_set_enable(periph_id, 0);
846 void reset_cmplx_set_enable(int cpu, int which, int reset)
848 struct clk_rst_ctlr *clkrst =
849 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
852 /* Form the mask, which depends on the cpu chosen. Tegra20 has 2 */
853 assert(cpu >= 0 && cpu < 2);
856 /* either enable or disable those reset for that CPU */
858 writel(mask, &clkrst->crc_cpu_cmplx_set);
860 writel(mask, &clkrst->crc_cpu_cmplx_clr);
863 unsigned clock_get_rate(enum clock_id clkid)
871 parent_rate = osc_freq[clock_get_osc_freq()];
872 if (clkid == CLOCK_ID_OSC)
875 pll = get_pll(clkid);
876 base = readl(&pll->pll_base);
878 /* Oh for bf_unpack()... */
879 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
880 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
881 if (clkid == CLOCK_ID_USB)
882 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
884 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
890 * Set the output frequency you want for each PLL clock.
891 * PLL output frequencies are programmed by setting their N, M and P values.
892 * The governing equations are:
893 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
894 * where Fo is the output frequency from the PLL.
895 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
896 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
897 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
899 * @param n PLL feedback divider(DIVN)
900 * @param m PLL input divider(DIVN)
901 * @param p post divider(DIVP)
902 * @param cpcon base PLL charge pump(CPCON)
903 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
904 * be overriden), 1 if PLL is already correct
906 static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
912 pll = get_pll(clkid);
914 base_reg = readl(&pll->pll_base);
916 /* Set BYPASS, m, n and p to PLL_BASE */
917 base_reg &= ~PLL_DIVM_MASK;
918 base_reg |= m << PLL_DIVM_SHIFT;
920 base_reg &= ~PLL_DIVN_MASK;
921 base_reg |= n << PLL_DIVN_SHIFT;
923 base_reg &= ~PLL_DIVP_MASK;
924 base_reg |= p << PLL_DIVP_SHIFT;
926 if (clkid == CLOCK_ID_PERIPH) {
928 * If the PLL is already set up, check that it is correct
929 * and record this info for clock_verify() to check.
931 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
932 base_reg |= PLL_ENABLE_MASK;
933 if (base_reg != readl(&pll->pll_base))
935 return pllp_valid ? 1 : -1;
937 base_reg |= PLL_BASE_OVRRIDE_MASK;
940 base_reg |= PLL_BYPASS_MASK;
941 writel(base_reg, &pll->pll_base);
943 /* Set cpcon to PLL_MISC */
944 misc_reg = readl(&pll->pll_misc);
945 misc_reg &= ~PLL_CPCON_MASK;
946 misc_reg |= cpcon << PLL_CPCON_SHIFT;
947 writel(misc_reg, &pll->pll_misc);
950 base_reg |= PLL_ENABLE_MASK;
951 writel(base_reg, &pll->pll_base);
954 base_reg &= ~PLL_BYPASS_MASK;
955 writel(base_reg, &pll->pll_base);
960 void clock_ll_start_uart(enum periph_id periph_id)
962 /* Assert UART reset and enable clock */
963 reset_set_enable(periph_id, 1);
964 clock_enable(periph_id);
965 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
970 /* De-assert reset to UART */
971 reset_set_enable(periph_id, 0);
974 #ifdef CONFIG_OF_CONTROL
976 * Convert a device tree clock ID to our peripheral ID. They are mostly
977 * the same but we are very cautious so we check that a valid clock ID is
980 * @param clk_id Clock ID according to tegra20 device tree binding
981 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
983 static enum periph_id clk_id_to_periph_id(int clk_id)
986 return PERIPH_ID_NONE;
1009 return PERIPH_ID_NONE;
1015 int clock_decode_periph_id(const void *blob, int node)
1021 err = fdtdec_get_int_array(blob, node, "clocks", cell,
1025 id = clk_id_to_periph_id(cell[1]);
1026 assert(clock_periph_id_isvalid(id));
1029 #endif /* CONFIG_OF_CONTROL */
1031 int clock_verify(void)
1033 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
1034 u32 reg = readl(&pll->pll_base);
1037 printf("Warning: PLLP %x is not correct\n", reg);
1040 debug("PLLX %x is correct\n", reg);
1044 void clock_early_init(void)
1047 * PLLP output frequency set to 216MHz
1048 * PLLC output frequency set to 600Mhz
1050 * TODO: Can we calculate these values instead of hard-coding?
1052 switch (clock_get_osc_freq()) {
1053 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
1054 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
1055 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
1058 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
1059 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
1060 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
1063 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
1064 clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
1065 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
1067 case CLOCK_OSC_FREQ_19_2:
1070 * These are not supported. It is too early to print a
1071 * message and the UART likely won't work anyway due to the
1072 * oscillator being wrong.
1078 void clock_init(void)
1080 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
1081 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
1082 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
1083 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
1084 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
1085 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
1086 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
1087 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);