arch/arm/include/asm/arch-am33xx/hardware_am43xx.h

   1 /*
   2  * hardware_am43xx.h
   3  *
   4  * AM43xx hardware specific header
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __AM43XX_HARDWARE_AM43XX_H
  12 #define __AM43XX_HARDWARE_AM43XX_H
  13
  14 /* Module base addresses */
  15
  16 /* L3 Fast Configuration Bandwidth Limiter Base Address */
  17 #define L3F_CFG_BWLIMITER               0x44005200
  18
  19 /* UART Base Address */
  20 #define UART0_BASE                      0x44E09000
  21
  22 /* GPIO Base address */
  23 #define GPIO2_BASE                      0x481AC000
  24
  25 /* Watchdog Timer */
  26 #define WDT_BASE                        0x44E35000
  27
  28 /* Control Module Base Address */
  29 #define CTRL_BASE                       0x44E10000
  30 #define CTRL_DEVICE_BASE                0x44E10600
  31
  32 /* PRCM Base Address */
  33 #define PRCM_BASE                       0x44DF0000
  34 #define CM_WKUP                         0x44DF2800
  35 #define CM_PER                          0x44DF8800
  36 #define CM_DPLL                         0x44DF4200
  37 #define CM_RTC                          0x44DF8500
  38
  39 #define PRM_RSTCTRL                     (PRCM_BASE + 0x4000)
  40 #define PRM_RSTST                       (PRM_RSTCTRL + 4)
  41
  42 /* VTP Base address */
  43 #define VTP0_CTRL_ADDR                  0x44E10E0C
  44 #define VTP1_CTRL_ADDR                  0x48140E10
  45
  46 /* USB CTRL Base Address */
  47 #define USB1_CTRL                       0x44e10628
  48 #define USB1_CTRL_CM_PWRDN              BIT(0)
  49 #define USB1_CTRL_OTG_PWRDN             BIT(1)
  50
  51 /* DDR Base address */
  52 #define DDR_PHY_CMD_ADDR                0x44E12000
  53 #define DDR_PHY_DATA_ADDR               0x44E120C8
  54 #define DDR_PHY_CMD_ADDR2               0x47C0C800
  55 #define DDR_PHY_DATA_ADDR2              0x47C0C8C8
  56 #define DDR_DATA_REGS_NR                2
  57
  58 /* CPSW Config space */
  59 #define CPSW_MDIO_BASE                  0x4A101000
  60
  61 /* RTC base address */
  62 #define RTC_BASE                        0x44E3E000
  63
  64 /* USB OTG */
  65 #define USB_OTG_SS1_BASE                0x48390000
  66 #define USB_OTG_SS1_GLUE_BASE           0x48380000
  67 #define USB2_PHY1_POWER                 0x44E10620
  68
  69 #define USB_OTG_SS2_BASE                0x483D0000
  70 #define USB_OTG_SS2_GLUE_BASE           0x483C0000
  71 #define USB2_PHY2_POWER                 0x44E10628
  72
  73 /* USB Clock Control */
  74 #define PRM_PER_USB_OTG_SS0_CLKCTRL (CM_PER + 0x260)
  75 #define PRM_PER_USB_OTG_SS1_CLKCTRL (CM_PER + 0x268)
  76 #define USBOTGSSX_CLKCTRL_MODULE_EN     (1 << 1)
  77 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960 (1 << 8)
  78
  79 #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8)
  80 #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0)
  81 #define USBPHYOCPSCP_MODULE_EN  (1 << 1)
  82 #define CM_DEVICE_INST                  0x44df4100
  83 #define PRM_DEVICE_INST                 0x44df4000
  84
  85 #define USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960   (1 << 8)
  86 #define USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K        (1 << 8)
  87
  88 /* Control status register */
  89 #define CTRL_CRYSTAL_FREQ_SRC_MASK              (1 << 31)
  90 #define CTRL_CRYSTAL_FREQ_SRC_SHIFT             31
  91 #define CTRL_CRYSTAL_FREQ_SELECTION_MASK        (0x3 << 29)
  92 #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT       29
  93 #define CTRL_SYSBOOT_15_14_MASK                 (0x3 << 22)
  94 #define CTRL_SYSBOOT_15_14_SHIFT                22
  95
  96 #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT           0x0
  97 #define CTRL_CRYSTAL_FREQ_SRC_EFUSE             0x1
  98
  99 #define NUM_CRYSTAL_FREQ                        0x4
 100
 101 #endif /* __AM43XX_HARDWARE_AM43XX_H */