2 * (C) Copyright 2012 Stephen Warren
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _BCM2835_MBOX_H
8 #define _BCM2835_MBOX_H
10 #include <linux/compiler.h>
13 * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU")
14 * and the ARM CPU. The ARM CPU is often thought of as the main CPU.
15 * However, the VideoCore actually controls the initial SoC boot, and hides
16 * much of the hardware behind a protocol. This protocol is transported
17 * using the SoC's mailbox hardware module.
19 * The mailbox hardware supports passing 32-bit values back and forth.
20 * Presumably by software convention of the firmware, the bottom 4 bits of the
21 * value are used to indicate a logical channel, and the upper 28 bits are the
22 * actual payload. Various channels exist using these simple raw messages. See
23 * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an
24 * example, the messages on the power management channel are a bitmask of
25 * devices whose power should be enabled.
27 * The property mailbox channel passes messages that contain the (16-byte
28 * aligned) ARM physical address of a memory buffer. This buffer is passed to
29 * the VC for processing, is modified in-place by the VC, and the address then
30 * passed back to the ARM CPU as the response mailbox message to indicate
31 * request completion. The buffers have a generic and extensible format; each
32 * buffer contains a standard header, a list of "tags", and a terminating zero
33 * entry. Each tag contains an ID indicating its type, and length fields for
34 * generic parsing. With some limitations, an arbitrary set of tags may be
35 * combined together into a single message buffer. This file defines structs
36 * representing the header and many individual tag layouts and IDs.
41 #define BCM2835_MBOX_PHYSADDR 0x2000b880
43 struct bcm2835_mbox_regs {
51 #define BCM2835_MBOX_STATUS_WR_FULL 0x80000000
52 #define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000
54 /* Lower 4-bits are channel ID */
55 #define BCM2835_CHAN_MASK 0xf
56 #define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \
57 (chan & BCM2835_CHAN_MASK))
58 #define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK)
59 #define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK))
61 /* Property mailbox buffer structures */
63 #define BCM2835_MBOX_PROP_CHAN 8
65 /* All message buffers must start with this header */
66 struct bcm2835_mbox_hdr {
71 #define BCM2835_MBOX_REQ_CODE 0
72 #define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000
74 #define BCM2835_MBOX_INIT_HDR(_m_) { \
75 memset((_m_), 0, sizeof(*(_m_))); \
76 (_m_)->hdr.buf_size = sizeof(*(_m_)); \
77 (_m_)->hdr.code = 0; \
82 * A message buffer contains a list of tags. Each tag must also start with
83 * a standardized header.
85 struct bcm2835_mbox_tag_hdr {
91 #define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \
92 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
93 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
94 (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \
97 #define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \
98 (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \
99 (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \
100 (_t_)->tag_hdr.val_len = 0; \
103 /* When responding, the VC sets this bit in val_len to indicate a response */
104 #define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000
107 * Below we define the ID and struct for many possible tags. This header only
108 * defines individual tag structs, not entire message structs, since in
109 * general an arbitrary set of tags may be combined into a single message.
110 * Clients of the mbox API are expected to define their own overall message
111 * structures by combining the header, a set of tags, and a terminating
112 * entry. For example,
115 * struct bcm2835_mbox_hdr hdr;
116 * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
117 * ... perhaps other tags here ...
122 #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005
124 struct bcm2835_mbox_tag_get_arm_mem {
125 struct bcm2835_mbox_tag_hdr tag_hdr;
136 #define BCM2835_MBOX_POWER_DEVID_SDHCI 0
137 #define BCM2835_MBOX_POWER_DEVID_UART0 1
138 #define BCM2835_MBOX_POWER_DEVID_UART1 2
139 #define BCM2835_MBOX_POWER_DEVID_USB_HCD 3
140 #define BCM2835_MBOX_POWER_DEVID_I2C0 4
141 #define BCM2835_MBOX_POWER_DEVID_I2C1 5
142 #define BCM2835_MBOX_POWER_DEVID_I2C2 6
143 #define BCM2835_MBOX_POWER_DEVID_SPI 7
144 #define BCM2835_MBOX_POWER_DEVID_CCP2TX 8
146 #define BCM2835_MBOX_POWER_STATE_RESP_ON (1 << 0)
147 /* Device doesn't exist */
148 #define BCM2835_MBOX_POWER_STATE_RESP_NODEV (1 << 1)
150 #define BCM2835_MBOX_TAG_GET_POWER_STATE 0x00020001
152 struct bcm2835_mbox_tag_get_power_state {
153 struct bcm2835_mbox_tag_hdr tag_hdr;
165 #define BCM2835_MBOX_TAG_SET_POWER_STATE 0x00028001
167 #define BCM2835_MBOX_SET_POWER_STATE_REQ_ON (1 << 0)
168 #define BCM2835_MBOX_SET_POWER_STATE_REQ_WAIT (1 << 1)
170 struct bcm2835_mbox_tag_set_power_state {
171 struct bcm2835_mbox_tag_hdr tag_hdr;
184 #define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002
186 #define BCM2835_MBOX_CLOCK_ID_EMMC 1
187 #define BCM2835_MBOX_CLOCK_ID_UART 2
188 #define BCM2835_MBOX_CLOCK_ID_ARM 3
189 #define BCM2835_MBOX_CLOCK_ID_CORE 4
190 #define BCM2835_MBOX_CLOCK_ID_V3D 5
191 #define BCM2835_MBOX_CLOCK_ID_H264 6
192 #define BCM2835_MBOX_CLOCK_ID_ISP 7
193 #define BCM2835_MBOX_CLOCK_ID_SDRAM 8
194 #define BCM2835_MBOX_CLOCK_ID_PIXEL 9
195 #define BCM2835_MBOX_CLOCK_ID_PWM 10
197 struct bcm2835_mbox_tag_get_clock_rate {
198 struct bcm2835_mbox_tag_hdr tag_hdr;
210 #define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001
212 struct bcm2835_mbox_tag_allocate_buffer {
213 struct bcm2835_mbox_tag_hdr tag_hdr;
225 #define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001
227 struct bcm2835_mbox_tag_release_buffer {
228 struct bcm2835_mbox_tag_hdr tag_hdr;
237 #define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002
239 struct bcm2835_mbox_tag_blank_screen {
240 struct bcm2835_mbox_tag_hdr tag_hdr;
243 /* bit 0 means on, other bots reserved */
252 /* Physical means output signal */
253 #define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003
254 #define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003
255 #define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003
257 struct bcm2835_mbox_tag_physical_w_h {
258 struct bcm2835_mbox_tag_hdr tag_hdr;
260 /* req not used for get */
272 /* Virtual means display buffer */
273 #define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004
274 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004
275 #define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004
277 struct bcm2835_mbox_tag_virtual_w_h {
278 struct bcm2835_mbox_tag_hdr tag_hdr;
280 /* req not used for get */
292 #define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005
293 #define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005
294 #define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005
296 struct bcm2835_mbox_tag_depth {
297 struct bcm2835_mbox_tag_hdr tag_hdr;
299 /* req not used for get */
309 #define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006
310 #define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005
311 #define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006
313 #define BCM2835_MBOX_PIXEL_ORDER_BGR 0
314 #define BCM2835_MBOX_PIXEL_ORDER_RGB 1
316 struct bcm2835_mbox_tag_pixel_order {
317 struct bcm2835_mbox_tag_hdr tag_hdr;
319 /* req not used for get */
329 #define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007
330 #define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007
331 #define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007
333 #define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0
334 #define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1
335 #define BCM2835_MBOX_ALPHA_MODE_IGNORED 2
337 struct bcm2835_mbox_tag_alpha_mode {
338 struct bcm2835_mbox_tag_hdr tag_hdr;
340 /* req not used for get */
350 #define BCM2835_MBOX_TAG_GET_PITCH 0x00040008
352 struct bcm2835_mbox_tag_pitch {
353 struct bcm2835_mbox_tag_hdr tag_hdr;
363 /* Offset of display window within buffer */
364 #define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009
365 #define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009
366 #define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009
368 struct bcm2835_mbox_tag_virtual_offset {
369 struct bcm2835_mbox_tag_hdr tag_hdr;
371 /* req not used for get */
383 #define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a
384 #define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a
385 #define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a
387 struct bcm2835_mbox_tag_overscan {
388 struct bcm2835_mbox_tag_hdr tag_hdr;
390 /* req not used for get */
406 #define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b
408 struct bcm2835_mbox_tag_get_palette {
409 struct bcm2835_mbox_tag_hdr tag_hdr;
419 #define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b
421 struct bcm2835_mbox_tag_test_palette {
422 struct bcm2835_mbox_tag_hdr tag_hdr;
435 #define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b
437 struct bcm2835_mbox_tag_set_palette {
438 struct bcm2835_mbox_tag_hdr tag_hdr;
452 * Pass a raw u32 message to the VC, and receive a raw u32 back.
454 * Returns 0 for success, any other value for error.
456 int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv);
459 * Pass a complete property-style buffer to the VC, and wait until it has
462 * This function expects a pointer to the mbox_hdr structure in an attempt
463 * to ensure some degree of type safety. However, some number of tags and
464 * a termination value are expected to immediately follow the header in
465 * memory, as required by the property protocol.
467 * Returns 0 for success, any other value for error.
469 int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer);