2 * Freescale i.MX28 LCDIF Register Definitions
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * SPDX-License-Identifier: GPL-2.0+
13 #ifndef __MX28_REGS_LCDIF_H__
14 #define __MX28_REGS_LCDIF_H__
16 #include <asm/imx-common/regs-common.h>
19 struct mxs_lcdif_regs {
20 mxs_reg_32(hw_lcdif_ctrl); /* 0x00 */
21 mxs_reg_32(hw_lcdif_ctrl1); /* 0x10 */
22 #if defined(CONFIG_SOC_MX28)
23 mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
24 #endif /* MX23/MX28 */
25 mxs_reg_32(hw_lcdif_transfer_count); /* 0x20/0x30 */
26 mxs_reg_32(hw_lcdif_cur_buf); /* 0x30/0x40 */
27 mxs_reg_32(hw_lcdif_next_buf); /* 0x40/0x50 */
29 #if defined(CONFIG_SOC_MX23)
30 reg_32(reserved1); /* 0x50 */
33 mxs_reg_32(hw_lcdif_timing); /* 0x60 */
34 mxs_reg_32(hw_lcdif_vdctrl0); /* 0x70 */
35 mxs_reg_32(hw_lcdif_vdctrl1); /* 0x80 */
36 mxs_reg_32(hw_lcdif_vdctrl2); /* 0x90 */
37 mxs_reg_32(hw_lcdif_vdctrl3); /* 0xa0 */
38 mxs_reg_32(hw_lcdif_vdctrl4); /* 0xb0 */
39 mxs_reg_32(hw_lcdif_dvictrl0); /* 0xc0 */
40 mxs_reg_32(hw_lcdif_dvictrl1); /* 0xd0 */
41 mxs_reg_32(hw_lcdif_dvictrl2); /* 0xe0 */
42 mxs_reg_32(hw_lcdif_dvictrl3); /* 0xf0 */
43 mxs_reg_32(hw_lcdif_dvictrl4); /* 0x100 */
44 mxs_reg_32(hw_lcdif_csc_coeffctrl0); /* 0x110 */
45 mxs_reg_32(hw_lcdif_csc_coeffctrl1); /* 0x120 */
46 mxs_reg_32(hw_lcdif_csc_coeffctrl2); /* 0x130 */
47 mxs_reg_32(hw_lcdif_csc_coeffctrl3); /* 0x140 */
48 mxs_reg_32(hw_lcdif_csc_coeffctrl4); /* 0x150 */
49 mxs_reg_32(hw_lcdif_csc_offset); /* 0x160 */
50 mxs_reg_32(hw_lcdif_csc_limit); /* 0x170 */
52 #if defined(CONFIG_SOC_MX23)
53 reg_32(reserved2[3]); /* 0x180-0x1a0 */
54 #endif /* MX23/MX28 */
55 mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */
56 mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */
57 #if defined(CONFIG_SOC_MX28)
58 mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
60 mxs_reg_32(hw_lcdif_lcdif_stat); /* 0x1d0/0x1b0 */
61 mxs_reg_32(hw_lcdif_version); /* 0x1e0/0x1c0 */
62 mxs_reg_32(hw_lcdif_debug0); /* 0x1f0/0x1d0 */
63 mxs_reg_32(hw_lcdif_debug1); /* 0x200/0x1e0 */
64 mxs_reg_32(hw_lcdif_debug2); /* 0x1f0 */
68 #define LCDIF_CTRL_SFTRST (1 << 31)
69 #define LCDIF_CTRL_CLKGATE (1 << 30)
70 #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
71 #define LCDIF_CTRL_READ_WRITEB (1 << 28)
72 #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
73 #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
74 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
75 #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
76 #define LCDIF_CTRL_DVI_MODE (1 << 20)
77 #define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
78 #define LCDIF_CTRL_VSYNC_MODE (1 << 18)
79 #define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
80 #define LCDIF_CTRL_DATA_SELECT (1 << 16)
81 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
82 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
83 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
84 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
85 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
86 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
87 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
88 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
89 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
90 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
91 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
92 #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
93 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
94 #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
95 #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
96 #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
97 #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
98 #define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
99 #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
100 #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
101 #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
102 #define LCDIF_CTRL_RUN (1 << 0)
104 #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
105 #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
106 #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
107 #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
108 #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
109 #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
110 #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
111 #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
112 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
113 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
114 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n) (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \
115 LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
116 #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
117 #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
118 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
119 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
120 #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
121 #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
122 #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
123 #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
124 #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
125 #define LCDIF_CTRL1_MODE86 (1 << 1)
126 #define LCDIF_CTRL1_RESET (1 << 0)
128 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
129 #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
130 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
131 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
132 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
133 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
134 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
135 #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
136 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
137 #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
138 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
139 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
140 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
141 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
142 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
143 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
144 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
145 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
146 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
147 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
148 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
149 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
150 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
151 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
152 #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
153 #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
154 #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
155 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
156 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
157 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
158 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
160 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
161 #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
162 #define LCDIF_TRANSFER_COUNT_V_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \
163 LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
164 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
165 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
166 #define LCDIF_TRANSFER_COUNT_H_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \
167 LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
169 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
170 #define LCDIF_CUR_BUF_ADDR_OFFSET 0
172 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
173 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0
175 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
176 #define LCDIF_TIMING_CMD_HOLD_OFFSET 24
177 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
178 #define LCDIF_TIMING_CMD_SETUP_OFFSET 16
179 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
180 #define LCDIF_TIMING_DATA_HOLD_OFFSET 8
181 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
182 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0
184 #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
185 #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
186 #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
187 #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
188 #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
189 #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
190 #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
191 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
192 #define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
193 #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
194 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
195 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
196 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \
197 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
199 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
200 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
201 #define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
202 LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
204 #if defined(CONFIG_SOC_MX23)
205 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24)
206 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 24
207 #elif defined(CONFIG_SOC_MX28)
208 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
209 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
211 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \
212 LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
213 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
214 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
215 #define LCDIF_VDCTRL2_HSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \
216 LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
218 #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
219 #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
220 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
221 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
222 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \
223 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
224 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
225 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
226 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \
227 LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
229 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
230 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
231 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n) (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \
232 LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
233 #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
234 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
235 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
236 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n) (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \
237 LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
239 #endif /* __MX28_REGS_LCDIF_H__ */