arch/arm/include/asm/arch-omap3/cpu.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  */
  24
  25 #ifndef _CPU_H
  26 #define _CPU_H
  27
  28 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
  29 #include <asm/types.h>
  30 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
  31
  32 /* Register offsets of common modules */
  33 /* Control */
  34 #ifndef __KERNEL_STRICT_NAMES
  35 #ifndef __ASSEMBLY__
  36 struct ctrl {
  37         u8 res1[0xC0];
  38         u16 gpmc_nadv_ale;      /* 0xC0 */
  39         u16 gpmc_noe;           /* 0xC2 */
  40         u16 gpmc_nwe;           /* 0xC4 */
  41         u8 res2[0x22A];
  42         u32 status;             /* 0x2F0 */
  43         u32 gpstatus;           /* 0x2F4 */
  44         u8 res3[0x08];
  45         u32 rpubkey_0;          /* 0x300 */
  46         u32 rpubkey_1;          /* 0x304 */
  47         u32 rpubkey_2;          /* 0x308 */
  48         u32 rpubkey_3;          /* 0x30C */
  49         u32 rpubkey_4;          /* 0x310 */
  50         u8 res4[0x04];
  51         u32 randkey_0;          /* 0x318 */
  52         u32 randkey_1;          /* 0x31C */
  53         u32 randkey_2;          /* 0x320 */
  54         u32 randkey_3;          /* 0x324 */
  55         u8 res5[0x124];
  56         u32 ctrl_omap_stat;     /* 0x44C */
  57 };
  58 #else /* __ASSEMBLY__ */
  59 #define CONTROL_STATUS          0x2F0
  60 #endif /* __ASSEMBLY__ */
  61 #endif /* __KERNEL_STRICT_NAMES */
  62
  63 #ifndef __KERNEL_STRICT_NAMES
  64 #ifndef __ASSEMBLY__
  65 struct ctrl_id {
  66         u8 res1[0x4];
  67         u32 idcode;             /* 0x04 */
  68         u32 prod_id;            /* 0x08 */
  69         u32 sku_id;             /* 0x0c */
  70         u8 res2[0x08];
  71         u32 die_id_0;           /* 0x18 */
  72         u32 die_id_1;           /* 0x1C */
  73         u32 die_id_2;           /* 0x20 */
  74         u32 die_id_3;           /* 0x24 */
  75 };
  76 #endif /* __ASSEMBLY__ */
  77 #endif /* __KERNEL_STRICT_NAMES */
  78
  79 /* device type */
  80 #define DEVICE_MASK             (0x7 << 8)
  81 #define SYSBOOT_MASK            0x1F
  82 #define TST_DEVICE              0x0
  83 #define EMU_DEVICE              0x1
  84 #define HS_DEVICE               0x2
  85 #define GP_DEVICE               0x3
  86
  87 /* device speed */
  88 #define SKUID_CLK_MASK          0xf
  89 #define SKUID_CLK_600MHZ        0x0
  90 #define SKUID_CLK_720MHZ        0x8
  91
  92 #define GPMC_BASE               (OMAP34XX_GPMC_BASE)
  93 #define GPMC_CONFIG_CS0         0x60
  94 #define GPMC_CONFIG_CS0_BASE    (GPMC_BASE + GPMC_CONFIG_CS0)
  95
  96 #ifndef __KERNEL_STRICT_NAMES
  97 #ifndef __ASSEMBLY__
  98 struct gpmc_cs {
  99         u32 config1;            /* 0x00 */
 100         u32 config2;            /* 0x04 */
 101         u32 config3;            /* 0x08 */
 102         u32 config4;            /* 0x0C */
 103         u32 config5;            /* 0x10 */
 104         u32 config6;            /* 0x14 */
 105         u32 config7;            /* 0x18 */
 106         u32 nand_cmd;           /* 0x1C */
 107         u32 nand_adr;           /* 0x20 */
 108         u32 nand_dat;           /* 0x24 */
 109         u8 res[8];              /* blow up to 0x30 byte */
 110 };
 111
 112 struct bch_res_0_3 {
 113         u32 bch_result_x[4];
 114 };
 115
 116 struct gpmc {
 117         u8 res1[0x10];
 118         u32 sysconfig;          /* 0x10 */
 119         u8 res2[0x4];
 120         u32 irqstatus;          /* 0x18 */
 121         u32 irqenable;          /* 0x1C */
 122         u8 res3[0x20];
 123         u32 timeout_control;    /* 0x40 */
 124         u8 res4[0xC];
 125         u32 config;             /* 0x50 */
 126         u32 status;             /* 0x54 */
 127         u8 res5[0x8];   /* 0x58 */
 128         struct gpmc_cs cs[8];   /* 0x60, 0x90, .. */
 129         u8 res6[0x14];          /* 0x1E0 */
 130         u32 ecc_config;         /* 0x1F4 */
 131         u32 ecc_control;        /* 0x1F8 */
 132         u32 ecc_size_config;    /* 0x1FC */
 133         u32 ecc1_result;        /* 0x200 */
 134         u32 ecc2_result;        /* 0x204 */
 135         u32 ecc3_result;        /* 0x208 */
 136         u32 ecc4_result;        /* 0x20C */
 137         u32 ecc5_result;        /* 0x210 */
 138         u32 ecc6_result;        /* 0x214 */
 139         u32 ecc7_result;        /* 0x218 */
 140         u32 ecc8_result;        /* 0x21C */
 141         u32 ecc9_result;        /* 0x220 */
 142         u8 res7[0x1C];          /* fill up to 0x240 */
 143         struct bch_res_0_3 bch_result_0_3[7];   /* 0x240 */
 144 };
 145
 146 /* Used for board specific gpmc initialization */
 147 extern struct gpmc *gpmc_cfg;
 148
 149 #else /* __ASSEMBLY__ */
 150 #define GPMC_CONFIG1            0x00
 151 #define GPMC_CONFIG2            0x04
 152 #define GPMC_CONFIG3            0x08
 153 #define GPMC_CONFIG4            0x0C
 154 #define GPMC_CONFIG5            0x10
 155 #define GPMC_CONFIG6            0x14
 156 #define GPMC_CONFIG7            0x18
 157 #endif /* __ASSEMBLY__ */
 158 #endif /* __KERNEL_STRICT_NAMES */
 159
 160 /* GPMC Mapping */
 161 #define FLASH_BASE              0x10000000      /* NOR flash, */
 162                                                 /* aligned to 256 Meg */
 163 #define FLASH_BASE_SDPV1        0x04000000      /* NOR flash, */
 164                                                 /* aligned to 64 Meg */
 165 #define FLASH_BASE_SDPV2        0x10000000      /* NOR flash, */
 166                                                 /* aligned to 256 Meg */
 167 #define DEBUG_BASE              0x08000000      /* debug board */
 168 #define NAND_BASE               0x30000000      /* NAND addr */
 169                                                 /* (actual size small port) */
 170 #define PISMO2_BASE             0x18000000      /* PISMO2 CS1/2 */
 171 #define ONENAND_MAP             0x20000000      /* OneNand addr */
 172                                                 /* (actual size small port) */
 173 /* SMS */
 174 #ifndef __KERNEL_STRICT_NAMES
 175 #ifndef __ASSEMBLY__
 176 struct sms {
 177         u8 res1[0x10];
 178         u32 sysconfig;          /* 0x10 */
 179         u8 res2[0x34];
 180         u32 rg_att0;            /* 0x48 */
 181         u8 res3[0x84];
 182         u32 class_arb0;         /* 0xD0 */
 183 };
 184 #endif /* __ASSEMBLY__ */
 185 #endif /* __KERNEL_STRICT_NAMES */
 186
 187 #define BURSTCOMPLETE_GROUP7    (0x1 << 31)
 188
 189 /* SDRC */
 190 #ifndef __KERNEL_STRICT_NAMES
 191 #ifndef __ASSEMBLY__
 192 struct sdrc_cs {
 193         u32 mcfg;               /* 0x80 || 0xB0 */
 194         u32 mr;                 /* 0x84 || 0xB4 */
 195         u8 res1[0x4];
 196         u32 emr2;               /* 0x8C || 0xBC */
 197         u8 res2[0x14];
 198         u32 rfr_ctrl;           /* 0x84 || 0xD4 */
 199         u32 manual;             /* 0xA8 || 0xD8 */
 200         u8 res3[0x4];
 201 };
 202
 203 struct sdrc_actim {
 204         u32 ctrla;              /* 0x9C || 0xC4 */
 205         u32 ctrlb;              /* 0xA0 || 0xC8 */
 206 };
 207
 208 struct sdrc {
 209         u8 res1[0x10];
 210         u32 sysconfig;          /* 0x10 */
 211         u32 status;             /* 0x14 */
 212         u8 res2[0x28];
 213         u32 cs_cfg;             /* 0x40 */
 214         u32 sharing;            /* 0x44 */
 215         u8 res3[0x18];
 216         u32 dlla_ctrl;          /* 0x60 */
 217         u32 dlla_status;        /* 0x64 */
 218         u32 dllb_ctrl;          /* 0x68 */
 219         u32 dllb_status;        /* 0x6C */
 220         u32 power;              /* 0x70 */
 221         u8 res4[0xC];
 222         struct sdrc_cs cs[2];   /* 0x80 || 0xB0 */
 223 };
 224
 225 /* EMIF4 */
 226 typedef struct emif4 {
 227         unsigned int emif_mod_id_rev;
 228         unsigned int sdram_sts;
 229         unsigned int sdram_config;
 230         unsigned int res1;
 231         unsigned int sdram_refresh_ctrl;
 232         unsigned int sdram_refresh_ctrl_shdw;
 233         unsigned int sdram_time1;
 234         unsigned int sdram_time1_shdw;
 235         unsigned int sdram_time2;
 236         unsigned int sdram_time2_shdw;
 237         unsigned int sdram_time3;
 238         unsigned int sdram_time3_shdw;
 239         unsigned char res2[8];
 240         unsigned int sdram_pwr_mgmt;
 241         unsigned int sdram_pwr_mgmt_shdw;
 242         unsigned char res3[32];
 243         unsigned int sdram_iodft_tlgc;
 244         unsigned char res4[128];
 245         unsigned int ddr_phyctrl1;
 246         unsigned int ddr_phyctrl1_shdw;
 247         unsigned int ddr_phyctrl2;
 248 } emif4_t;
 249
 250 #endif /* __ASSEMBLY__ */
 251 #endif /* __KERNEL_STRICT_NAMES */
 252
 253 #define DLLPHASE_90             (0x1 << 1)
 254 #define LOADDLL                 (0x1 << 2)
 255 #define ENADLL                  (0x1 << 3)
 256 #define DLL_DELAY_MASK          0xFF00
 257 #define DLL_NO_FILTER_MASK      ((0x1 << 9) | (0x1 << 8))
 258
 259 #define PAGEPOLICY_HIGH         (0x1 << 0)
 260 #define SRFRONRESET             (0x1 << 7)
 261 #define PWDNEN                  (0x1 << 2)
 262 #define WAKEUPPROC              (0x1 << 26)
 263
 264 #define DDR_SDRAM               (0x1 << 0)
 265 #define DEEPPD                  (0x1 << 3)
 266 #define B32NOT16                (0x1 << 4)
 267 #define BANKALLOCATION          (0x2 << 6)
 268 #define RAMSIZE_128             (0x40 << 8) /* RAM size in 2MB chunks */
 269 #define ADDRMUXLEGACY           (0x1 << 19)
 270 #define CASWIDTH_10BITS         (0x5 << 20)
 271 #define RASWIDTH_13BITS         (0x2 << 24)
 272 #define BURSTLENGTH4            (0x2 << 0)
 273 #define CASL3                   (0x3 << 4)
 274 #define SDRC_ACTIM_CTRL0_BASE   (OMAP34XX_SDRC_BASE + 0x9C)
 275 #define SDRC_ACTIM_CTRL1_BASE   (OMAP34XX_SDRC_BASE + 0xC4)
 276 #define ARE_ARCV_1              (0x1 << 0)
 277 #define ARCV                    (0x4e2 << 8) /* Autorefresh count */
 278 #define OMAP34XX_SDRC_CS0       0x80000000
 279 #define OMAP34XX_SDRC_CS1       0xA0000000
 280 #define CMD_NOP                 0x0
 281 #define CMD_PRECHARGE           0x1
 282 #define CMD_AUTOREFRESH         0x2
 283 #define CMD_ENTR_PWRDOWN        0x3
 284 #define CMD_EXIT_PWRDOWN        0x4
 285 #define CMD_ENTR_SRFRSH         0x5
 286 #define CMD_CKE_HIGH            0x6
 287 #define CMD_CKE_LOW             0x7
 288 #define SOFTRESET               (0x1 << 1)
 289 #define SMART_IDLE              (0x2 << 3)
 290 #define REF_ON_IDLE             (0x1 << 6)
 291
 292 /* DMA */
 293 #ifndef __KERNEL_STRICT_NAMES
 294 #ifndef __ASSEMBLY__
 295 struct dma4_chan {
 296         u32 ccr;
 297         u32 clnk_ctrl;
 298         u32 cicr;
 299         u32 csr;
 300         u32 csdp;
 301         u32 cen;
 302         u32 cfn;
 303         u32 cssa;
 304         u32 cdsa;
 305         u32 csel;
 306         u32 csfl;
 307         u32 cdel;
 308         u32 cdfl;
 309         u32 csac;
 310         u32 cdac;
 311         u32 ccen;
 312         u32 ccfn;
 313         u32 color;
 314 };
 315
 316 struct dma4 {
 317         u32 revision;
 318         u8 res1[0x4];
 319         u32 irqstatus_l[0x4];
 320         u32 irqenable_l[0x4];
 321         u32 sysstatus;
 322         u32 ocp_sysconfig;
 323         u8 res2[0x34];
 324         u32 caps_0;
 325         u8 res3[0x4];
 326         u32 caps_2;
 327         u32 caps_3;
 328         u32 caps_4;
 329         u32 gcr;
 330         u8 res4[0x4];
 331         struct dma4_chan chan[32];
 332 };
 333
 334 #endif /*__ASSEMBLY__ */
 335 #endif /* __KERNEL_STRICT_NAMES */
 336
 337 /* timer regs offsets (32 bit regs) */
 338
 339 #ifndef __KERNEL_STRICT_NAMES
 340 #ifndef __ASSEMBLY__
 341 struct gptimer {
 342         u32 tidr;       /* 0x00 r */
 343         u8 res[0xc];
 344         u32 tiocp_cfg;  /* 0x10 rw */
 345         u32 tistat;     /* 0x14 r */
 346         u32 tisr;       /* 0x18 rw */
 347         u32 tier;       /* 0x1c rw */
 348         u32 twer;       /* 0x20 rw */
 349         u32 tclr;       /* 0x24 rw */
 350         u32 tcrr;       /* 0x28 rw */
 351         u32 tldr;       /* 0x2c rw */
 352         u32 ttgr;       /* 0x30 rw */
 353         u32 twpc;       /* 0x34 r*/
 354         u32 tmar;       /* 0x38 rw*/
 355         u32 tcar1;      /* 0x3c r */
 356         u32 tcicr;      /* 0x40 rw */
 357         u32 tcar2;      /* 0x44 r */
 358 };
 359 #endif /* __ASSEMBLY__ */
 360 #endif /* __KERNEL_STRICT_NAMES */
 361
 362 /* enable sys_clk NO-prescale /1 */
 363 #define GPT_EN                  ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
 364
 365 /* Watchdog */
 366 #ifndef __KERNEL_STRICT_NAMES
 367 #ifndef __ASSEMBLY__
 368 struct watchdog {
 369         u8 res1[0x34];
 370         u32 wwps;       /* 0x34 r */
 371         u8 res2[0x10];
 372         u32 wspr;       /* 0x48 rw */
 373 };
 374 #endif /* __ASSEMBLY__ */
 375 #endif /* __KERNEL_STRICT_NAMES */
 376
 377 #define WD_UNLOCK1              0xAAAA
 378 #define WD_UNLOCK2              0x5555
 379
 380 /* PRCM */
 381 #define PRCM_BASE               0x48004000
 382
 383 #ifndef __KERNEL_STRICT_NAMES
 384 #ifndef __ASSEMBLY__
 385 struct prcm {
 386         u32 fclken_iva2;        /* 0x00 */
 387         u32 clken_pll_iva2;     /* 0x04 */
 388         u8 res1[0x1c];
 389         u32 idlest_pll_iva2;    /* 0x24 */
 390         u8 res2[0x18];
 391         u32 clksel1_pll_iva2 ;  /* 0x40 */
 392         u32 clksel2_pll_iva2;   /* 0x44 */
 393         u8 res3[0x8bc];
 394         u32 clken_pll_mpu;      /* 0x904 */
 395         u8 res4[0x1c];
 396         u32 idlest_pll_mpu;     /* 0x924 */
 397         u8 res5[0x18];
 398         u32 clksel1_pll_mpu;    /* 0x940 */
 399         u32 clksel2_pll_mpu;    /* 0x944 */
 400         u8 res6[0xb8];
 401         u32 fclken1_core;       /* 0xa00 */
 402         u32 res_fclken2_core;
 403         u32 fclken3_core;       /* 0xa08 */
 404         u8 res7[0x4];
 405         u32 iclken1_core;       /* 0xa10 */
 406         u32 iclken2_core;       /* 0xa14 */
 407         u32 iclken3_core;       /* 0xa18 */
 408         u8 res8[0x24];
 409         u32 clksel_core;        /* 0xa40 */
 410         u8 res9[0xbc];
 411         u32 fclken_gfx;         /* 0xb00 */
 412         u8 res10[0xc];
 413         u32 iclken_gfx;         /* 0xb10 */
 414         u8 res11[0x2c];
 415         u32 clksel_gfx;         /* 0xb40 */
 416         u8 res12[0xbc];
 417         u32 fclken_wkup;        /* 0xc00 */
 418         u8 res13[0xc];
 419         u32 iclken_wkup;        /* 0xc10 */
 420         u8 res14[0xc];
 421         u32 idlest_wkup;        /* 0xc20 */
 422         u8 res15[0x1c];
 423         u32 clksel_wkup;        /* 0xc40 */
 424         u8 res16[0xbc];
 425         u32 clken_pll;          /* 0xd00 */
 426         u32 clken2_pll;         /* 0xd04 */
 427         u8 res17[0x18];
 428         u32 idlest_ckgen;       /* 0xd20 */
 429         u32 idlest2_ckgen;      /* 0xd24 */
 430         u8 res18[0x18];
 431         u32 clksel1_pll;        /* 0xd40 */
 432         u32 clksel2_pll;        /* 0xd44 */
 433         u32 clksel3_pll;        /* 0xd48 */
 434         u32 clksel4_pll;        /* 0xd4c */
 435         u32 clksel5_pll;        /* 0xd50 */
 436         u8 res19[0xac];
 437         u32 fclken_dss;         /* 0xe00 */
 438         u8 res20[0xc];
 439         u32 iclken_dss;         /* 0xe10 */
 440         u8 res21[0x2c];
 441         u32 clksel_dss;         /* 0xe40 */
 442         u8 res22[0xbc];
 443         u32 fclken_cam;         /* 0xf00 */
 444         u8 res23[0xc];
 445         u32 iclken_cam;         /* 0xf10 */
 446         u8 res24[0x2c];
 447         u32 clksel_cam;         /* 0xf40 */
 448         u8 res25[0xbc];
 449         u32 fclken_per;         /* 0x1000 */
 450         u8 res26[0xc];
 451         u32 iclken_per;         /* 0x1010 */
 452         u8 res27[0x2c];
 453         u32 clksel_per;         /* 0x1040 */
 454         u8 res28[0xfc];
 455         u32 clksel1_emu;        /* 0x1140 */
 456         u8 res29[0x2bc];
 457         u32 fclken_usbhost;     /* 0x1400 */
 458         u8 res30[0xc];
 459         u32 iclken_usbhost;     /* 0x1410 */
 460 };
 461 #else /* __ASSEMBLY__ */
 462 #define CM_CLKSEL_CORE          0x48004a40
 463 #define CM_CLKSEL_GFX           0x48004b40
 464 #define CM_CLKSEL_WKUP          0x48004c40
 465 #define CM_CLKEN_PLL            0x48004d00
 466 #define CM_CLKSEL1_PLL          0x48004d40
 467 #define CM_CLKSEL1_EMU          0x48005140
 468 #endif /* __ASSEMBLY__ */
 469 #endif /* __KERNEL_STRICT_NAMES */
 470
 471 #define PRM_BASE                0x48306000
 472
 473 #ifndef __KERNEL_STRICT_NAMES
 474 #ifndef __ASSEMBLY__
 475 struct prm {
 476         u8 res1[0xd40];
 477         u32 clksel;             /* 0xd40 */
 478         u8 res2[0x50c];
 479         u32 rstctrl;            /* 0x1250 */
 480         u8 res3[0x1c];
 481         u32 clksrc_ctrl;        /* 0x1270 */
 482 };
 483 #endif /* __ASSEMBLY__ */
 484 #endif /* __KERNEL_STRICT_NAMES */
 485
 486 #define PRM_RSTCTRL             0x48307250
 487 #define PRM_RSTCTRL_RESET       0x04
 488 #define PRM_RSTST                       0x48307258
 489 #define PRM_RSTST_WARM_RESET_MASK       0x7D2
 490 #define SYSCLKDIV_1             (0x1 << 6)
 491 #define SYSCLKDIV_2             (0x1 << 7)
 492
 493 #define CLKSEL_GPT1             (0x1 << 0)
 494
 495 #define EN_GPT1                 (0x1 << 0)
 496 #define EN_32KSYNC              (0x1 << 2)
 497
 498 #define ST_WDT2                 (0x1 << 5)
 499
 500 #define ST_MPU_CLK              (0x1 << 0)
 501
 502 #define ST_CORE_CLK             (0x1 << 0)
 503
 504 #define ST_PERIPH_CLK           (0x1 << 1)
 505
 506 #define ST_IVA2_CLK             (0x1 << 0)
 507
 508 #define RESETDONE               (0x1 << 0)
 509
 510 #define TCLR_ST                 (0x1 << 0)
 511 #define TCLR_AR                 (0x1 << 1)
 512 #define TCLR_PRE                (0x1 << 5)
 513
 514 /* SMX-APE */
 515 #define PM_RT_APE_BASE_ADDR_ARM         (SMX_APE_BASE + 0x10000)
 516 #define PM_GPMC_BASE_ADDR_ARM           (SMX_APE_BASE + 0x12400)
 517 #define PM_OCM_RAM_BASE_ADDR_ARM        (SMX_APE_BASE + 0x12800)
 518 #define PM_IVA2_BASE_ADDR_ARM           (SMX_APE_BASE + 0x14000)
 519
 520 #ifndef __KERNEL_STRICT_NAMES
 521 #ifndef __ASSEMBLY__
 522 struct pm {
 523         u8 res1[0x48];
 524         u32 req_info_permission_0;      /* 0x48 */
 525         u8 res2[0x4];
 526         u32 read_permission_0;          /* 0x50 */
 527         u8 res3[0x4];
 528         u32 wirte_permission_0;         /* 0x58 */
 529         u8 res4[0x4];
 530         u32 addr_match_1;               /* 0x58 */
 531         u8 res5[0x4];
 532         u32 req_info_permission_1;      /* 0x68 */
 533         u8 res6[0x14];
 534         u32 addr_match_2;               /* 0x80 */
 535 };
 536 #endif /*__ASSEMBLY__ */
 537 #endif /* __KERNEL_STRICT_NAMES */
 538
 539 /* Permission values for registers -Full fledged permissions to all */
 540 #define UNLOCK_1                        0xFFFFFFFF
 541 #define UNLOCK_2                        0x00000000
 542 #define UNLOCK_3                        0x0000FFFF
 543
 544 #define NOT_EARLY                       0
 545
 546 /* I2C base */
 547 #define I2C_BASE1               (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
 548 #define I2C_BASE2               (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
 549 #define I2C_BASE3               (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
 550
 551 /* MUSB base */
 552 #define MUSB_BASE               (OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
 553
 554 /* OMAP3 GPIO registers */
 555 #define OMAP_GPIO_REVISION              0x0000
 556 #define OMAP_GPIO_SYSCONFIG             0x0010
 557 #define OMAP_GPIO_SYSSTATUS             0x0014
 558 #define OMAP_GPIO_IRQSTATUS1            0x0018
 559 #define OMAP_GPIO_IRQSTATUS2            0x0028
 560 #define OMAP_GPIO_IRQENABLE2            0x002c
 561 #define OMAP_GPIO_IRQENABLE1            0x001c
 562 #define OMAP_GPIO_WAKE_EN               0x0020
 563 #define OMAP_GPIO_CTRL                  0x0030
 564 #define OMAP_GPIO_OE                    0x0034
 565 #define OMAP_GPIO_DATAIN                0x0038
 566 #define OMAP_GPIO_DATAOUT               0x003c
 567 #define OMAP_GPIO_LEVELDETECT0          0x0040
 568 #define OMAP_GPIO_LEVELDETECT1          0x0044
 569 #define OMAP_GPIO_RISINGDETECT          0x0048
 570 #define OMAP_GPIO_FALLINGDETECT         0x004c
 571 #define OMAP_GPIO_DEBOUNCE_EN           0x0050
 572 #define OMAP_GPIO_DEBOUNCE_VAL          0x0054
 573 #define OMAP_GPIO_CLEARIRQENABLE1       0x0060
 574 #define OMAP_GPIO_SETIRQENABLE1         0x0064
 575 #define OMAP_GPIO_CLEARWKUENA           0x0080
 576 #define OMAP_GPIO_SETWKUENA             0x0084
 577 #define OMAP_GPIO_CLEARDATAOUT          0x0090
 578 #define OMAP_GPIO_SETDATAOUT            0x0094
 579
 580 #endif /* _CPU_H */