2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
11 #define ZYNQ_SERIAL_BASEADDR0 0xFF000000
12 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000
14 #define ZYNQ_GEM_BASEADDR0 0xFF0B0000
15 #define ZYNQ_GEM_BASEADDR1 0xFF0C0000
16 #define ZYNQ_GEM_BASEADDR2 0xFF0D0000
17 #define ZYNQ_GEM_BASEADDR3 0xFF0E0000
19 #define ZYNQ_SPI_BASEADDR0 0xFF040000
20 #define ZYNQ_SPI_BASEADDR1 0xFF050000
22 #define ZYNQ_I2C_BASEADDR0 0xFF020000
23 #define ZYNQ_I2C_BASEADDR1 0xFF030000
25 #define ZYNQ_SDHCI_BASEADDR0 0xFF160000
26 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000
28 #define ZYNQMP_SATA_BASEADDR 0xFD0C0000
30 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
31 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
35 u32 cpu_r5_ctrl; /* 0x90 */
37 u32 timestamp_ref_ctrl; /* 0x128 */
39 u32 boot_mode; /* 0x200 */
41 u32 rst_lpd_top; /* 0x23C */
45 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
47 #define ZYNQMP_IOU_SCNTR 0xFF250000
48 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
49 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
52 u32 counter_control_register;
54 u32 base_frequency_id_register;
57 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
59 /* Bootmode setting values */
60 #define BOOT_MODES_MASK 0x0000000F
61 #define SD_MODE 0x00000003
62 #define EMMC_MODE 0x00000006
63 #define JTAG_MODE 0x00000000
65 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
67 struct iou_slcr_regs {
72 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
74 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
79 u32 rpu0_cfg; /* 0x100 */
81 u32 rpu1_cfg; /* 0x200 */
84 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
86 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
90 u32 rst_fpd_apu; /* 0x104 */
94 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
96 #define ZYNQMP_APU_BASEADDR 0xFD5C0000
100 u32 rvbar_addr0_l; /* 0x40 */
101 u32 rvbar_addr0_h; /* 0x44 */
105 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
107 /* Board version value */
108 #define ZYNQMP_CSU_VERSION_SILICON 0x0
109 #define ZYNQMP_CSU_VERSION_EP108 0x1
110 #define ZYNQMP_CSU_VERSION_VELOCE 0x2
111 #define ZYNQMP_CSU_VERSION_QEMU 0x3
113 #endif /* _ASM_ARCH_HARDWARE_H */