2 * Based on Linux i.MX iomux-v3.h file:
3 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
6 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __ASM_ARCH_IOMUX_V3_H__
12 #define __ASM_ARCH_IOMUX_V3_H__
17 * build IOMUX_PAD structure
19 * This iomux scheme is based around pads, which are the physical balls
22 * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
23 * things like driving strength and pullup/pulldown.
24 * - Each pad can have but not necessarily does have an output routing register
25 * (IOMUXC_SW_MUX_CTL_PAD_x).
26 * - Each pad can have but not necessarily does have an input routing register
27 * (IOMUXC_x_SELECT_INPUT)
29 * The three register sets do not have a fixed offset to each other,
30 * hence we order this table by pad control registers (which all pads
31 * have) and put the optional i/o routing registers into additional
34 * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
35 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
37 * IOMUX/PAD Bit field definitions
39 * MUX_CTRL_OFS: 0..11 (12)
40 * PAD_CTRL_OFS: 12..23 (12)
41 * SEL_INPUT_OFS: 24..35 (12)
42 * MUX_MODE + SION: 36..40 (5)
43 * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18)
48 typedef u64 iomux_v3_cfg_t;
50 #define MUX_CTRL_OFS_SHIFT 0
51 #define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
52 #define MUX_PAD_CTRL_OFS_SHIFT 12
53 #define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
54 MUX_PAD_CTRL_OFS_SHIFT)
55 #define MUX_SEL_INPUT_OFS_SHIFT 24
56 #define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
57 MUX_SEL_INPUT_OFS_SHIFT)
59 #define MUX_MODE_SHIFT 36
60 #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
61 #define MUX_PAD_CTRL_SHIFT 41
62 #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
63 #define MUX_SEL_INPUT_SHIFT 59
64 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
66 #define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
68 #define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID)
69 #define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \
72 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
73 sel_input, pad_ctrl) \
74 (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
75 ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
76 ((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
77 ((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
78 ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
79 ((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
81 #define NEW_PAD_CTRL(cfg, pad) (((cfg) & ~MUX_PAD_CTRL_MASK) | \
92 #define __PAD_CTRL_VALID (1 << 17)
93 #define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
97 #define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16)
99 #define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 14 | PAD_CTL_PUE)
100 #define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 14 | PAD_CTL_PUE)
101 #define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 14 | PAD_CTL_PUE)
102 #define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 14 | PAD_CTL_PUE)
103 #define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 13 | PAD_CTL_PKE)
104 #define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 12)
106 #define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 11)
108 #define PAD_CTL_SPEED_LOW __MUX_PAD_CTRL(1 << 6)
109 #define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(2 << 6)
110 #define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 6)
112 #define PAD_CTL_DSE_DISABLE __MUX_PAD_CTRL(0 << 3)
113 #define PAD_CTL_DSE_240ohm __MUX_PAD_CTRL(1 << 3)
114 #define PAD_CTL_DSE_120ohm __MUX_PAD_CTRL(2 << 3)
115 #define PAD_CTL_DSE_80ohm __MUX_PAD_CTRL(3 << 3)
116 #define PAD_CTL_DSE_60ohm __MUX_PAD_CTRL(4 << 3)
117 #define PAD_CTL_DSE_48ohm __MUX_PAD_CTRL(5 << 3)
118 #define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3)
119 #define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3)
121 #if defined CONFIG_SOC_MX6SL
122 #define PAD_CTL_LVE __MUX_PAD_CTRL(1 << 1)
123 #define PAD_CTL_LVE_BIT __MUX_PAD_CTRL(1 << 22)
126 #elif defined(CONFIG_SOC_VF610)
128 #define PAD_MUX_MODE_SHIFT 20
130 #define PAD_CTL_INPUT_DIFFERENTIAL __MUX_PAD_CTRL(1 << 16)
132 #define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(1 << 12)
133 #define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 12)
135 #define PAD_CTL_SRE __MUX_PAD_CTRL(1 << 11)
137 #define PAD_CTL_DSE_150ohm __MUX_PAD_CTRL(1 << 6)
138 #define PAD_CTL_DSE_50ohm __MUX_PAD_CTRL(3 << 6)
139 #define PAD_CTL_DSE_25ohm __MUX_PAD_CTRL(6 << 6)
140 #define PAD_CTL_DSE_20ohm __MUX_PAD_CTRL(7 << 6)
142 #define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE)
143 #define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE)
144 #define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE)
145 #define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 3)
146 #define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 2 | PAD_CTL_PKE)
148 #define PAD_CTL_OBE_IBE_ENABLE __MUX_PAD_CTRL(3 << 0)
149 #define PAD_CTL_OBE_ENABLE __MUX_PAD_CTRL(1 << 1)
150 #define PAD_CTL_IBE_ENABLE __MUX_PAD_CTRL(1 << 0)
154 #define PAD_CTL_DVS __MUX_PAD_CTRL(1 << 13)
155 #define PAD_CTL_INPUT_DDR __MUX_PAD_CTRL(1 << 9)
156 #define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 8)
158 #define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 7)
159 #define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 6 | PAD_CTL_PKE)
160 #define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 4 | PAD_CTL_PUE)
161 #define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE)
162 #define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE)
163 #define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE)
165 #define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 3)
167 #define PAD_CTL_DSE_LOW __MUX_PAD_CTRL(0 << 1)
168 #define PAD_CTL_DSE_MED __MUX_PAD_CTRL(1 << 1)
169 #define PAD_CTL_DSE_HIGH __MUX_PAD_CTRL(2 << 1)
170 #define PAD_CTL_DSE_MAX __MUX_PAD_CTRL(3 << 1)
174 #define PAD_CTL_SRE_SLOW __MUX_PAD_CTRL(0 << 0)
175 #define PAD_CTL_SRE_FAST __MUX_PAD_CTRL(1 << 0)
177 #define IOMUX_CONFIG_SION 0x10
179 #define GPIO_PIN_MASK 0x1f
180 #define GPIO_PORT_SHIFT 5
181 #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
182 #define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
183 #define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
184 #define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
185 #define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
186 #define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
187 #define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
189 void imx_iomux_v3_setup_pad(const iomux_v3_cfg_t const pad);
190 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
193 * Set bits for general purpose registers
195 void imx_iomux_set_gpr_register(int group, int start_bit,
196 int num_bits, int value);
198 /* macros for declaring and using pinmux array */
199 #if defined(CONFIG_SOC_MX6QDL)
200 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
201 #define SETUP_IOMUX_PAD(def) \
202 if (is_cpu_type(MXC_CPU_MX6Q)) { \
203 imx_iomux_v3_setup_pad(MX6Q_##def); \
205 imx_iomux_v3_setup_pad(MX6DL_##def); \
207 #define SETUP_IOMUX_PADS(x) \
208 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
209 #elif defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)
210 #define IOMUX_PADS(x) MX6Q_##x
211 #define SETUP_IOMUX_PAD(def) \
212 imx_iomux_v3_setup_pad(MX6Q_##def);
213 #define SETUP_IOMUX_PADS(x) \
214 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
216 #define IOMUX_PADS(x) MX6DL_##x
217 #define SETUP_IOMUX_PAD(def) \
218 imx_iomux_v3_setup_pad(MX6DL_##def);
219 #define SETUP_IOMUX_PADS(x) \
220 imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
223 #endif /* __ASM_ARCH_IOMUX_V3_H__*/