2 * linux/arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/export.h>
11 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/ioport.h>
14 #include <linux/delay.h>
15 #include <linux/utsname.h>
16 #include <linux/initrd.h>
17 #include <linux/console.h>
18 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/screen_info.h>
21 #include <linux/of_iommu.h>
22 #include <linux/of_platform.h>
23 #include <linux/init.h>
24 #include <linux/kexec.h>
25 #include <linux/of_fdt.h>
26 #include <linux/cpu.h>
27 #include <linux/interrupt.h>
28 #include <linux/smp.h>
29 #include <linux/proc_fs.h>
30 #include <linux/memblock.h>
31 #include <linux/bug.h>
32 #include <linux/compiler.h>
33 #include <linux/sort.h>
35 #include <asm/unified.h>
38 #include <asm/cputype.h>
40 #include <asm/procinfo.h>
42 #include <asm/sections.h>
43 #include <asm/setup.h>
44 #include <asm/smp_plat.h>
45 #include <asm/mach-types.h>
46 #include <asm/cacheflush.h>
47 #include <asm/cachetype.h>
48 #include <asm/tlbflush.h>
51 #include <asm/mach/arch.h>
52 #include <asm/mach/irq.h>
53 #include <asm/mach/time.h>
54 #include <asm/system_info.h>
55 #include <asm/system_misc.h>
56 #include <asm/traps.h>
57 #include <asm/unwind.h>
58 #include <asm/memblock.h>
64 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
67 static int __init fpe_setup(char *line)
69 memcpy(fpe_type, line, 8);
73 __setup("fpe=", fpe_setup);
76 extern void init_default_cache_policy(unsigned long);
77 extern void paging_init(const struct machine_desc *desc);
78 extern void early_paging_init(const struct machine_desc *,
79 struct proc_info_list *);
80 extern void sanity_check_meminfo(void);
81 extern enum reboot_mode reboot_mode;
82 extern void setup_dma_zone(const struct machine_desc *desc);
84 unsigned int processor_id;
85 EXPORT_SYMBOL(processor_id);
86 unsigned int __machine_arch_type __read_mostly;
87 EXPORT_SYMBOL(__machine_arch_type);
88 unsigned int cacheid __read_mostly;
89 EXPORT_SYMBOL(cacheid);
91 unsigned int __atags_pointer __initdata;
93 unsigned int system_rev;
94 EXPORT_SYMBOL(system_rev);
96 unsigned int system_serial_low;
97 EXPORT_SYMBOL(system_serial_low);
99 unsigned int system_serial_high;
100 EXPORT_SYMBOL(system_serial_high);
102 unsigned int elf_hwcap __read_mostly;
103 EXPORT_SYMBOL(elf_hwcap);
105 unsigned int elf_hwcap2 __read_mostly;
106 EXPORT_SYMBOL(elf_hwcap2);
110 struct processor processor __read_mostly;
113 struct cpu_tlb_fns cpu_tlb __read_mostly;
116 struct cpu_user_fns cpu_user __read_mostly;
119 struct cpu_cache_fns cpu_cache __read_mostly;
121 #ifdef CONFIG_OUTER_CACHE
122 struct outer_cache_fns outer_cache __read_mostly;
123 EXPORT_SYMBOL(outer_cache);
127 * Cached cpu_architecture() result for use by assembler code.
128 * C code should use the cpu_architecture() function instead of accessing this
131 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
138 } ____cacheline_aligned;
140 #ifndef CONFIG_CPU_V7M
141 static struct stack stacks[NR_CPUS];
144 char elf_platform[ELF_PLATFORM_SIZE];
145 EXPORT_SYMBOL(elf_platform);
147 static const char *cpu_name;
148 static const char *machine_name;
149 static char __initdata cmd_line[COMMAND_LINE_SIZE];
150 const struct machine_desc *machine_desc __initdata;
152 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
153 #define ENDIANNESS ((char)endian_test.l)
155 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
158 * Standard memory resources
160 static struct resource mem_res[] = {
165 .flags = IORESOURCE_MEM
168 .name = "Kernel code",
171 .flags = IORESOURCE_MEM
174 .name = "Kernel data",
177 .flags = IORESOURCE_MEM
181 #define video_ram mem_res[0]
182 #define kernel_code mem_res[1]
183 #define kernel_data mem_res[2]
185 static struct resource io_res[] = {
190 .flags = IORESOURCE_IO | IORESOURCE_BUSY
196 .flags = IORESOURCE_IO | IORESOURCE_BUSY
202 .flags = IORESOURCE_IO | IORESOURCE_BUSY
206 #define lp0 io_res[0]
207 #define lp1 io_res[1]
208 #define lp2 io_res[2]
210 static const char *proc_arch[] = {
230 #ifdef CONFIG_CPU_V7M
231 static int __get_cpu_architecture(void)
233 return CPU_ARCH_ARMv7M;
236 static int __get_cpu_architecture(void)
240 if ((read_cpuid_id() & 0x0008f000) == 0) {
241 cpu_arch = CPU_ARCH_UNKNOWN;
242 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
243 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
244 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
245 cpu_arch = (read_cpuid_id() >> 16) & 7;
247 cpu_arch += CPU_ARCH_ARMv3;
248 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
249 /* Revised CPUID format. Read the Memory Model Feature
250 * Register 0 and check for VMSAv7 or PMSAv7 */
251 unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
252 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
253 (mmfr0 & 0x000000f0) >= 0x00000030)
254 cpu_arch = CPU_ARCH_ARMv7;
255 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
256 (mmfr0 & 0x000000f0) == 0x00000020)
257 cpu_arch = CPU_ARCH_ARMv6;
259 cpu_arch = CPU_ARCH_UNKNOWN;
261 cpu_arch = CPU_ARCH_UNKNOWN;
267 int __pure cpu_architecture(void)
269 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
271 return __cpu_architecture;
274 static int cpu_has_aliasing_icache(unsigned int arch)
277 unsigned int id_reg, num_sets, line_size;
279 /* PIPT caches never alias. */
280 if (icache_is_pipt())
283 /* arch specifies the register format */
286 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
287 : /* No output operands */
290 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
292 line_size = 4 << ((id_reg & 0x7) + 2);
293 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
294 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
297 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
300 /* I-cache aliases will be handled by D-cache aliasing code */
304 return aliasing_icache;
307 static void __init cacheid_init(void)
309 unsigned int arch = cpu_architecture();
311 if (arch == CPU_ARCH_ARMv7M) {
313 } else if (arch >= CPU_ARCH_ARMv6) {
314 unsigned int cachetype = read_cpuid_cachetype();
315 if ((cachetype & (7 << 29)) == 4 << 29) {
316 /* ARMv7 register format */
317 arch = CPU_ARCH_ARMv7;
318 cacheid = CACHEID_VIPT_NONALIASING;
319 switch (cachetype & (3 << 14)) {
321 cacheid |= CACHEID_ASID_TAGGED;
324 cacheid |= CACHEID_PIPT;
328 arch = CPU_ARCH_ARMv6;
329 if (cachetype & (1 << 23))
330 cacheid = CACHEID_VIPT_ALIASING;
332 cacheid = CACHEID_VIPT_NONALIASING;
334 if (cpu_has_aliasing_icache(arch))
335 cacheid |= CACHEID_VIPT_I_ALIASING;
337 cacheid = CACHEID_VIVT;
340 pr_info("CPU: %s data cache, %s instruction cache\n",
341 cache_is_vivt() ? "VIVT" :
342 cache_is_vipt_aliasing() ? "VIPT aliasing" :
343 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
344 cache_is_vivt() ? "VIVT" :
345 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
346 icache_is_vipt_aliasing() ? "VIPT aliasing" :
347 icache_is_pipt() ? "PIPT" :
348 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
352 * These functions re-use the assembly code in head.S, which
353 * already provide the required functionality.
355 extern struct proc_info_list *lookup_processor_type(unsigned int);
357 void __init early_print(const char *str, ...)
359 extern void printascii(const char *);
364 vsnprintf(buf, sizeof(buf), str, ap);
367 #ifdef CONFIG_DEBUG_LL
373 static void __init cpuid_init_hwcaps(void)
378 if (cpu_architecture() < CPU_ARCH_ARMv7)
381 block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
383 elf_hwcap |= HWCAP_IDIVA;
385 elf_hwcap |= HWCAP_IDIVT;
387 /* LPAE implies atomic ldrd/strd instructions */
388 block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
390 elf_hwcap |= HWCAP_LPAE;
392 /* check for supported v8 Crypto instructions */
393 isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
395 block = cpuid_feature_extract_field(isar5, 4);
397 elf_hwcap2 |= HWCAP2_PMULL;
399 elf_hwcap2 |= HWCAP2_AES;
401 block = cpuid_feature_extract_field(isar5, 8);
403 elf_hwcap2 |= HWCAP2_SHA1;
405 block = cpuid_feature_extract_field(isar5, 12);
407 elf_hwcap2 |= HWCAP2_SHA2;
409 block = cpuid_feature_extract_field(isar5, 16);
411 elf_hwcap2 |= HWCAP2_CRC32;
414 static void __init elf_hwcap_fixup(void)
416 unsigned id = read_cpuid_id();
419 * HWCAP_TLS is available only on 1136 r1p0 and later,
420 * see also kuser_get_tls_init.
422 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
423 ((id >> 20) & 3) == 0) {
424 elf_hwcap &= ~HWCAP_TLS;
428 /* Verify if CPUID scheme is implemented */
429 if ((id & 0x000f0000) != 0x000f0000)
433 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
434 * avoid advertising SWP; it may not be atomic with
435 * multiprocessing cores.
437 if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
438 (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
439 cpuid_feature_extract(CPUID_EXT_ISAR3, 20) >= 3))
440 elf_hwcap &= ~HWCAP_SWP;
444 * cpu_init - initialise one CPU.
446 * cpu_init sets up the per-CPU stacks.
448 void notrace cpu_init(void)
450 #ifndef CONFIG_CPU_V7M
451 unsigned int cpu = smp_processor_id();
452 struct stack *stk = &stacks[cpu];
454 if (cpu >= NR_CPUS) {
455 pr_crit("CPU%u: bad primary CPU number\n", cpu);
460 * This only works on resume and secondary cores. For booting on the
461 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
463 set_my_cpu_offset(per_cpu_offset(cpu));
468 * Define the placement constraint for the inline asm directive below.
469 * In Thumb-2, msr with an immediate value is not allowed.
471 #ifdef CONFIG_THUMB2_KERNEL
478 * setup stacks for re-entrant exception handlers
482 "add r14, %0, %2\n\t"
485 "add r14, %0, %4\n\t"
488 "add r14, %0, %6\n\t"
491 "add r14, %0, %8\n\t"
496 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
497 "I" (offsetof(struct stack, irq[0])),
498 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
499 "I" (offsetof(struct stack, abt[0])),
500 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
501 "I" (offsetof(struct stack, und[0])),
502 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
503 "I" (offsetof(struct stack, fiq[0])),
504 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
509 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
511 void __init smp_setup_processor_id(void)
514 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
515 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
517 cpu_logical_map(0) = cpu;
518 for (i = 1; i < nr_cpu_ids; ++i)
519 cpu_logical_map(i) = i == cpu ? 0 : i;
522 * clear __my_cpu_offset on boot CPU to avoid hang caused by
523 * using percpu variable early, for example, lockdep will
524 * access percpu variable inside lock_release
526 set_my_cpu_offset(0);
528 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
531 struct mpidr_hash mpidr_hash;
534 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
535 * level in order to build a linear index from an
536 * MPIDR value. Resulting algorithm is a collision
537 * free hash carried out through shifting and ORing
539 static void __init smp_build_mpidr_hash(void)
542 u32 fs[3], bits[3], ls, mask = 0;
544 * Pre-scan the list of MPIDRS and filter out bits that do
545 * not contribute to affinity levels, ie they never toggle.
547 for_each_possible_cpu(i)
548 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
549 pr_debug("mask of set bits 0x%x\n", mask);
551 * Find and stash the last and first bit set at all affinity levels to
552 * check how many bits are required to represent them.
554 for (i = 0; i < 3; i++) {
555 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
557 * Find the MSB bit and LSB bits position
558 * to determine how many bits are required
559 * to express the affinity level.
562 fs[i] = affinity ? ffs(affinity) - 1 : 0;
563 bits[i] = ls - fs[i];
566 * An index can be created from the MPIDR by isolating the
567 * significant bits at each affinity level and by shifting
568 * them in order to compress the 24 bits values space to a
569 * compressed set of values. This is equivalent to hashing
570 * the MPIDR through shifting and ORing. It is a collision free
571 * hash though not minimal since some levels might contain a number
572 * of CPUs that is not an exact power of 2 and their bit
573 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
575 mpidr_hash.shift_aff[0] = fs[0];
576 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
577 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
579 mpidr_hash.mask = mask;
580 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
581 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
582 mpidr_hash.shift_aff[0],
583 mpidr_hash.shift_aff[1],
584 mpidr_hash.shift_aff[2],
588 * 4x is an arbitrary value used to warn on a hash table much bigger
589 * than expected on most systems.
591 if (mpidr_hash_size() > 4 * num_possible_cpus())
592 pr_warn("Large number of MPIDR hash buckets detected\n");
593 sync_cache_w(&mpidr_hash);
597 static void __init setup_processor(void)
599 struct proc_info_list *list;
602 * locate processor in the list of supported processor
603 * types. The linker builds this table for us from the
604 * entries in arch/arm/mm/proc-*.S
606 list = lookup_processor_type(read_cpuid_id());
608 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
613 cpu_name = list->cpu_name;
614 __cpu_architecture = __get_cpu_architecture();
617 processor = *list->proc;
620 cpu_tlb = *list->tlb;
623 cpu_user = *list->user;
626 cpu_cache = *list->cache;
629 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
630 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
631 proc_arch[cpu_architecture()], get_cr());
633 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
634 list->arch_name, ENDIANNESS);
635 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
636 list->elf_name, ENDIANNESS);
637 elf_hwcap = list->elf_hwcap;
641 #ifndef CONFIG_ARM_THUMB
642 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
645 init_default_cache_policy(list->__cpu_mm_mmu_flags);
647 erratum_a15_798181_init();
655 void __init dump_machine_table(void)
657 const struct machine_desc *p;
659 early_print("Available machine support:\n\nID (hex)\tNAME\n");
660 for_each_machine_desc(p)
661 early_print("%08x\t%s\n", p->nr, p->name);
663 early_print("\nPlease check your kernel config and/or bootloader.\n");
666 /* can't use cpu_relax() here as it may require MMU setup */;
669 int __init arm_add_memory(u64 start, u64 size)
674 * Ensure that start/size are aligned to a page boundary.
675 * Size is rounded down, start is rounded up.
677 aligned_start = PAGE_ALIGN(start);
678 if (aligned_start > start + size)
681 size -= aligned_start - start;
683 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
684 if (aligned_start > ULONG_MAX) {
685 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
690 if (aligned_start + size > ULONG_MAX) {
691 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
694 * To ensure bank->start + bank->size is representable in
695 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
696 * This means we lose a page after masking.
698 size = ULONG_MAX - aligned_start;
702 if (aligned_start < PHYS_OFFSET) {
703 if (aligned_start + size <= PHYS_OFFSET) {
704 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
705 aligned_start, aligned_start + size);
709 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
710 aligned_start, (u64)PHYS_OFFSET);
712 size -= PHYS_OFFSET - aligned_start;
713 aligned_start = PHYS_OFFSET;
716 start = aligned_start;
717 size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
720 * Check whether this memory region has non-zero size or
721 * invalid node number.
726 memblock_add(start, size);
731 * Pick out the memory size. We look for mem=size@start,
732 * where start and size are "size[KkMm]"
735 static int __init early_mem(char *p)
737 static int usermem __initdata = 0;
743 * If the user specifies memory size, we
744 * blow away any automatically generated
749 memblock_remove(memblock_start_of_DRAM(),
750 memblock_end_of_DRAM() - memblock_start_of_DRAM());
754 size = memparse(p, &endp);
756 start = memparse(endp + 1, NULL);
758 arm_add_memory(start, size);
762 early_param("mem", early_mem);
764 static void __init request_standard_resources(const struct machine_desc *mdesc)
766 struct memblock_region *region;
767 struct resource *res;
769 kernel_code.start = virt_to_phys(_text);
770 kernel_code.end = virt_to_phys(_etext - 1);
771 kernel_data.start = virt_to_phys(_sdata);
772 kernel_data.end = virt_to_phys(_end - 1);
774 for_each_memblock(memory, region) {
775 res = memblock_virt_alloc(sizeof(*res), 0);
776 res->name = "System RAM";
777 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
778 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
779 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
781 request_resource(&iomem_resource, res);
783 if (kernel_code.start >= res->start &&
784 kernel_code.end <= res->end)
785 request_resource(res, &kernel_code);
786 if (kernel_data.start >= res->start &&
787 kernel_data.end <= res->end)
788 request_resource(res, &kernel_data);
791 if (mdesc->video_start) {
792 video_ram.start = mdesc->video_start;
793 video_ram.end = mdesc->video_end;
794 request_resource(&iomem_resource, &video_ram);
798 * Some machines don't have the possibility of ever
799 * possessing lp0, lp1 or lp2
801 if (mdesc->reserve_lp0)
802 request_resource(&ioport_resource, &lp0);
803 if (mdesc->reserve_lp1)
804 request_resource(&ioport_resource, &lp1);
805 if (mdesc->reserve_lp2)
806 request_resource(&ioport_resource, &lp2);
809 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
810 struct screen_info screen_info = {
811 .orig_video_lines = 30,
812 .orig_video_cols = 80,
813 .orig_video_mode = 0,
814 .orig_video_ega_bx = 0,
815 .orig_video_isVGA = 1,
816 .orig_video_points = 8
820 static int __init customize_machine(void)
823 * customizes platform devices, or adds new ones
824 * On DT based machines, we fall back to populating the
825 * machine from the device tree, if no callback is provided,
826 * otherwise we would always need an init_machine callback.
829 if (machine_desc->init_machine)
830 machine_desc->init_machine();
833 of_platform_populate(NULL, of_default_bus_match_table,
838 arch_initcall(customize_machine);
840 static int __init init_machine_late(void)
842 if (machine_desc->init_late)
843 machine_desc->init_late();
846 late_initcall(init_machine_late);
849 static inline unsigned long long get_total_mem(void)
853 total = max_low_pfn - min_low_pfn;
854 return total << PAGE_SHIFT;
858 * reserve_crashkernel() - reserves memory are for crash kernel
860 * This function reserves memory area given in "crashkernel=" kernel command
861 * line parameter. The memory reserved is used by a dump capture kernel when
862 * primary kernel is crashing.
864 static void __init reserve_crashkernel(void)
866 unsigned long long crash_size, crash_base;
867 unsigned long long total_mem;
870 total_mem = get_total_mem();
871 ret = parse_crashkernel(boot_command_line, total_mem,
872 &crash_size, &crash_base);
876 ret = memblock_reserve(crash_base, crash_size);
878 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
879 (unsigned long)crash_base);
883 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
884 (unsigned long)(crash_size >> 20),
885 (unsigned long)(crash_base >> 20),
886 (unsigned long)(total_mem >> 20));
888 crashk_res.start = crash_base;
889 crashk_res.end = crash_base + crash_size - 1;
890 insert_resource(&iomem_resource, &crashk_res);
893 static inline void reserve_crashkernel(void) {}
894 #endif /* CONFIG_KEXEC */
896 void __init hyp_mode_check(void)
898 #ifdef CONFIG_ARM_VIRT_EXT
901 if (is_hyp_mode_available()) {
902 pr_info("CPU: All CPU(s) started in HYP mode.\n");
903 pr_info("CPU: Virtualization extensions available.\n");
904 } else if (is_hyp_mode_mismatched()) {
905 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
906 __boot_cpu_mode & MODE_MASK);
907 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
909 pr_info("CPU: All CPU(s) started in SVC mode.\n");
913 void __init setup_arch(char **cmdline_p)
915 const struct machine_desc *mdesc;
918 mdesc = setup_machine_fdt(__atags_pointer);
920 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
921 machine_desc = mdesc;
922 machine_name = mdesc->name;
923 dump_stack_set_arch_desc("%s", mdesc->name);
925 if (mdesc->reboot_mode != REBOOT_HARD)
926 reboot_mode = mdesc->reboot_mode;
928 init_mm.start_code = (unsigned long) _text;
929 init_mm.end_code = (unsigned long) _etext;
930 init_mm.end_data = (unsigned long) _edata;
931 init_mm.brk = (unsigned long) _end;
933 /* populate cmd_line too for later use, preserving boot_command_line */
934 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
935 *cmdline_p = cmd_line;
939 early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
940 setup_dma_zone(mdesc);
941 sanity_check_meminfo();
942 arm_memblock_init(mdesc);
945 request_standard_resources(mdesc);
948 arm_pm_restart = mdesc->restart;
950 unflatten_device_tree();
952 arm_dt_init_cpu_maps();
956 if (!mdesc->smp_init || !mdesc->smp_init()) {
957 if (psci_smp_available())
958 smp_set_ops(&psci_smp_ops);
960 smp_set_ops(mdesc->smp);
963 smp_build_mpidr_hash();
970 reserve_crashkernel();
972 #ifdef CONFIG_MULTI_IRQ_HANDLER
973 handle_arch_irq = mdesc->handle_irq;
977 #if defined(CONFIG_VGA_CONSOLE)
978 conswitchp = &vga_con;
979 #elif defined(CONFIG_DUMMY_CONSOLE)
980 conswitchp = &dummy_con;
984 if (mdesc->init_early)
989 static int __init topology_init(void)
993 for_each_possible_cpu(cpu) {
994 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
995 cpuinfo->cpu.hotpluggable = 1;
996 register_cpu(&cpuinfo->cpu, cpu);
1001 subsys_initcall(topology_init);
1003 #ifdef CONFIG_HAVE_PROC_CPU
1004 static int __init proc_cpu_init(void)
1006 struct proc_dir_entry *res;
1008 res = proc_mkdir("cpu", NULL);
1013 fs_initcall(proc_cpu_init);
1016 static const char *hwcap_str[] = {
1042 static const char *hwcap2_str[] = {
1051 static int c_show(struct seq_file *m, void *v)
1056 for_each_online_cpu(i) {
1058 * glibc reads /proc/cpuinfo to determine the number of
1059 * online processors, looking for lines beginning with
1060 * "processor". Give glibc what it expects.
1062 seq_printf(m, "processor\t: %d\n", i);
1063 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1064 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1065 cpu_name, cpuid & 15, elf_platform);
1067 #if defined(CONFIG_SMP)
1068 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1069 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1070 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1072 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1073 loops_per_jiffy / (500000/HZ),
1074 (loops_per_jiffy / (5000/HZ)) % 100);
1076 /* dump out the processor features */
1077 seq_puts(m, "Features\t: ");
1079 for (j = 0; hwcap_str[j]; j++)
1080 if (elf_hwcap & (1 << j))
1081 seq_printf(m, "%s ", hwcap_str[j]);
1083 for (j = 0; hwcap2_str[j]; j++)
1084 if (elf_hwcap2 & (1 << j))
1085 seq_printf(m, "%s ", hwcap2_str[j]);
1087 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1088 seq_printf(m, "CPU architecture: %s\n",
1089 proc_arch[cpu_architecture()]);
1091 if ((cpuid & 0x0008f000) == 0x00000000) {
1093 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1095 if ((cpuid & 0x0008f000) == 0x00007000) {
1097 seq_printf(m, "CPU variant\t: 0x%02x\n",
1098 (cpuid >> 16) & 127);
1101 seq_printf(m, "CPU variant\t: 0x%x\n",
1102 (cpuid >> 20) & 15);
1104 seq_printf(m, "CPU part\t: 0x%03x\n",
1105 (cpuid >> 4) & 0xfff);
1107 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1110 seq_printf(m, "Hardware\t: %s\n", machine_name);
1111 seq_printf(m, "Revision\t: %04x\n", system_rev);
1112 seq_printf(m, "Serial\t\t: %08x%08x\n",
1113 system_serial_high, system_serial_low);
1118 static void *c_start(struct seq_file *m, loff_t *pos)
1120 return *pos < 1 ? (void *)1 : NULL;
1123 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1129 static void c_stop(struct seq_file *m, void *v)
1133 const struct seq_operations cpuinfo_op = {