3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/cache.h>
11 #include <linux/compiler.h>
13 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
15 DECLARE_GLOBAL_DATA_PTR;
17 __weak void arm_init_before_mmu(void)
21 __weak void arm_init_domains(void)
25 void set_section_dcache(int section, enum dcache_option option)
27 u32 *page_table = (u32 *)gd->arch.tlb_addr;
30 value = (section << MMU_SECTION_SHIFT) | (3 << 10);
32 page_table[section] = value;
35 __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
37 debug("%s: Warning: not implemented\n", __func__);
40 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
41 enum dcache_option option)
43 u32 *page_table = (u32 *)gd->arch.tlb_addr;
44 unsigned long upto, end;
46 end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
47 start = start >> MMU_SECTION_SHIFT;
48 debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
50 for (upto = start; upto < end; upto++)
51 set_section_dcache(upto, option);
52 mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
55 __weak void dram_bank_mmu_setup(int bank)
60 debug("%s: bank: %d\n", __func__, bank);
61 for (i = bd->bi_dram[bank].start >> 20;
62 i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
64 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
65 set_section_dcache(i, DCACHE_WRITETHROUGH);
66 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
67 set_section_dcache(i, DCACHE_WRITEALLOC);
69 set_section_dcache(i, DCACHE_WRITEBACK);
74 /* to activate the MMU we need to set up virtual memory: use 1M areas */
75 static inline void mmu_setup(void)
80 arm_init_before_mmu();
81 /* Set up an identity-mapping for all 4GB, rw for everyone */
82 for (i = 0; i < 4096; i++)
83 set_section_dcache(i, DCACHE_OFF);
85 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
86 dram_bank_mmu_setup(i);
91 reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
92 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
93 reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
94 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
95 reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
97 reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
99 asm volatile("mcr p15, 0, %0, c2, c0, 0"
100 : : "r" (reg) : "memory");
102 /* Copy the page table address to cp15 */
103 asm volatile("mcr p15, 0, %0, c2, c0, 0"
104 : : "r" (gd->arch.tlb_addr) : "memory");
106 /* Set the access control to all-supervisor */
107 asm volatile("mcr p15, 0, %0, c3, c0, 0"
112 /* and enable the mmu */
113 reg = get_cr(); /* get control reg. */
117 static int mmu_enabled(void)
119 return get_cr() & CR_M;
122 /* cache_bit must be either CR_I or CR_C */
123 static void cache_enable(uint32_t cache_bit)
127 /* The data cache is not active unless the mmu is enabled too */
128 if ((cache_bit == CR_C) && !mmu_enabled())
130 reg = get_cr(); /* get control reg. */
131 set_cr(reg | cache_bit);
134 /* cache_bit must be either CR_I or CR_C */
135 static void cache_disable(uint32_t cache_bit)
141 if (cache_bit == CR_C) {
142 /* if cache isn;t enabled no need to disable */
143 if ((reg & CR_C) != CR_C)
145 /* if disabling data cache, disable mmu too */
149 if (cache_bit == (CR_C | CR_M))
151 set_cr(reg & ~cache_bit);
155 #ifdef CONFIG_SYS_ICACHE_OFF
156 void icache_enable (void)
161 void icache_disable (void)
166 int icache_status (void)
168 return 0; /* always off */
171 void icache_enable(void)
176 void icache_disable(void)
181 int icache_status(void)
183 return (get_cr() & CR_I) != 0;
187 #ifdef CONFIG_SYS_DCACHE_OFF
188 void dcache_enable (void)
193 void dcache_disable (void)
198 int dcache_status (void)
200 return 0; /* always off */
203 void dcache_enable(void)
208 void dcache_disable(void)
213 int dcache_status(void)
215 return (get_cr() & CR_C) != 0;