2 * arch/arm/mach-at91/at91rm9200_devices.c
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <asm/mach/arch.h>
14 #include <asm/mach/map.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/gpio.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
21 #include <mach/at91rm9200.h>
22 #include <mach/at91rm9200_mc.h>
23 #include <mach/at91_ramc.h>
24 #include <mach/hardware.h>
30 /* --------------------------------------------------------------------
32 * -------------------------------------------------------------------- */
34 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
35 static u64 ohci_dmamask = DMA_BIT_MASK(32);
36 static struct at91_usbh_data usbh_data;
38 static struct resource usbh_resources[] = {
40 .start = AT91RM9200_UHP_BASE,
41 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
42 .flags = IORESOURCE_MEM,
45 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
46 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
47 .flags = IORESOURCE_IRQ,
51 static struct platform_device at91rm9200_usbh_device = {
55 .dma_mask = &ohci_dmamask,
56 .coherent_dma_mask = DMA_BIT_MASK(32),
57 .platform_data = &usbh_data,
59 .resource = usbh_resources,
60 .num_resources = ARRAY_SIZE(usbh_resources),
63 void __init at91_add_device_usbh(struct at91_usbh_data *data)
70 /* Enable overcurrent notification */
71 for (i = 0; i < data->ports; i++) {
72 if (gpio_is_valid(data->overcurrent_pin[i]))
73 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 platform_device_register(&at91rm9200_usbh_device);
80 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84 /* --------------------------------------------------------------------
86 * -------------------------------------------------------------------- */
88 #if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
89 static struct at91_udc_data udc_data;
91 static struct resource udc_resources[] = {
93 .start = AT91RM9200_BASE_UDP,
94 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
95 .flags = IORESOURCE_MEM,
98 .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
99 .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
100 .flags = IORESOURCE_IRQ,
104 static struct platform_device at91rm9200_udc_device = {
108 .platform_data = &udc_data,
110 .resource = udc_resources,
111 .num_resources = ARRAY_SIZE(udc_resources),
114 void __init at91_add_device_udc(struct at91_udc_data *data)
119 if (gpio_is_valid(data->vbus_pin)) {
120 at91_set_gpio_input(data->vbus_pin, 0);
121 at91_set_deglitch(data->vbus_pin, 1);
123 if (gpio_is_valid(data->pullup_pin))
124 at91_set_gpio_output(data->pullup_pin, 0);
127 platform_device_register(&at91rm9200_udc_device);
130 void __init at91_add_device_udc(struct at91_udc_data *data) {}
134 /* --------------------------------------------------------------------
136 * -------------------------------------------------------------------- */
138 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
139 static u64 eth_dmamask = DMA_BIT_MASK(32);
140 static struct macb_platform_data eth_data;
142 static struct resource eth_resources[] = {
144 .start = AT91RM9200_BASE_EMAC,
145 .end = AT91RM9200_BASE_EMAC + SZ_16K - 1,
146 .flags = IORESOURCE_MEM,
149 .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
150 .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
151 .flags = IORESOURCE_IRQ,
155 static struct platform_device at91rm9200_eth_device = {
156 .name = "at91_ether",
159 .dma_mask = ð_dmamask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 .platform_data = ð_data,
163 .resource = eth_resources,
164 .num_resources = ARRAY_SIZE(eth_resources),
167 void __init at91_add_device_eth(struct macb_platform_data *data)
172 if (gpio_is_valid(data->phy_irq_pin)) {
173 at91_set_gpio_input(data->phy_irq_pin, 0);
174 at91_set_deglitch(data->phy_irq_pin, 1);
177 /* Pins used for MII and RMII */
178 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
179 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
180 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
181 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
182 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
183 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
184 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
185 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
186 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
187 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
189 if (!data->is_rmii) {
190 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
191 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
192 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
193 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
194 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
195 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
196 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
197 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
201 platform_device_register(&at91rm9200_eth_device);
204 void __init at91_add_device_eth(struct macb_platform_data *data) {}
208 /* --------------------------------------------------------------------
209 * Compact Flash / PCMCIA
210 * -------------------------------------------------------------------- */
212 #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
213 static struct at91_cf_data cf_data;
215 #define CF_BASE AT91_CHIPSELECT_4
217 static struct resource cf_resources[] = {
220 /* ties up CS4, CS5 and CS6 */
221 .end = CF_BASE + (0x30000000 - 1),
222 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
226 static struct platform_device at91rm9200_cf_device = {
230 .platform_data = &cf_data,
232 .resource = cf_resources,
233 .num_resources = ARRAY_SIZE(cf_resources),
236 void __init at91_add_device_cf(struct at91_cf_data *data)
243 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
245 /* CF takes over CS4, CS5, CS6 */
246 csa = at91_ramc_read(0, AT91_EBI_CSA);
247 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
250 * Static memory controller timing adjustments.
251 * REVISIT: these timings are in terms of MCK cycles, so
252 * when MCK changes (cpufreq etc) so must these values...
254 at91_ramc_write(0, AT91_SMC_CSR(4),
259 | AT91_SMC_NWS_(32) /* wait states */
260 | AT91_SMC_RWSETUP_(6) /* setup time */
261 | AT91_SMC_RWHOLD_(4) /* hold time */
265 if (gpio_is_valid(data->irq_pin)) {
266 at91_set_gpio_input(data->irq_pin, 1);
267 at91_set_deglitch(data->irq_pin, 1);
269 at91_set_gpio_input(data->det_pin, 1);
270 at91_set_deglitch(data->det_pin, 1);
272 /* outputs, initially off */
273 if (gpio_is_valid(data->vcc_pin))
274 at91_set_gpio_output(data->vcc_pin, 0);
275 at91_set_gpio_output(data->rst_pin, 0);
277 /* force poweron defaults for these pins ... */
278 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
279 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
280 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
281 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
283 /* nWAIT is _not_ a default setting */
284 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
287 platform_device_register(&at91rm9200_cf_device);
290 void __init at91_add_device_cf(struct at91_cf_data *data) {}
294 /* --------------------------------------------------------------------
296 * -------------------------------------------------------------------- */
298 #if IS_ENABLED(CONFIG_MMC_ATMELMCI)
299 static u64 mmc_dmamask = DMA_BIT_MASK(32);
300 static struct mci_platform_data mmc_data;
302 static struct resource mmc_resources[] = {
304 .start = AT91RM9200_BASE_MCI,
305 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
306 .flags = IORESOURCE_MEM,
309 .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
310 .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
311 .flags = IORESOURCE_IRQ,
315 static struct platform_device at91rm9200_mmc_device = {
319 .dma_mask = &mmc_dmamask,
320 .coherent_dma_mask = DMA_BIT_MASK(32),
321 .platform_data = &mmc_data,
323 .resource = mmc_resources,
324 .num_resources = ARRAY_SIZE(mmc_resources),
327 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
330 unsigned int slot_count = 0;
335 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
337 if (!data->slot[i].bus_width)
341 if (gpio_is_valid(data->slot[i].detect_pin)) {
342 at91_set_gpio_input(data->slot[i].detect_pin, 1);
343 at91_set_deglitch(data->slot[i].detect_pin, 1);
345 if (gpio_is_valid(data->slot[i].wp_pin))
346 at91_set_gpio_input(data->slot[i].wp_pin, 1);
351 at91_set_A_periph(AT91_PIN_PA28, 1);
352 /* DAT0, maybe DAT1..DAT3 */
353 at91_set_A_periph(AT91_PIN_PA29, 1);
354 if (data->slot[i].bus_width == 4) {
355 at91_set_B_periph(AT91_PIN_PB3, 1);
356 at91_set_B_periph(AT91_PIN_PB4, 1);
357 at91_set_B_periph(AT91_PIN_PB5, 1);
363 at91_set_B_periph(AT91_PIN_PA8, 1);
364 /* DAT0, maybe DAT1..DAT3 */
365 at91_set_B_periph(AT91_PIN_PA9, 1);
366 if (data->slot[i].bus_width == 4) {
367 at91_set_B_periph(AT91_PIN_PA10, 1);
368 at91_set_B_periph(AT91_PIN_PA11, 1);
369 at91_set_B_periph(AT91_PIN_PA12, 1);
375 "AT91: SD/MMC slot %d not available\n", i);
380 at91_set_A_periph(AT91_PIN_PA27, 0);
383 platform_device_register(&at91rm9200_mmc_device);
389 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
393 /* --------------------------------------------------------------------
395 * -------------------------------------------------------------------- */
397 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
398 static struct atmel_nand_data nand_data;
400 #define NAND_BASE AT91_CHIPSELECT_3
402 static struct resource nand_resources[] = {
405 .end = NAND_BASE + SZ_256M - 1,
406 .flags = IORESOURCE_MEM,
410 static struct platform_device at91rm9200_nand_device = {
411 .name = "atmel_nand",
414 .platform_data = &nand_data,
416 .resource = nand_resources,
417 .num_resources = ARRAY_SIZE(nand_resources),
420 void __init at91_add_device_nand(struct atmel_nand_data *data)
427 /* enable the address range of CS3 */
428 csa = at91_ramc_read(0, AT91_EBI_CSA);
429 at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
431 /* set the bus interface characteristics */
432 at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
435 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
436 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
440 if (gpio_is_valid(data->enable_pin))
441 at91_set_gpio_output(data->enable_pin, 1);
444 if (gpio_is_valid(data->rdy_pin))
445 at91_set_gpio_input(data->rdy_pin, 1);
447 /* card detect pin */
448 if (gpio_is_valid(data->det_pin))
449 at91_set_gpio_input(data->det_pin, 1);
451 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
452 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
455 platform_device_register(&at91rm9200_nand_device);
458 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
462 /* --------------------------------------------------------------------
464 * -------------------------------------------------------------------- */
467 * Prefer the GPIO code since the TWI controller isn't robust
468 * (gets overruns and underruns under load) and can only issue
469 * repeated STARTs in one scenario (the driver doesn't yet handle them).
471 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
473 static struct i2c_gpio_platform_data pdata = {
474 .sda_pin = AT91_PIN_PA25,
475 .sda_is_open_drain = 1,
476 .scl_pin = AT91_PIN_PA26,
477 .scl_is_open_drain = 1,
478 .udelay = 2, /* ~100 kHz */
481 static struct platform_device at91rm9200_twi_device = {
484 .dev.platform_data = &pdata,
487 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
489 at91_set_GPIO_periph(AT91_PIN_PA25, 1); /* TWD (SDA) */
490 at91_set_multi_drive(AT91_PIN_PA25, 1);
492 at91_set_GPIO_periph(AT91_PIN_PA26, 1); /* TWCK (SCL) */
493 at91_set_multi_drive(AT91_PIN_PA26, 1);
495 i2c_register_board_info(0, devices, nr_devices);
496 platform_device_register(&at91rm9200_twi_device);
499 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
501 static struct resource twi_resources[] = {
503 .start = AT91RM9200_BASE_TWI,
504 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
505 .flags = IORESOURCE_MEM,
508 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
509 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
510 .flags = IORESOURCE_IRQ,
514 static struct platform_device at91rm9200_twi_device = {
515 .name = "i2c-at91rm9200",
517 .resource = twi_resources,
518 .num_resources = ARRAY_SIZE(twi_resources),
521 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
523 /* pins used for TWI interface */
524 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
525 at91_set_multi_drive(AT91_PIN_PA25, 1);
527 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
528 at91_set_multi_drive(AT91_PIN_PA26, 1);
530 i2c_register_board_info(0, devices, nr_devices);
531 platform_device_register(&at91rm9200_twi_device);
534 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
538 /* --------------------------------------------------------------------
540 * -------------------------------------------------------------------- */
542 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
543 static u64 spi_dmamask = DMA_BIT_MASK(32);
545 static struct resource spi_resources[] = {
547 .start = AT91RM9200_BASE_SPI,
548 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
549 .flags = IORESOURCE_MEM,
552 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
553 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
554 .flags = IORESOURCE_IRQ,
558 static struct platform_device at91rm9200_spi_device = {
562 .dma_mask = &spi_dmamask,
563 .coherent_dma_mask = DMA_BIT_MASK(32),
565 .resource = spi_resources,
566 .num_resources = ARRAY_SIZE(spi_resources),
569 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
571 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
574 unsigned long cs_pin;
576 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
577 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
578 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
580 /* Enable SPI chip-selects */
581 for (i = 0; i < nr_devices; i++) {
582 if (devices[i].controller_data)
583 cs_pin = (unsigned long) devices[i].controller_data;
585 cs_pin = spi_standard_cs[devices[i].chip_select];
587 if (devices[i].chip_select == 0) /* for CS0 errata */
588 at91_set_A_periph(cs_pin, 0);
590 at91_set_gpio_output(cs_pin, 1);
593 /* pass chip-select pin to driver */
594 devices[i].controller_data = (void *) cs_pin;
597 spi_register_board_info(devices, nr_devices);
598 platform_device_register(&at91rm9200_spi_device);
601 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
605 /* --------------------------------------------------------------------
606 * Timer/Counter blocks
607 * -------------------------------------------------------------------- */
609 #ifdef CONFIG_ATMEL_TCLIB
611 static struct resource tcb0_resources[] = {
613 .start = AT91RM9200_BASE_TCB0,
614 .end = AT91RM9200_BASE_TCB0 + SZ_16K - 1,
615 .flags = IORESOURCE_MEM,
618 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
619 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
620 .flags = IORESOURCE_IRQ,
623 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
624 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
625 .flags = IORESOURCE_IRQ,
628 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
629 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
630 .flags = IORESOURCE_IRQ,
634 static struct platform_device at91rm9200_tcb0_device = {
637 .resource = tcb0_resources,
638 .num_resources = ARRAY_SIZE(tcb0_resources),
641 static struct resource tcb1_resources[] = {
643 .start = AT91RM9200_BASE_TCB1,
644 .end = AT91RM9200_BASE_TCB1 + SZ_16K - 1,
645 .flags = IORESOURCE_MEM,
648 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
649 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
650 .flags = IORESOURCE_IRQ,
653 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
654 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
655 .flags = IORESOURCE_IRQ,
658 .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
659 .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
660 .flags = IORESOURCE_IRQ,
664 static struct platform_device at91rm9200_tcb1_device = {
667 .resource = tcb1_resources,
668 .num_resources = ARRAY_SIZE(tcb1_resources),
671 static void __init at91_add_device_tc(void)
673 platform_device_register(&at91rm9200_tcb0_device);
674 platform_device_register(&at91rm9200_tcb1_device);
677 static void __init at91_add_device_tc(void) { }
681 /* --------------------------------------------------------------------
683 * -------------------------------------------------------------------- */
685 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
686 static struct resource rtc_resources[] = {
688 .start = AT91RM9200_BASE_RTC,
689 .end = AT91RM9200_BASE_RTC + SZ_256 - 1,
690 .flags = IORESOURCE_MEM,
693 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
694 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
695 .flags = IORESOURCE_IRQ,
699 static struct platform_device at91rm9200_rtc_device = {
702 .resource = rtc_resources,
703 .num_resources = ARRAY_SIZE(rtc_resources),
706 static void __init at91_add_device_rtc(void)
708 platform_device_register(&at91rm9200_rtc_device);
711 static void __init at91_add_device_rtc(void) {}
715 /* --------------------------------------------------------------------
717 * -------------------------------------------------------------------- */
719 #if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
720 static struct platform_device at91rm9200_wdt_device = {
726 static void __init at91_add_device_watchdog(void)
728 platform_device_register(&at91rm9200_wdt_device);
731 static void __init at91_add_device_watchdog(void) {}
735 /* --------------------------------------------------------------------
736 * SSC -- Synchronous Serial Controller
737 * -------------------------------------------------------------------- */
739 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
740 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
742 static struct resource ssc0_resources[] = {
744 .start = AT91RM9200_BASE_SSC0,
745 .end = AT91RM9200_BASE_SSC0 + SZ_16K - 1,
746 .flags = IORESOURCE_MEM,
749 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
750 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
751 .flags = IORESOURCE_IRQ,
755 static struct platform_device at91rm9200_ssc0_device = {
756 .name = "at91rm9200_ssc",
759 .dma_mask = &ssc0_dmamask,
760 .coherent_dma_mask = DMA_BIT_MASK(32),
762 .resource = ssc0_resources,
763 .num_resources = ARRAY_SIZE(ssc0_resources),
766 static inline void configure_ssc0_pins(unsigned pins)
768 if (pins & ATMEL_SSC_TF)
769 at91_set_A_periph(AT91_PIN_PB0, 1);
770 if (pins & ATMEL_SSC_TK)
771 at91_set_A_periph(AT91_PIN_PB1, 1);
772 if (pins & ATMEL_SSC_TD)
773 at91_set_A_periph(AT91_PIN_PB2, 1);
774 if (pins & ATMEL_SSC_RD)
775 at91_set_A_periph(AT91_PIN_PB3, 1);
776 if (pins & ATMEL_SSC_RK)
777 at91_set_A_periph(AT91_PIN_PB4, 1);
778 if (pins & ATMEL_SSC_RF)
779 at91_set_A_periph(AT91_PIN_PB5, 1);
782 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
784 static struct resource ssc1_resources[] = {
786 .start = AT91RM9200_BASE_SSC1,
787 .end = AT91RM9200_BASE_SSC1 + SZ_16K - 1,
788 .flags = IORESOURCE_MEM,
791 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
792 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
793 .flags = IORESOURCE_IRQ,
797 static struct platform_device at91rm9200_ssc1_device = {
798 .name = "at91rm9200_ssc",
801 .dma_mask = &ssc1_dmamask,
802 .coherent_dma_mask = DMA_BIT_MASK(32),
804 .resource = ssc1_resources,
805 .num_resources = ARRAY_SIZE(ssc1_resources),
808 static inline void configure_ssc1_pins(unsigned pins)
810 if (pins & ATMEL_SSC_TF)
811 at91_set_A_periph(AT91_PIN_PB6, 1);
812 if (pins & ATMEL_SSC_TK)
813 at91_set_A_periph(AT91_PIN_PB7, 1);
814 if (pins & ATMEL_SSC_TD)
815 at91_set_A_periph(AT91_PIN_PB8, 1);
816 if (pins & ATMEL_SSC_RD)
817 at91_set_A_periph(AT91_PIN_PB9, 1);
818 if (pins & ATMEL_SSC_RK)
819 at91_set_A_periph(AT91_PIN_PB10, 1);
820 if (pins & ATMEL_SSC_RF)
821 at91_set_A_periph(AT91_PIN_PB11, 1);
824 static u64 ssc2_dmamask = DMA_BIT_MASK(32);
826 static struct resource ssc2_resources[] = {
828 .start = AT91RM9200_BASE_SSC2,
829 .end = AT91RM9200_BASE_SSC2 + SZ_16K - 1,
830 .flags = IORESOURCE_MEM,
833 .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
834 .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
835 .flags = IORESOURCE_IRQ,
839 static struct platform_device at91rm9200_ssc2_device = {
840 .name = "at91rm9200_ssc",
843 .dma_mask = &ssc2_dmamask,
844 .coherent_dma_mask = DMA_BIT_MASK(32),
846 .resource = ssc2_resources,
847 .num_resources = ARRAY_SIZE(ssc2_resources),
850 static inline void configure_ssc2_pins(unsigned pins)
852 if (pins & ATMEL_SSC_TF)
853 at91_set_A_periph(AT91_PIN_PB12, 1);
854 if (pins & ATMEL_SSC_TK)
855 at91_set_A_periph(AT91_PIN_PB13, 1);
856 if (pins & ATMEL_SSC_TD)
857 at91_set_A_periph(AT91_PIN_PB14, 1);
858 if (pins & ATMEL_SSC_RD)
859 at91_set_A_periph(AT91_PIN_PB15, 1);
860 if (pins & ATMEL_SSC_RK)
861 at91_set_A_periph(AT91_PIN_PB16, 1);
862 if (pins & ATMEL_SSC_RF)
863 at91_set_A_periph(AT91_PIN_PB17, 1);
867 * SSC controllers are accessed through library code, instead of any
868 * kind of all-singing/all-dancing driver. For example one could be
869 * used by a particular I2S audio codec's driver, while another one
870 * on the same system might be used by a custom data capture driver.
872 void __init at91_add_device_ssc(unsigned id, unsigned pins)
874 struct platform_device *pdev;
877 * NOTE: caller is responsible for passing information matching
878 * "pins" to whatever will be using each particular controller.
881 case AT91RM9200_ID_SSC0:
882 pdev = &at91rm9200_ssc0_device;
883 configure_ssc0_pins(pins);
885 case AT91RM9200_ID_SSC1:
886 pdev = &at91rm9200_ssc1_device;
887 configure_ssc1_pins(pins);
889 case AT91RM9200_ID_SSC2:
890 pdev = &at91rm9200_ssc2_device;
891 configure_ssc2_pins(pins);
897 platform_device_register(pdev);
901 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
905 /* --------------------------------------------------------------------
907 * -------------------------------------------------------------------- */
909 #if defined(CONFIG_SERIAL_ATMEL)
910 static struct resource dbgu_resources[] = {
912 .start = AT91RM9200_BASE_DBGU,
913 .end = AT91RM9200_BASE_DBGU + SZ_512 - 1,
914 .flags = IORESOURCE_MEM,
917 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
918 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
919 .flags = IORESOURCE_IRQ,
923 static struct atmel_uart_data dbgu_data = {
925 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
929 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
931 static struct platform_device at91rm9200_dbgu_device = {
932 .name = "atmel_usart",
935 .dma_mask = &dbgu_dmamask,
936 .coherent_dma_mask = DMA_BIT_MASK(32),
937 .platform_data = &dbgu_data,
939 .resource = dbgu_resources,
940 .num_resources = ARRAY_SIZE(dbgu_resources),
943 static inline void configure_dbgu_pins(void)
945 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
946 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
949 static struct resource uart0_resources[] = {
951 .start = AT91RM9200_BASE_US0,
952 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
953 .flags = IORESOURCE_MEM,
956 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
957 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
958 .flags = IORESOURCE_IRQ,
962 static struct atmel_uart_data uart0_data = {
968 static u64 uart0_dmamask = DMA_BIT_MASK(32);
970 static struct platform_device at91rm9200_uart0_device = {
971 .name = "atmel_usart",
974 .dma_mask = &uart0_dmamask,
975 .coherent_dma_mask = DMA_BIT_MASK(32),
976 .platform_data = &uart0_data,
978 .resource = uart0_resources,
979 .num_resources = ARRAY_SIZE(uart0_resources),
982 static inline void configure_usart0_pins(unsigned pins)
984 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
985 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
987 if (pins & ATMEL_UART_CTS)
988 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
990 if (pins & ATMEL_UART_RTS) {
992 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
993 * We need to drive the pin manually. The serial driver will driver
994 * this to high when initializing.
996 uart0_data.rts_gpio = AT91_PIN_PA21;
1000 static struct resource uart1_resources[] = {
1002 .start = AT91RM9200_BASE_US1,
1003 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
1004 .flags = IORESOURCE_MEM,
1007 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1008 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
1009 .flags = IORESOURCE_IRQ,
1013 static struct atmel_uart_data uart1_data = {
1016 .rts_gpio = -EINVAL,
1019 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1021 static struct platform_device at91rm9200_uart1_device = {
1022 .name = "atmel_usart",
1025 .dma_mask = &uart1_dmamask,
1026 .coherent_dma_mask = DMA_BIT_MASK(32),
1027 .platform_data = &uart1_data,
1029 .resource = uart1_resources,
1030 .num_resources = ARRAY_SIZE(uart1_resources),
1033 static inline void configure_usart1_pins(unsigned pins)
1035 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
1036 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
1038 if (pins & ATMEL_UART_RI)
1039 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
1040 if (pins & ATMEL_UART_DTR)
1041 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
1042 if (pins & ATMEL_UART_DCD)
1043 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
1044 if (pins & ATMEL_UART_CTS)
1045 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
1046 if (pins & ATMEL_UART_DSR)
1047 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
1048 if (pins & ATMEL_UART_RTS)
1049 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
1052 static struct resource uart2_resources[] = {
1054 .start = AT91RM9200_BASE_US2,
1055 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
1056 .flags = IORESOURCE_MEM,
1059 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1060 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
1061 .flags = IORESOURCE_IRQ,
1065 static struct atmel_uart_data uart2_data = {
1068 .rts_gpio = -EINVAL,
1071 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1073 static struct platform_device at91rm9200_uart2_device = {
1074 .name = "atmel_usart",
1077 .dma_mask = &uart2_dmamask,
1078 .coherent_dma_mask = DMA_BIT_MASK(32),
1079 .platform_data = &uart2_data,
1081 .resource = uart2_resources,
1082 .num_resources = ARRAY_SIZE(uart2_resources),
1085 static inline void configure_usart2_pins(unsigned pins)
1087 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
1088 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
1090 if (pins & ATMEL_UART_CTS)
1091 at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
1092 if (pins & ATMEL_UART_RTS)
1093 at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
1096 static struct resource uart3_resources[] = {
1098 .start = AT91RM9200_BASE_US3,
1099 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
1100 .flags = IORESOURCE_MEM,
1103 .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1104 .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
1105 .flags = IORESOURCE_IRQ,
1109 static struct atmel_uart_data uart3_data = {
1112 .rts_gpio = -EINVAL,
1115 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1117 static struct platform_device at91rm9200_uart3_device = {
1118 .name = "atmel_usart",
1121 .dma_mask = &uart3_dmamask,
1122 .coherent_dma_mask = DMA_BIT_MASK(32),
1123 .platform_data = &uart3_data,
1125 .resource = uart3_resources,
1126 .num_resources = ARRAY_SIZE(uart3_resources),
1129 static inline void configure_usart3_pins(unsigned pins)
1131 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
1132 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
1134 if (pins & ATMEL_UART_CTS)
1135 at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
1136 if (pins & ATMEL_UART_RTS)
1137 at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
1140 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1142 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1144 struct platform_device *pdev;
1145 struct atmel_uart_data *pdata;
1149 pdev = &at91rm9200_dbgu_device;
1150 configure_dbgu_pins();
1152 case AT91RM9200_ID_US0:
1153 pdev = &at91rm9200_uart0_device;
1154 configure_usart0_pins(pins);
1156 case AT91RM9200_ID_US1:
1157 pdev = &at91rm9200_uart1_device;
1158 configure_usart1_pins(pins);
1160 case AT91RM9200_ID_US2:
1161 pdev = &at91rm9200_uart2_device;
1162 configure_usart2_pins(pins);
1164 case AT91RM9200_ID_US3:
1165 pdev = &at91rm9200_uart3_device;
1166 configure_usart3_pins(pins);
1171 pdata = pdev->dev.platform_data;
1172 pdata->num = portnr; /* update to mapped ID */
1174 if (portnr < ATMEL_MAX_UART)
1175 at91_uarts[portnr] = pdev;
1178 void __init at91_add_device_serial(void)
1182 for (i = 0; i < ATMEL_MAX_UART; i++) {
1184 platform_device_register(at91_uarts[i]);
1188 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1189 void __init at91_add_device_serial(void) {}
1193 /* -------------------------------------------------------------------- */
1196 * These devices are always present and don't need any board-specific
1199 static int __init at91_add_standard_devices(void)
1201 at91_add_device_rtc();
1202 at91_add_device_watchdog();
1203 at91_add_device_tc();
1207 arch_initcall(at91_add_standard_devices);