arch/arm/mach-at91/at91sam9g45.c

   1 /*
   2  *  Chip-specific setup code for the AT91SAM9G45 family
   3  *
   4  *  Copyright (C) 2009 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/dma-mapping.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/at91sam9g45.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/cpu.h>
  22
  23 #include "soc.h"
  24 #include "generic.h"
  25 #include "clock.h"
  26 #include "sam9_smc.h"
  27
  28 /* --------------------------------------------------------------------
  29  *  Clocks
  30  * -------------------------------------------------------------------- */
  31
  32 /*
  33  * The peripheral clocks.
  34  */
  35 static struct clk pioA_clk = {
  36         .name           = "pioA_clk",
  37         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOA,
  38         .type           = CLK_TYPE_PERIPHERAL,
  39 };
  40 static struct clk pioB_clk = {
  41         .name           = "pioB_clk",
  42         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOB,
  43         .type           = CLK_TYPE_PERIPHERAL,
  44 };
  45 static struct clk pioC_clk = {
  46         .name           = "pioC_clk",
  47         .pmc_mask       = 1 << AT91SAM9G45_ID_PIOC,
  48         .type           = CLK_TYPE_PERIPHERAL,
  49 };
  50 static struct clk pioDE_clk = {
  51         .name           = "pioDE_clk",
  52         .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
  53         .type           = CLK_TYPE_PERIPHERAL,
  54 };
  55 static struct clk trng_clk = {
  56         .name           = "trng_clk",
  57         .pmc_mask       = 1 << AT91SAM9G45_ID_TRNG,
  58         .type           = CLK_TYPE_PERIPHERAL,
  59 };
  60 static struct clk usart0_clk = {
  61         .name           = "usart0_clk",
  62         .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
  63         .type           = CLK_TYPE_PERIPHERAL,
  64 };
  65 static struct clk usart1_clk = {
  66         .name           = "usart1_clk",
  67         .pmc_mask       = 1 << AT91SAM9G45_ID_US1,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk usart2_clk = {
  71         .name           = "usart2_clk",
  72         .pmc_mask       = 1 << AT91SAM9G45_ID_US2,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk usart3_clk = {
  76         .name           = "usart3_clk",
  77         .pmc_mask       = 1 << AT91SAM9G45_ID_US3,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk mmc0_clk = {
  81         .name           = "mci0_clk",
  82         .pmc_mask       = 1 << AT91SAM9G45_ID_MCI0,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk twi0_clk = {
  86         .name           = "twi0_clk",
  87         .pmc_mask       = 1 << AT91SAM9G45_ID_TWI0,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk twi1_clk = {
  91         .name           = "twi1_clk",
  92         .pmc_mask       = 1 << AT91SAM9G45_ID_TWI1,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk spi0_clk = {
  96         .name           = "spi0_clk",
  97         .pmc_mask       = 1 << AT91SAM9G45_ID_SPI0,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk spi1_clk = {
 101         .name           = "spi1_clk",
 102         .pmc_mask       = 1 << AT91SAM9G45_ID_SPI1,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk ssc0_clk = {
 106         .name           = "ssc0_clk",
 107         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC0,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk ssc1_clk = {
 111         .name           = "ssc1_clk",
 112         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk tcb0_clk = {
 116         .name           = "tcb0_clk",
 117         .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk pwm_clk = {
 121         .name           = "pwm_clk",
 122         .pmc_mask       = 1 << AT91SAM9G45_ID_PWMC,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk tsc_clk = {
 126         .name           = "tsc_clk",
 127         .pmc_mask       = 1 << AT91SAM9G45_ID_TSC,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk dma_clk = {
 131         .name           = "dma_clk",
 132         .pmc_mask       = 1 << AT91SAM9G45_ID_DMA,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk uhphs_clk = {
 136         .name           = "uhphs_clk",
 137         .pmc_mask       = 1 << AT91SAM9G45_ID_UHPHS,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk lcdc_clk = {
 141         .name           = "lcdc_clk",
 142         .pmc_mask       = 1 << AT91SAM9G45_ID_LCDC,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk ac97_clk = {
 146         .name           = "ac97_clk",
 147         .pmc_mask       = 1 << AT91SAM9G45_ID_AC97C,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk macb_clk = {
 151         .name           = "pclk",
 152         .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155 static struct clk isi_clk = {
 156         .name           = "isi_clk",
 157         .pmc_mask       = 1 << AT91SAM9G45_ID_ISI,
 158         .type           = CLK_TYPE_PERIPHERAL,
 159 };
 160 static struct clk udphs_clk = {
 161         .name           = "udphs_clk",
 162         .pmc_mask       = 1 << AT91SAM9G45_ID_UDPHS,
 163         .type           = CLK_TYPE_PERIPHERAL,
 164 };
 165 static struct clk mmc1_clk = {
 166         .name           = "mci1_clk",
 167         .pmc_mask       = 1 << AT91SAM9G45_ID_MCI1,
 168         .type           = CLK_TYPE_PERIPHERAL,
 169 };
 170
 171 /* Video decoder clock - Only for sam9m10/sam9m11 */
 172 static struct clk vdec_clk = {
 173         .name           = "vdec_clk",
 174         .pmc_mask       = 1 << AT91SAM9G45_ID_VDEC,
 175         .type           = CLK_TYPE_PERIPHERAL,
 176 };
 177
 178 static struct clk *periph_clocks[] __initdata = {
 179         &pioA_clk,
 180         &pioB_clk,
 181         &pioC_clk,
 182         &pioDE_clk,
 183         &trng_clk,
 184         &usart0_clk,
 185         &usart1_clk,
 186         &usart2_clk,
 187         &usart3_clk,
 188         &mmc0_clk,
 189         &twi0_clk,
 190         &twi1_clk,
 191         &spi0_clk,
 192         &spi1_clk,
 193         &ssc0_clk,
 194         &ssc1_clk,
 195         &tcb0_clk,
 196         &pwm_clk,
 197         &tsc_clk,
 198         &dma_clk,
 199         &uhphs_clk,
 200         &lcdc_clk,
 201         &ac97_clk,
 202         &macb_clk,
 203         &isi_clk,
 204         &udphs_clk,
 205         &mmc1_clk,
 206         // irq0
 207 };
 208
 209 static struct clk_lookup periph_clocks_lookups[] = {
 210         /* One additional fake clock for macb_hclk */
 211         CLKDEV_CON_ID("hclk", &macb_clk),
 212         /* One additional fake clock for ohci */
 213         CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
 214         CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
 215         CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
 216         CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
 217         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
 218         CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
 219         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 220         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 221         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
 222         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
 223         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 224         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 225         CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
 226         /* more usart lookup table for DT entries */
 227         CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
 228         CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
 229         CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
 230         CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
 231         CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
 232         /* fake hclk clock */
 233         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 234         CLKDEV_CON_ID("pioA", &pioA_clk),
 235         CLKDEV_CON_ID("pioB", &pioB_clk),
 236         CLKDEV_CON_ID("pioC", &pioC_clk),
 237         CLKDEV_CON_ID("pioD", &pioDE_clk),
 238         CLKDEV_CON_ID("pioE", &pioDE_clk),
 239 };
 240
 241 static struct clk_lookup usart_clocks_lookups[] = {
 242         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 243         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 244         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 245         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 246         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 247 };
 248
 249 /*
 250  * The two programmable clocks.
 251  * You must configure pin multiplexing to bring these signals out.
 252  */
 253 static struct clk pck0 = {
 254         .name           = "pck0",
 255         .pmc_mask       = AT91_PMC_PCK0,
 256         .type           = CLK_TYPE_PROGRAMMABLE,
 257         .id             = 0,
 258 };
 259 static struct clk pck1 = {
 260         .name           = "pck1",
 261         .pmc_mask       = AT91_PMC_PCK1,
 262         .type           = CLK_TYPE_PROGRAMMABLE,
 263         .id             = 1,
 264 };
 265
 266 static void __init at91sam9g45_register_clocks(void)
 267 {
 268         int i;
 269
 270         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 271                 clk_register(periph_clocks[i]);
 272
 273         clkdev_add_table(periph_clocks_lookups,
 274                          ARRAY_SIZE(periph_clocks_lookups));
 275         clkdev_add_table(usart_clocks_lookups,
 276                          ARRAY_SIZE(usart_clocks_lookups));
 277
 278         if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
 279                 clk_register(&vdec_clk);
 280
 281         clk_register(&pck0);
 282         clk_register(&pck1);
 283 }
 284
 285 static struct clk_lookup console_clock_lookup;
 286
 287 void __init at91sam9g45_set_console_clock(int id)
 288 {
 289         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 290                 return;
 291
 292         console_clock_lookup.con_id = "usart";
 293         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 294         clkdev_add(&console_clock_lookup);
 295 }
 296
 297 /* --------------------------------------------------------------------
 298  *  GPIO
 299  * -------------------------------------------------------------------- */
 300
 301 static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
 302         {
 303                 .id             = AT91SAM9G45_ID_PIOA,
 304                 .regbase        = AT91SAM9G45_BASE_PIOA,
 305         }, {
 306                 .id             = AT91SAM9G45_ID_PIOB,
 307                 .regbase        = AT91SAM9G45_BASE_PIOB,
 308         }, {
 309                 .id             = AT91SAM9G45_ID_PIOC,
 310                 .regbase        = AT91SAM9G45_BASE_PIOC,
 311         }, {
 312                 .id             = AT91SAM9G45_ID_PIODE,
 313                 .regbase        = AT91SAM9G45_BASE_PIOD,
 314         }, {
 315                 .id             = AT91SAM9G45_ID_PIODE,
 316                 .regbase        = AT91SAM9G45_BASE_PIOE,
 317         }
 318 };
 319
 320 /* --------------------------------------------------------------------
 321  *  AT91SAM9G45 processor initialization
 322  * -------------------------------------------------------------------- */
 323
 324 static void __init at91sam9g45_map_io(void)
 325 {
 326         at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
 327         init_consistent_dma_size(SZ_4M);
 328 }
 329
 330 static void __init at91sam9g45_ioremap_registers(void)
 331 {
 332         at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
 333         at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
 334         at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
 335         at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
 336 }
 337
 338 static void __init at91sam9g45_initialize(void)
 339 {
 340         arm_pm_restart = at91sam9g45_restart;
 341         at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 342
 343         /* Register GPIO subsystem */
 344         at91_gpio_init(at91sam9g45_gpio, 5);
 345 }
 346
 347 /* --------------------------------------------------------------------
 348  *  Interrupt initialization
 349  * -------------------------------------------------------------------- */
 350
 351 /*
 352  * The default interrupt priority levels (0 = lowest, 7 = highest).
 353  */
 354 static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
 355         7,      /* Advanced Interrupt Controller (FIQ) */
 356         7,      /* System Peripherals */
 357         1,      /* Parallel IO Controller A */
 358         1,      /* Parallel IO Controller B */
 359         1,      /* Parallel IO Controller C */
 360         1,      /* Parallel IO Controller D and E */
 361         0,
 362         5,      /* USART 0 */
 363         5,      /* USART 1 */
 364         5,      /* USART 2 */
 365         5,      /* USART 3 */
 366         0,      /* Multimedia Card Interface 0 */
 367         6,      /* Two-Wire Interface 0 */
 368         6,      /* Two-Wire Interface 1 */
 369         5,      /* Serial Peripheral Interface 0 */
 370         5,      /* Serial Peripheral Interface 1 */
 371         4,      /* Serial Synchronous Controller 0 */
 372         4,      /* Serial Synchronous Controller 1 */
 373         0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
 374         0,      /* Pulse Width Modulation Controller */
 375         0,      /* Touch Screen Controller */
 376         0,      /* DMA Controller */
 377         2,      /* USB Host High Speed port */
 378         3,      /* LDC Controller */
 379         5,      /* AC97 Controller */
 380         3,      /* Ethernet */
 381         0,      /* Image Sensor Interface */
 382         2,      /* USB Device High speed port */
 383         0,
 384         0,      /* Multimedia Card Interface 1 */
 385         0,
 386         0,      /* Advanced Interrupt Controller (IRQ0) */
 387 };
 388
 389 struct at91_init_soc __initdata at91sam9g45_soc = {
 390         .map_io = at91sam9g45_map_io,
 391         .default_irq_priority = at91sam9g45_default_irq_priority,
 392         .ioremap_registers = at91sam9g45_ioremap_registers,
 393         .register_clocks = at91sam9g45_register_clocks,
 394         .init = at91sam9g45_initialize,
 395 };