2 * linux/arch/arm/mach-at91/gpio.c
4 * Copyright (C) 2005 HP Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/clk.h>
13 #include <linux/errno.h>
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/debugfs.h>
19 #include <linux/seq_file.h>
20 #include <linux/kernel.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_gpio.h>
29 #include <mach/hardware.h>
30 #include <mach/at91_pio.h>
34 struct at91_gpio_chip {
35 struct gpio_chip chip;
36 struct at91_gpio_chip *next; /* Bank sharing same clock */
37 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
38 int pioc_virq; /* PIO bank Linux virtual interrupt */
39 int pioc_idx; /* PIO bank index */
40 void __iomem *regbase; /* PIO bank virtual address */
41 struct clk *clock; /* associated clock */
42 struct irq_domain *domain; /* associated irq domain */
45 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
47 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
48 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
49 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
50 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
51 unsigned offset, int val);
52 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
54 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
56 #define AT91_GPIO_CHIP(name, nr_gpio) \
60 .direction_input = at91_gpiolib_direction_input, \
61 .direction_output = at91_gpiolib_direction_output, \
62 .get = at91_gpiolib_get, \
63 .set = at91_gpiolib_set, \
64 .dbg_show = at91_gpiolib_dbg_show, \
65 .to_irq = at91_gpiolib_to_irq, \
70 static struct at91_gpio_chip gpio_chip[] = {
71 AT91_GPIO_CHIP("pioA", 32),
72 AT91_GPIO_CHIP("pioB", 32),
73 AT91_GPIO_CHIP("pioC", 32),
74 AT91_GPIO_CHIP("pioD", 32),
75 AT91_GPIO_CHIP("pioE", 32),
78 static int gpio_banks;
80 static inline void __iomem *pin_to_controller(unsigned pin)
83 if (likely(pin < gpio_banks))
84 return gpio_chip[pin].regbase;
89 static inline unsigned pin_to_mask(unsigned pin)
91 return 1 << (pin % 32);
95 /*--------------------------------------------------------------------------*/
97 /* Not all hardware capabilities are exposed through these calls; they
98 * only encapsulate the most common features and modes. (So if you
99 * want to change signals in groups, do it directly.)
101 * Bootloaders will usually handle some of the pin multiplexing setup.
102 * The intent is certainly that by the time Linux is fully booted, all
103 * pins should have been fully initialized. These setup calls should
104 * only be used by board setup routines, or possibly in driver probe().
106 * For bootloaders doing all that setup, these calls could be inlined
107 * as NOPs so Linux won't duplicate any setup code
112 * mux the pin to the "GPIO" peripheral role.
114 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
116 void __iomem *pio = pin_to_controller(pin);
117 unsigned mask = pin_to_mask(pin);
121 __raw_writel(mask, pio + PIO_IDR);
122 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
123 __raw_writel(mask, pio + PIO_PER);
126 EXPORT_SYMBOL(at91_set_GPIO_periph);
130 * mux the pin to the "A" internal peripheral role.
132 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
134 void __iomem *pio = pin_to_controller(pin);
135 unsigned mask = pin_to_mask(pin);
140 __raw_writel(mask, pio + PIO_IDR);
141 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
142 __raw_writel(mask, pio + PIO_ASR);
143 __raw_writel(mask, pio + PIO_PDR);
146 EXPORT_SYMBOL(at91_set_A_periph);
150 * mux the pin to the "B" internal peripheral role.
152 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
154 void __iomem *pio = pin_to_controller(pin);
155 unsigned mask = pin_to_mask(pin);
160 __raw_writel(mask, pio + PIO_IDR);
161 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
162 __raw_writel(mask, pio + PIO_BSR);
163 __raw_writel(mask, pio + PIO_PDR);
166 EXPORT_SYMBOL(at91_set_B_periph);
170 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
171 * configure it for an input.
173 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
175 void __iomem *pio = pin_to_controller(pin);
176 unsigned mask = pin_to_mask(pin);
181 __raw_writel(mask, pio + PIO_IDR);
182 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
183 __raw_writel(mask, pio + PIO_ODR);
184 __raw_writel(mask, pio + PIO_PER);
187 EXPORT_SYMBOL(at91_set_gpio_input);
191 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
192 * and configure it for an output.
194 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
196 void __iomem *pio = pin_to_controller(pin);
197 unsigned mask = pin_to_mask(pin);
202 __raw_writel(mask, pio + PIO_IDR);
203 __raw_writel(mask, pio + PIO_PUDR);
204 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
205 __raw_writel(mask, pio + PIO_OER);
206 __raw_writel(mask, pio + PIO_PER);
209 EXPORT_SYMBOL(at91_set_gpio_output);
213 * enable/disable the glitch filter; mostly used with IRQ handling.
215 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
217 void __iomem *pio = pin_to_controller(pin);
218 unsigned mask = pin_to_mask(pin);
222 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
225 EXPORT_SYMBOL(at91_set_deglitch);
228 * enable/disable the multi-driver; This is only valid for output and
229 * allows the output pin to run as an open collector output.
231 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
233 void __iomem *pio = pin_to_controller(pin);
234 unsigned mask = pin_to_mask(pin);
239 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
242 EXPORT_SYMBOL(at91_set_multi_drive);
245 * assuming the pin is muxed as a gpio output, set its value.
247 int at91_set_gpio_value(unsigned pin, int value)
249 void __iomem *pio = pin_to_controller(pin);
250 unsigned mask = pin_to_mask(pin);
254 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
257 EXPORT_SYMBOL(at91_set_gpio_value);
261 * read the pin's value (works even if it's not muxed as a gpio).
263 int at91_get_gpio_value(unsigned pin)
265 void __iomem *pio = pin_to_controller(pin);
266 unsigned mask = pin_to_mask(pin);
271 pdsr = __raw_readl(pio + PIO_PDSR);
272 return (pdsr & mask) != 0;
274 EXPORT_SYMBOL(at91_get_gpio_value);
276 /*--------------------------------------------------------------------------*/
280 static u32 wakeups[MAX_GPIO_BANKS];
281 static u32 backups[MAX_GPIO_BANKS];
283 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
285 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
286 unsigned mask = 1 << d->hwirq;
287 unsigned bank = at91_gpio->pioc_idx;
289 if (unlikely(bank >= MAX_GPIO_BANKS))
293 wakeups[bank] |= mask;
295 wakeups[bank] &= ~mask;
297 irq_set_irq_wake(at91_gpio->pioc_virq, state);
302 void at91_gpio_suspend(void)
306 for (i = 0; i < gpio_banks; i++) {
307 void __iomem *pio = gpio_chip[i].regbase;
309 backups[i] = __raw_readl(pio + PIO_IMR);
310 __raw_writel(backups[i], pio + PIO_IDR);
311 __raw_writel(wakeups[i], pio + PIO_IER);
314 clk_unprepare(gpio_chip[i].clock);
315 clk_disable(gpio_chip[i].clock);
317 #ifdef CONFIG_PM_DEBUG
318 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
324 void at91_gpio_resume(void)
328 for (i = 0; i < gpio_banks; i++) {
329 void __iomem *pio = gpio_chip[i].regbase;
332 if (clk_prepare(gpio_chip[i].clock) == 0)
333 clk_enable(gpio_chip[i].clock);
336 __raw_writel(wakeups[i], pio + PIO_IDR);
337 __raw_writel(backups[i], pio + PIO_IER);
342 #define gpio_irq_set_wake NULL
346 /* Several AIC controller irqs are dispatched through this GPIO handler.
347 * To use any AT91_PIN_* as an externally triggered IRQ, first call
348 * at91_set_gpio_input() then maybe enable its glitch filter.
349 * Then just request_irq() with the pin ID; it works like any ARM IRQ
350 * handler, though it always triggers on rising and falling edges.
352 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
353 * configuring them with at91_set_a_periph() or at91_set_b_periph().
354 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
357 static void gpio_irq_mask(struct irq_data *d)
359 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
360 void __iomem *pio = at91_gpio->regbase;
361 unsigned mask = 1 << d->hwirq;
364 __raw_writel(mask, pio + PIO_IDR);
367 static void gpio_irq_unmask(struct irq_data *d)
369 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
370 void __iomem *pio = at91_gpio->regbase;
371 unsigned mask = 1 << d->hwirq;
374 __raw_writel(mask, pio + PIO_IER);
377 static int gpio_irq_type(struct irq_data *d, unsigned type)
381 case IRQ_TYPE_EDGE_BOTH:
388 static struct irq_chip gpio_irqchip = {
390 .irq_disable = gpio_irq_mask,
391 .irq_mask = gpio_irq_mask,
392 .irq_unmask = gpio_irq_unmask,
393 .irq_set_type = gpio_irq_type,
394 .irq_set_wake = gpio_irq_set_wake,
397 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
399 struct irq_data *idata = irq_desc_get_irq_data(desc);
400 struct irq_chip *chip = irq_data_get_irq_chip(idata);
401 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
402 void __iomem *pio = at91_gpio->regbase;
406 /* temporarily mask (level sensitive) parent IRQ */
407 chip->irq_ack(idata);
409 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
410 * When there none are pending, we're finished unless we need
411 * to process multiple banks (like ID_PIOCDE on sam9263).
413 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
415 if (!at91_gpio->next)
417 at91_gpio = at91_gpio->next;
418 pio = at91_gpio->regbase;
422 n = find_first_bit(&isr, BITS_PER_LONG);
423 while (n < BITS_PER_LONG) {
424 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
425 n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
428 chip->irq_unmask(idata);
429 /* now it may re-trigger */
432 /*--------------------------------------------------------------------------*/
434 #ifdef CONFIG_DEBUG_FS
436 static int at91_gpio_show(struct seq_file *s, void *unused)
441 seq_printf(s, "Pin\t");
442 for (bank = 0; bank < gpio_banks; bank++) {
443 seq_printf(s, "PIO%c\t", 'A' + bank);
445 seq_printf(s, "\n\n");
447 /* print pin status */
448 for (j = 0; j < 32; j++) {
449 seq_printf(s, "%i:\t", j);
451 for (bank = 0; bank < gpio_banks; bank++) {
452 unsigned pin = (32 * bank) + j;
453 void __iomem *pio = pin_to_controller(pin);
454 unsigned mask = pin_to_mask(pin);
456 if (__raw_readl(pio + PIO_PSR) & mask)
457 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
459 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
470 static int at91_gpio_open(struct inode *inode, struct file *file)
472 return single_open(file, at91_gpio_show, NULL);
475 static const struct file_operations at91_gpio_operations = {
476 .open = at91_gpio_open,
479 .release = single_release,
482 static int __init at91_gpio_debugfs_init(void)
484 /* /sys/kernel/debug/at91_gpio */
485 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
488 postcore_initcall(at91_gpio_debugfs_init);
492 /*--------------------------------------------------------------------------*/
495 * This lock class tells lockdep that GPIO irqs are in a different
496 * category than their parents, so it won't report false recursion.
498 static struct lock_class_key gpio_lock_class;
500 #if defined(CONFIG_OF)
501 static int at91_gpio_irq_map(struct irq_domain *h, unsigned int virq,
504 struct at91_gpio_chip *at91_gpio = h->host_data;
506 irq_set_lockdep_class(virq, &gpio_lock_class);
509 * Can use the "simple" and not "edge" handler since it's
510 * shorter, and the AIC handles interrupts sanely.
512 irq_set_chip_and_handler(virq, &gpio_irqchip,
514 set_irq_flags(virq, IRQF_VALID);
515 irq_set_chip_data(virq, at91_gpio);
520 static struct irq_domain_ops at91_gpio_ops = {
521 .map = at91_gpio_irq_map,
522 .xlate = irq_domain_xlate_twocell,
525 int __init at91_gpio_of_irq_setup(struct device_node *node,
526 struct device_node *parent)
528 struct at91_gpio_chip *prev = NULL;
529 int alias_idx = of_alias_get_id(node, "gpio");
530 struct at91_gpio_chip *at91_gpio = &gpio_chip[alias_idx];
532 /* Disable irqs of this PIO controller */
533 __raw_writel(~0, at91_gpio->regbase + PIO_IDR);
535 /* Setup irq domain */
536 at91_gpio->domain = irq_domain_add_linear(node, at91_gpio->chip.ngpio,
537 &at91_gpio_ops, at91_gpio);
538 if (!at91_gpio->domain)
539 panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
540 at91_gpio->pioc_idx);
542 /* Setup chained handler */
543 if (at91_gpio->pioc_idx)
544 prev = &gpio_chip[at91_gpio->pioc_idx - 1];
546 /* The toplevel handler handles one bank of GPIOs, except
547 * on some SoC it can handles up to three...
548 * We only set up the handler for the first of the list.
550 if (prev && prev->next == at91_gpio)
553 at91_gpio->pioc_virq = irq_create_mapping(irq_find_host(parent),
554 at91_gpio->pioc_hwirq);
555 irq_set_chip_data(at91_gpio->pioc_virq, at91_gpio);
556 irq_set_chained_handler(at91_gpio->pioc_virq, gpio_irq_handler);
561 int __init at91_gpio_of_irq_setup(struct device_node *node,
562 struct device_node *parent)
569 * irqdomain initialization: pile up irqdomains on top of AIC range
571 static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
575 irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
577 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
578 at91_gpio->pioc_idx, irq_base);
579 at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
581 &irq_domain_simple_ops, NULL);
582 if (!at91_gpio->domain)
583 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
584 at91_gpio->pioc_idx);
588 * Called from the processor-specific init to enable GPIO interrupt support.
590 void __init at91_gpio_irq_setup(void)
594 struct at91_gpio_chip *this, *prev;
596 for (pioc = 0, this = gpio_chip, prev = NULL;
598 prev = this, this++) {
601 __raw_writel(~0, this->regbase + PIO_IDR);
603 /* setup irq domain for this GPIO controller */
604 at91_gpio_irqdomain(this);
606 for (offset = 0; offset < this->chip.ngpio; offset++) {
607 unsigned int virq = irq_find_mapping(this->domain, offset);
608 irq_set_lockdep_class(virq, &gpio_lock_class);
611 * Can use the "simple" and not "edge" handler since it's
612 * shorter, and the AIC handles interrupts sanely.
614 irq_set_chip_and_handler(virq, &gpio_irqchip,
616 set_irq_flags(virq, IRQF_VALID);
617 irq_set_chip_data(virq, this);
622 /* The toplevel handler handles one bank of GPIOs, except
623 * on some SoC it can handles up to three...
624 * We only set up the handler for the first of the list.
626 if (prev && prev->next == this)
629 this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
630 irq_set_chip_data(this->pioc_virq, this);
631 irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
633 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
636 /* gpiolib support */
637 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
640 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
641 void __iomem *pio = at91_gpio->regbase;
642 unsigned mask = 1 << offset;
644 __raw_writel(mask, pio + PIO_ODR);
648 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
649 unsigned offset, int val)
651 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
652 void __iomem *pio = at91_gpio->regbase;
653 unsigned mask = 1 << offset;
655 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
656 __raw_writel(mask, pio + PIO_OER);
660 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
662 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
663 void __iomem *pio = at91_gpio->regbase;
664 unsigned mask = 1 << offset;
667 pdsr = __raw_readl(pio + PIO_PDSR);
668 return (pdsr & mask) != 0;
671 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
673 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
674 void __iomem *pio = at91_gpio->regbase;
675 unsigned mask = 1 << offset;
677 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
680 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
684 for (i = 0; i < chip->ngpio; i++) {
685 unsigned pin = chip->base + i;
686 void __iomem *pio = pin_to_controller(pin);
687 unsigned mask = pin_to_mask(pin);
688 const char *gpio_label;
690 gpio_label = gpiochip_is_requested(chip, i);
692 seq_printf(s, "[%s] GPIO%s%d: ",
693 gpio_label, chip->label, i);
694 if (__raw_readl(pio + PIO_PSR) & mask)
695 seq_printf(s, "[gpio] %s\n",
696 at91_get_gpio_value(pin) ?
699 seq_printf(s, "[periph %s]\n",
700 __raw_readl(pio + PIO_ABSR) &
706 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
708 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
711 if (offset < chip->ngpio)
712 virq = irq_create_mapping(at91_gpio->domain, offset);
716 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
717 chip->label, offset + chip->base, virq);
721 static int __init at91_gpio_setup_clk(int idx)
723 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
725 /* retreive PIO controller's clock */
726 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
727 if (IS_ERR(at91_gpio->clock)) {
728 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
732 if (clk_prepare(at91_gpio->clock))
735 /* enable PIO controller's clock */
736 if (clk_enable(at91_gpio->clock)) {
737 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
744 clk_unprepare(at91_gpio->clock);
746 clk_put(at91_gpio->clock);
751 #ifdef CONFIG_OF_GPIO
752 static void __init of_at91_gpio_init_one(struct device_node *np)
755 struct at91_gpio_chip *at91_gpio;
760 alias_idx = of_alias_get_id(np, "gpio");
761 if (alias_idx >= MAX_GPIO_BANKS) {
762 pr_err("at91_gpio, failed alias idx(%d) > MAX_GPIO_BANKS(%d), ignoring.\n",
763 alias_idx, MAX_GPIO_BANKS);
767 at91_gpio = &gpio_chip[alias_idx];
768 at91_gpio->chip.base = alias_idx * at91_gpio->chip.ngpio;
770 at91_gpio->regbase = of_iomap(np, 0);
771 if (!at91_gpio->regbase) {
772 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n",
777 /* Get the interrupts property */
778 if (of_property_read_u32(np, "interrupts", &at91_gpio->pioc_hwirq)) {
779 pr_err("at91_gpio.%d, failed to get interrupts property, ignoring.\n",
785 if (at91_gpio_setup_clk(alias_idx))
788 at91_gpio->chip.of_node = np;
789 gpio_banks = max(gpio_banks, alias_idx + 1);
790 at91_gpio->pioc_idx = alias_idx;
794 iounmap(at91_gpio->regbase);
797 static int __init of_at91_gpio_init(void)
799 struct device_node *np = NULL;
802 * This isn't ideal, but it gets things hooked up until this
803 * driver is converted into a platform_device
805 for_each_compatible_node(np, NULL, "atmel,at91rm9200-gpio")
806 of_at91_gpio_init_one(np);
808 return gpio_banks > 0 ? 0 : -EINVAL;
811 static int __init of_at91_gpio_init(void)
817 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
819 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
821 at91_gpio->chip.base = idx * at91_gpio->chip.ngpio;
822 at91_gpio->pioc_hwirq = pioc_hwirq;
823 at91_gpio->pioc_idx = idx;
825 at91_gpio->regbase = ioremap(regbase, 512);
826 if (!at91_gpio->regbase) {
827 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
831 if (at91_gpio_setup_clk(idx))
834 gpio_banks = max(gpio_banks, idx + 1);
838 iounmap(at91_gpio->regbase);
842 * Called from the processor-specific init to enable GPIO pin support.
844 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
847 struct at91_gpio_chip *at91_gpio, *last = NULL;
849 BUG_ON(nr_banks > MAX_GPIO_BANKS);
851 if (of_at91_gpio_init() < 0) {
852 /* No GPIO controller found in device tree */
853 for (i = 0; i < nr_banks; i++)
854 at91_gpio_init_one(i, data[i].regbase, data[i].id);
857 for (i = 0; i < gpio_banks; i++) {
858 at91_gpio = &gpio_chip[i];
861 * GPIO controller are grouped on some SoC:
862 * PIOC, PIOD and PIOE can share the same IRQ line
864 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
865 last->next = at91_gpio;
868 gpiochip_add(&at91_gpio->chip);