arch/arm/mach-exynos/clock-exynos4.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27
  28 #include "common.h"
  29 #include "clock-exynos4.h"
  30
  31 #ifdef CONFIG_PM_SLEEP
  32 static struct sleep_save exynos4_clock_save[] = {
  33         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
  34         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
  35         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
  36         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
  37         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
  38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
  39         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
  40         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
  41         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
  42         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
  43         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
  44         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
  45         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
  46         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
  47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
  48         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
  49         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
  50         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
  51         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
  52         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
  53         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
  54         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
  55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
  56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
  57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
  58         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
  59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
  60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
  61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
  62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
  63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
  64         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
  65         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
  66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
  67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
  68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
  69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
  70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
  71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
  72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
  73         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
  74         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
  75         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
  76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
  77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
  78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
  79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
  80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
  81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
  82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
  83         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
  84         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
  85         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
  86         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
  87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
  88         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
  89         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
  90         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
  91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
  92         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
  93         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
  94 };
  95 #endif
  96
  97 static struct clk exynos4_clk_sclk_hdmi27m = {
  98         .name           = "sclk_hdmi27m",
  99         .rate           = 27000000,
 100 };
 101
 102 static struct clk exynos4_clk_sclk_hdmiphy = {
 103         .name           = "sclk_hdmiphy",
 104 };
 105
 106 static struct clk exynos4_clk_sclk_usbphy0 = {
 107         .name           = "sclk_usbphy0",
 108         .rate           = 27000000,
 109 };
 110
 111 static struct clk exynos4_clk_sclk_usbphy1 = {
 112         .name           = "sclk_usbphy1",
 113 };
 114
 115 static struct clk dummy_apb_pclk = {
 116         .name           = "apb_pclk",
 117         .id             = -1,
 118 };
 119
 120 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 121 {
 122         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 123 }
 124
 125 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 126 {
 127         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 128 }
 129
 130 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 131 {
 132         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 133 }
 134
 135 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 136 {
 137         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 138 }
 139
 140 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 141 {
 142         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 143 }
 144
 145 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 146 {
 147         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 148 }
 149
 150 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 151 {
 152         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 153 }
 154
 155 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 156 {
 157         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 158 }
 159
 160 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 161 {
 162         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 163 }
 164
 165 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 166 {
 167         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 168 }
 169
 170 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 171 {
 172         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 173 }
 174
 175 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 176 {
 177         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 178 }
 179
 180 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 181 {
 182         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 183 }
 184
 185 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 186 {
 187         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 188 }
 189
 190 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 191 {
 192         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 193 }
 194
 195 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 196 {
 197         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 198 }
 199
 200 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
 201 {
 202         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
 203 }
 204
 205 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 206 {
 207         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 208 }
 209
 210 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 211 {
 212         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 213 }
 214
 215 /* Core list of CMU_CPU side */
 216
 217 static struct clksrc_clk exynos4_clk_mout_apll = {
 218         .clk    = {
 219                 .name           = "mout_apll",
 220         },
 221         .sources = &clk_src_apll,
 222         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 223 };
 224
 225 static struct clksrc_clk exynos4_clk_sclk_apll = {
 226         .clk    = {
 227                 .name           = "sclk_apll",
 228                 .parent         = &exynos4_clk_mout_apll.clk,
 229         },
 230         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 231 };
 232
 233 static struct clksrc_clk exynos4_clk_mout_epll = {
 234         .clk    = {
 235                 .name           = "mout_epll",
 236         },
 237         .sources = &clk_src_epll,
 238         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 239 };
 240
 241 struct clksrc_clk exynos4_clk_mout_mpll = {
 242         .clk    = {
 243                 .name           = "mout_mpll",
 244         },
 245         .sources = &clk_src_mpll,
 246
 247         /* reg_src will be added in each SoCs' clock */
 248 };
 249
 250 static struct clk *exynos4_clkset_moutcore_list[] = {
 251         [0] = &exynos4_clk_mout_apll.clk,
 252         [1] = &exynos4_clk_mout_mpll.clk,
 253 };
 254
 255 static struct clksrc_sources exynos4_clkset_moutcore = {
 256         .sources        = exynos4_clkset_moutcore_list,
 257         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
 258 };
 259
 260 static struct clksrc_clk exynos4_clk_moutcore = {
 261         .clk    = {
 262                 .name           = "moutcore",
 263         },
 264         .sources = &exynos4_clkset_moutcore,
 265         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 266 };
 267
 268 static struct clksrc_clk exynos4_clk_coreclk = {
 269         .clk    = {
 270                 .name           = "core_clk",
 271                 .parent         = &exynos4_clk_moutcore.clk,
 272         },
 273         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 274 };
 275
 276 static struct clksrc_clk exynos4_clk_armclk = {
 277         .clk    = {
 278                 .name           = "armclk",
 279                 .parent         = &exynos4_clk_coreclk.clk,
 280         },
 281 };
 282
 283 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 284         .clk    = {
 285                 .name           = "aclk_corem0",
 286                 .parent         = &exynos4_clk_coreclk.clk,
 287         },
 288         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 289 };
 290
 291 static struct clksrc_clk exynos4_clk_aclk_cores = {
 292         .clk    = {
 293                 .name           = "aclk_cores",
 294                 .parent         = &exynos4_clk_coreclk.clk,
 295         },
 296         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 297 };
 298
 299 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 300         .clk    = {
 301                 .name           = "aclk_corem1",
 302                 .parent         = &exynos4_clk_coreclk.clk,
 303         },
 304         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 305 };
 306
 307 static struct clksrc_clk exynos4_clk_periphclk = {
 308         .clk    = {
 309                 .name           = "periphclk",
 310                 .parent         = &exynos4_clk_coreclk.clk,
 311         },
 312         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 313 };
 314
 315 /* Core list of CMU_CORE side */
 316
 317 static struct clk *exynos4_clkset_corebus_list[] = {
 318         [0] = &exynos4_clk_mout_mpll.clk,
 319         [1] = &exynos4_clk_sclk_apll.clk,
 320 };
 321
 322 struct clksrc_sources exynos4_clkset_mout_corebus = {
 323         .sources        = exynos4_clkset_corebus_list,
 324         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
 325 };
 326
 327 static struct clksrc_clk exynos4_clk_mout_corebus = {
 328         .clk    = {
 329                 .name           = "mout_corebus",
 330         },
 331         .sources = &exynos4_clkset_mout_corebus,
 332         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 333 };
 334
 335 static struct clksrc_clk exynos4_clk_sclk_dmc = {
 336         .clk    = {
 337                 .name           = "sclk_dmc",
 338                 .parent         = &exynos4_clk_mout_corebus.clk,
 339         },
 340         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 341 };
 342
 343 static struct clksrc_clk exynos4_clk_aclk_cored = {
 344         .clk    = {
 345                 .name           = "aclk_cored",
 346                 .parent         = &exynos4_clk_sclk_dmc.clk,
 347         },
 348         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 349 };
 350
 351 static struct clksrc_clk exynos4_clk_aclk_corep = {
 352         .clk    = {
 353                 .name           = "aclk_corep",
 354                 .parent         = &exynos4_clk_aclk_cored.clk,
 355         },
 356         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 357 };
 358
 359 static struct clksrc_clk exynos4_clk_aclk_acp = {
 360         .clk    = {
 361                 .name           = "aclk_acp",
 362                 .parent         = &exynos4_clk_mout_corebus.clk,
 363         },
 364         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 365 };
 366
 367 static struct clksrc_clk exynos4_clk_pclk_acp = {
 368         .clk    = {
 369                 .name           = "pclk_acp",
 370                 .parent         = &exynos4_clk_aclk_acp.clk,
 371         },
 372         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 373 };
 374
 375 /* Core list of CMU_TOP side */
 376
 377 struct clk *exynos4_clkset_aclk_top_list[] = {
 378         [0] = &exynos4_clk_mout_mpll.clk,
 379         [1] = &exynos4_clk_sclk_apll.clk,
 380 };
 381
 382 static struct clksrc_sources exynos4_clkset_aclk = {
 383         .sources        = exynos4_clkset_aclk_top_list,
 384         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 385 };
 386
 387 static struct clksrc_clk exynos4_clk_aclk_200 = {
 388         .clk    = {
 389                 .name           = "aclk_200",
 390         },
 391         .sources = &exynos4_clkset_aclk,
 392         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
 393         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 394 };
 395
 396 static struct clksrc_clk exynos4_clk_aclk_100 = {
 397         .clk    = {
 398                 .name           = "aclk_100",
 399         },
 400         .sources = &exynos4_clkset_aclk,
 401         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
 402         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 403 };
 404
 405 static struct clksrc_clk exynos4_clk_aclk_160 = {
 406         .clk    = {
 407                 .name           = "aclk_160",
 408         },
 409         .sources = &exynos4_clkset_aclk,
 410         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
 411         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 412 };
 413
 414 struct clksrc_clk exynos4_clk_aclk_133 = {
 415         .clk    = {
 416                 .name           = "aclk_133",
 417         },
 418         .sources = &exynos4_clkset_aclk,
 419         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
 420         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 421 };
 422
 423 static struct clk *exynos4_clkset_vpllsrc_list[] = {
 424         [0] = &clk_fin_vpll,
 425         [1] = &exynos4_clk_sclk_hdmi27m,
 426 };
 427
 428 static struct clksrc_sources exynos4_clkset_vpllsrc = {
 429         .sources        = exynos4_clkset_vpllsrc_list,
 430         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 431 };
 432
 433 static struct clksrc_clk exynos4_clk_vpllsrc = {
 434         .clk    = {
 435                 .name           = "vpll_src",
 436                 .enable         = exynos4_clksrc_mask_top_ctrl,
 437                 .ctrlbit        = (1 << 0),
 438         },
 439         .sources = &exynos4_clkset_vpllsrc,
 440         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 441 };
 442
 443 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
 444         [0] = &exynos4_clk_vpllsrc.clk,
 445         [1] = &clk_fout_vpll,
 446 };
 447
 448 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
 449         .sources        = exynos4_clkset_sclk_vpll_list,
 450         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 451 };
 452
 453 static struct clksrc_clk exynos4_clk_sclk_vpll = {
 454         .clk    = {
 455                 .name           = "sclk_vpll",
 456         },
 457         .sources = &exynos4_clkset_sclk_vpll,
 458         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 459 };
 460
 461 static struct clk exynos4_init_clocks_off[] = {
 462         {
 463                 .name           = "timers",
 464                 .parent         = &exynos4_clk_aclk_100.clk,
 465                 .enable         = exynos4_clk_ip_peril_ctrl,
 466                 .ctrlbit        = (1<<24),
 467         }, {
 468                 .name           = "csis",
 469                 .devname        = "s5p-mipi-csis.0",
 470                 .enable         = exynos4_clk_ip_cam_ctrl,
 471                 .ctrlbit        = (1 << 4),
 472         }, {
 473                 .name           = "csis",
 474                 .devname        = "s5p-mipi-csis.1",
 475                 .enable         = exynos4_clk_ip_cam_ctrl,
 476                 .ctrlbit        = (1 << 5),
 477         }, {
 478                 .name           = "jpeg",
 479                 .id             = 0,
 480                 .enable         = exynos4_clk_ip_cam_ctrl,
 481                 .ctrlbit        = (1 << 6),
 482         }, {
 483                 .name           = "fimc",
 484                 .devname        = "exynos4-fimc.0",
 485                 .enable         = exynos4_clk_ip_cam_ctrl,
 486                 .ctrlbit        = (1 << 0),
 487         }, {
 488                 .name           = "fimc",
 489                 .devname        = "exynos4-fimc.1",
 490                 .enable         = exynos4_clk_ip_cam_ctrl,
 491                 .ctrlbit        = (1 << 1),
 492         }, {
 493                 .name           = "fimc",
 494                 .devname        = "exynos4-fimc.2",
 495                 .enable         = exynos4_clk_ip_cam_ctrl,
 496                 .ctrlbit        = (1 << 2),
 497         }, {
 498                 .name           = "fimc",
 499                 .devname        = "exynos4-fimc.3",
 500                 .enable         = exynos4_clk_ip_cam_ctrl,
 501                 .ctrlbit        = (1 << 3),
 502         }, {
 503                 .name           = "tsi",
 504                 .enable         = exynos4_clk_ip_fsys_ctrl,
 505                 .ctrlbit        = (1 << 4),
 506         }, {
 507                 .name           = "hsmmc",
 508                 .devname        = "exynos4-sdhci.0",
 509                 .parent         = &exynos4_clk_aclk_133.clk,
 510                 .enable         = exynos4_clk_ip_fsys_ctrl,
 511                 .ctrlbit        = (1 << 5),
 512         }, {
 513                 .name           = "hsmmc",
 514                 .devname        = "exynos4-sdhci.1",
 515                 .parent         = &exynos4_clk_aclk_133.clk,
 516                 .enable         = exynos4_clk_ip_fsys_ctrl,
 517                 .ctrlbit        = (1 << 6),
 518         }, {
 519                 .name           = "hsmmc",
 520                 .devname        = "exynos4-sdhci.2",
 521                 .parent         = &exynos4_clk_aclk_133.clk,
 522                 .enable         = exynos4_clk_ip_fsys_ctrl,
 523                 .ctrlbit        = (1 << 7),
 524         }, {
 525                 .name           = "hsmmc",
 526                 .devname        = "exynos4-sdhci.3",
 527                 .parent         = &exynos4_clk_aclk_133.clk,
 528                 .enable         = exynos4_clk_ip_fsys_ctrl,
 529                 .ctrlbit        = (1 << 8),
 530         }, {
 531                 .name           = "biu",
 532                 .parent         = &exynos4_clk_aclk_133.clk,
 533                 .enable         = exynos4_clk_ip_fsys_ctrl,
 534                 .ctrlbit        = (1 << 9),
 535         }, {
 536                 .name           = "onenand",
 537                 .enable         = exynos4_clk_ip_fsys_ctrl,
 538                 .ctrlbit        = (1 << 15),
 539         }, {
 540                 .name           = "nfcon",
 541                 .enable         = exynos4_clk_ip_fsys_ctrl,
 542                 .ctrlbit        = (1 << 16),
 543         }, {
 544                 .name           = "dac",
 545                 .devname        = "s5p-sdo",
 546                 .enable         = exynos4_clk_ip_tv_ctrl,
 547                 .ctrlbit        = (1 << 2),
 548         }, {
 549                 .name           = "mixer",
 550                 .devname        = "s5p-mixer",
 551                 .enable         = exynos4_clk_ip_tv_ctrl,
 552                 .ctrlbit        = (1 << 1),
 553         }, {
 554                 .name           = "vp",
 555                 .devname        = "s5p-mixer",
 556                 .enable         = exynos4_clk_ip_tv_ctrl,
 557                 .ctrlbit        = (1 << 0),
 558         }, {
 559                 .name           = "hdmi",
 560                 .devname        = "exynos4-hdmi",
 561                 .enable         = exynos4_clk_ip_tv_ctrl,
 562                 .ctrlbit        = (1 << 3),
 563         }, {
 564                 .name           = "hdmiphy",
 565                 .devname        = "exynos4-hdmi",
 566                 .enable         = exynos4_clk_hdmiphy_ctrl,
 567                 .ctrlbit        = (1 << 0),
 568         }, {
 569                 .name           = "dacphy",
 570                 .devname        = "s5p-sdo",
 571                 .enable         = exynos4_clk_dac_ctrl,
 572                 .ctrlbit        = (1 << 0),
 573         }, {
 574                 .name           = "adc",
 575                 .enable         = exynos4_clk_ip_peril_ctrl,
 576                 .ctrlbit        = (1 << 15),
 577         }, {
 578                 .name           = "tmu_apbif",
 579                 .enable         = exynos4_clk_ip_perir_ctrl,
 580                 .ctrlbit        = (1 << 17),
 581         }, {
 582                 .name           = "keypad",
 583                 .enable         = exynos4_clk_ip_perir_ctrl,
 584                 .ctrlbit        = (1 << 16),
 585         }, {
 586                 .name           = "rtc",
 587                 .enable         = exynos4_clk_ip_perir_ctrl,
 588                 .ctrlbit        = (1 << 15),
 589         }, {
 590                 .name           = "watchdog",
 591                 .parent         = &exynos4_clk_aclk_100.clk,
 592                 .enable         = exynos4_clk_ip_perir_ctrl,
 593                 .ctrlbit        = (1 << 14),
 594         }, {
 595                 .name           = "usbhost",
 596                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 597                 .ctrlbit        = (1 << 12),
 598         }, {
 599                 .name           = "otg",
 600                 .enable         = exynos4_clk_ip_fsys_ctrl,
 601                 .ctrlbit        = (1 << 13),
 602         }, {
 603                 .name           = "spi",
 604                 .devname        = "exynos4210-spi.0",
 605                 .enable         = exynos4_clk_ip_peril_ctrl,
 606                 .ctrlbit        = (1 << 16),
 607         }, {
 608                 .name           = "spi",
 609                 .devname        = "exynos4210-spi.1",
 610                 .enable         = exynos4_clk_ip_peril_ctrl,
 611                 .ctrlbit        = (1 << 17),
 612         }, {
 613                 .name           = "spi",
 614                 .devname        = "exynos4210-spi.2",
 615                 .enable         = exynos4_clk_ip_peril_ctrl,
 616                 .ctrlbit        = (1 << 18),
 617         }, {
 618                 .name           = "iis",
 619                 .devname        = "samsung-i2s.1",
 620                 .enable         = exynos4_clk_ip_peril_ctrl,
 621                 .ctrlbit        = (1 << 20),
 622         }, {
 623                 .name           = "iis",
 624                 .devname        = "samsung-i2s.2",
 625                 .enable         = exynos4_clk_ip_peril_ctrl,
 626                 .ctrlbit        = (1 << 21),
 627         }, {
 628                 .name           = "pcm",
 629                 .devname        = "samsung-pcm.1",
 630                 .enable         = exynos4_clk_ip_peril_ctrl,
 631                 .ctrlbit        = (1 << 22),
 632         }, {
 633                 .name           = "pcm",
 634                 .devname        = "samsung-pcm.2",
 635                 .enable         = exynos4_clk_ip_peril_ctrl,
 636                 .ctrlbit        = (1 << 23),
 637         }, {
 638                 .name           = "slimbus",
 639                 .enable         = exynos4_clk_ip_peril_ctrl,
 640                 .ctrlbit        = (1 << 25),
 641         }, {
 642                 .name           = "spdif",
 643                 .devname        = "samsung-spdif",
 644                 .enable         = exynos4_clk_ip_peril_ctrl,
 645                 .ctrlbit        = (1 << 26),
 646         }, {
 647                 .name           = "ac97",
 648                 .devname        = "samsung-ac97",
 649                 .enable         = exynos4_clk_ip_peril_ctrl,
 650                 .ctrlbit        = (1 << 27),
 651         }, {
 652                 .name           = "mfc",
 653                 .devname        = "s5p-mfc",
 654                 .enable         = exynos4_clk_ip_mfc_ctrl,
 655                 .ctrlbit        = (1 << 0),
 656         }, {
 657                 .name           = "i2c",
 658                 .devname        = "s3c2440-i2c.0",
 659                 .parent         = &exynos4_clk_aclk_100.clk,
 660                 .enable         = exynos4_clk_ip_peril_ctrl,
 661                 .ctrlbit        = (1 << 6),
 662         }, {
 663                 .name           = "i2c",
 664                 .devname        = "s3c2440-i2c.1",
 665                 .parent         = &exynos4_clk_aclk_100.clk,
 666                 .enable         = exynos4_clk_ip_peril_ctrl,
 667                 .ctrlbit        = (1 << 7),
 668         }, {
 669                 .name           = "i2c",
 670                 .devname        = "s3c2440-i2c.2",
 671                 .parent         = &exynos4_clk_aclk_100.clk,
 672                 .enable         = exynos4_clk_ip_peril_ctrl,
 673                 .ctrlbit        = (1 << 8),
 674         }, {
 675                 .name           = "i2c",
 676                 .devname        = "s3c2440-i2c.3",
 677                 .parent         = &exynos4_clk_aclk_100.clk,
 678                 .enable         = exynos4_clk_ip_peril_ctrl,
 679                 .ctrlbit        = (1 << 9),
 680         }, {
 681                 .name           = "i2c",
 682                 .devname        = "s3c2440-i2c.4",
 683                 .parent         = &exynos4_clk_aclk_100.clk,
 684                 .enable         = exynos4_clk_ip_peril_ctrl,
 685                 .ctrlbit        = (1 << 10),
 686         }, {
 687                 .name           = "i2c",
 688                 .devname        = "s3c2440-i2c.5",
 689                 .parent         = &exynos4_clk_aclk_100.clk,
 690                 .enable         = exynos4_clk_ip_peril_ctrl,
 691                 .ctrlbit        = (1 << 11),
 692         }, {
 693                 .name           = "i2c",
 694                 .devname        = "s3c2440-i2c.6",
 695                 .parent         = &exynos4_clk_aclk_100.clk,
 696                 .enable         = exynos4_clk_ip_peril_ctrl,
 697                 .ctrlbit        = (1 << 12),
 698         }, {
 699                 .name           = "i2c",
 700                 .devname        = "s3c2440-i2c.7",
 701                 .parent         = &exynos4_clk_aclk_100.clk,
 702                 .enable         = exynos4_clk_ip_peril_ctrl,
 703                 .ctrlbit        = (1 << 13),
 704         }, {
 705                 .name           = "i2c",
 706                 .devname        = "s3c2440-hdmiphy-i2c",
 707                 .parent         = &exynos4_clk_aclk_100.clk,
 708                 .enable         = exynos4_clk_ip_peril_ctrl,
 709                 .ctrlbit        = (1 << 14),
 710         }, {
 711                 .name           = "sysmmu",
 712                 .devname        = "exynos-sysmmu.0",
 713                 .enable         = exynos4_clk_ip_mfc_ctrl,
 714                 .ctrlbit        = (1 << 1),
 715         }, {
 716                 .name           = "sysmmu",
 717                 .devname        = "exynos-sysmmu.1",
 718                 .enable         = exynos4_clk_ip_mfc_ctrl,
 719                 .ctrlbit        = (1 << 2),
 720         }, {
 721                 .name           = "sysmmu",
 722                 .devname        = "exynos-sysmmu.2",
 723                 .enable         = exynos4_clk_ip_tv_ctrl,
 724                 .ctrlbit        = (1 << 4),
 725         }, {
 726                 .name           = "sysmmu",
 727                 .devname        = "exynos-sysmmu.3",
 728                 .enable         = exynos4_clk_ip_cam_ctrl,
 729                 .ctrlbit        = (1 << 11),
 730         }, {
 731                 .name           = "sysmmu",
 732                 .devname        = "exynos-sysmmu.4",
 733                 .enable         = exynos4_clk_ip_image_ctrl,
 734                 .ctrlbit        = (1 << 4),
 735         }, {
 736                 .name           = "sysmmu",
 737                 .devname        = "exynos-sysmmu.5",
 738                 .enable         = exynos4_clk_ip_cam_ctrl,
 739                 .ctrlbit        = (1 << 7),
 740         }, {
 741                 .name           = "sysmmu",
 742                 .devname        = "exynos-sysmmu.6",
 743                 .enable         = exynos4_clk_ip_cam_ctrl,
 744                 .ctrlbit        = (1 << 8),
 745         }, {
 746                 .name           = "sysmmu",
 747                 .devname        = "exynos-sysmmu.7",
 748                 .enable         = exynos4_clk_ip_cam_ctrl,
 749                 .ctrlbit        = (1 << 9),
 750         }, {
 751                 .name           = "sysmmu",
 752                 .devname        = "exynos-sysmmu.8",
 753                 .enable         = exynos4_clk_ip_cam_ctrl,
 754                 .ctrlbit        = (1 << 10),
 755         }, {
 756                 .name           = "sysmmu",
 757                 .devname        = "exynos-sysmmu.10",
 758                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 759                 .ctrlbit        = (1 << 4),
 760         }
 761 };
 762
 763 static struct clk exynos4_init_clocks_on[] = {
 764         {
 765                 .name           = "uart",
 766                 .devname        = "s5pv210-uart.0",
 767                 .enable         = exynos4_clk_ip_peril_ctrl,
 768                 .ctrlbit        = (1 << 0),
 769         }, {
 770                 .name           = "uart",
 771                 .devname        = "s5pv210-uart.1",
 772                 .enable         = exynos4_clk_ip_peril_ctrl,
 773                 .ctrlbit        = (1 << 1),
 774         }, {
 775                 .name           = "uart",
 776                 .devname        = "s5pv210-uart.2",
 777                 .enable         = exynos4_clk_ip_peril_ctrl,
 778                 .ctrlbit        = (1 << 2),
 779         }, {
 780                 .name           = "uart",
 781                 .devname        = "s5pv210-uart.3",
 782                 .enable         = exynos4_clk_ip_peril_ctrl,
 783                 .ctrlbit        = (1 << 3),
 784         }, {
 785                 .name           = "uart",
 786                 .devname        = "s5pv210-uart.4",
 787                 .enable         = exynos4_clk_ip_peril_ctrl,
 788                 .ctrlbit        = (1 << 4),
 789         }, {
 790                 .name           = "uart",
 791                 .devname        = "s5pv210-uart.5",
 792                 .enable         = exynos4_clk_ip_peril_ctrl,
 793                 .ctrlbit        = (1 << 5),
 794         }
 795 };
 796
 797 static struct clk exynos4_clk_pdma0 = {
 798         .name           = "dma",
 799         .devname        = "dma-pl330.0",
 800         .enable         = exynos4_clk_ip_fsys_ctrl,
 801         .ctrlbit        = (1 << 0),
 802 };
 803
 804 static struct clk exynos4_clk_pdma1 = {
 805         .name           = "dma",
 806         .devname        = "dma-pl330.1",
 807         .enable         = exynos4_clk_ip_fsys_ctrl,
 808         .ctrlbit        = (1 << 1),
 809 };
 810
 811 static struct clk exynos4_clk_mdma1 = {
 812         .name           = "dma",
 813         .devname        = "dma-pl330.2",
 814         .enable         = exynos4_clk_ip_image_ctrl,
 815         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
 816 };
 817
 818 static struct clk exynos4_clk_fimd0 = {
 819         .name           = "fimd",
 820         .devname        = "exynos4-fb.0",
 821         .enable         = exynos4_clk_ip_lcd0_ctrl,
 822         .ctrlbit        = (1 << 0),
 823 };
 824
 825 struct clk *exynos4_clkset_group_list[] = {
 826         [0] = &clk_ext_xtal_mux,
 827         [1] = &clk_xusbxti,
 828         [2] = &exynos4_clk_sclk_hdmi27m,
 829         [3] = &exynos4_clk_sclk_usbphy0,
 830         [4] = &exynos4_clk_sclk_usbphy1,
 831         [5] = &exynos4_clk_sclk_hdmiphy,
 832         [6] = &exynos4_clk_mout_mpll.clk,
 833         [7] = &exynos4_clk_mout_epll.clk,
 834         [8] = &exynos4_clk_sclk_vpll.clk,
 835 };
 836
 837 struct clksrc_sources exynos4_clkset_group = {
 838         .sources        = exynos4_clkset_group_list,
 839         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
 840 };
 841
 842 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
 843         [0] = &exynos4_clk_mout_mpll.clk,
 844         [1] = &exynos4_clk_sclk_apll.clk,
 845 };
 846
 847 struct clksrc_sources exynos4_clkset_mout_g2d0 = {
 848         .sources        = exynos4_clkset_mout_g2d0_list,
 849         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 850 };
 851
 852 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
 853         [0] = &exynos4_clk_mout_epll.clk,
 854         [1] = &exynos4_clk_sclk_vpll.clk,
 855 };
 856
 857 struct clksrc_sources exynos4_clkset_mout_g2d1 = {
 858         .sources        = exynos4_clkset_mout_g2d1_list,
 859         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 860 };
 861
 862 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
 863         [0] = &exynos4_clk_mout_mpll.clk,
 864         [1] = &exynos4_clk_sclk_apll.clk,
 865 };
 866
 867 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
 868         .sources        = exynos4_clkset_mout_mfc0_list,
 869         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 870 };
 871
 872 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 873         .clk    = {
 874                 .name           = "mout_mfc0",
 875         },
 876         .sources = &exynos4_clkset_mout_mfc0,
 877         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 878 };
 879
 880 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
 881         [0] = &exynos4_clk_mout_epll.clk,
 882         [1] = &exynos4_clk_sclk_vpll.clk,
 883 };
 884
 885 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
 886         .sources        = exynos4_clkset_mout_mfc1_list,
 887         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 888 };
 889
 890 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 891         .clk    = {
 892                 .name           = "mout_mfc1",
 893         },
 894         .sources = &exynos4_clkset_mout_mfc1,
 895         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 896 };
 897
 898 static struct clk *exynos4_clkset_mout_mfc_list[] = {
 899         [0] = &exynos4_clk_mout_mfc0.clk,
 900         [1] = &exynos4_clk_mout_mfc1.clk,
 901 };
 902
 903 static struct clksrc_sources exynos4_clkset_mout_mfc = {
 904         .sources        = exynos4_clkset_mout_mfc_list,
 905         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 906 };
 907
 908 static struct clk *exynos4_clkset_sclk_dac_list[] = {
 909         [0] = &exynos4_clk_sclk_vpll.clk,
 910         [1] = &exynos4_clk_sclk_hdmiphy,
 911 };
 912
 913 static struct clksrc_sources exynos4_clkset_sclk_dac = {
 914         .sources        = exynos4_clkset_sclk_dac_list,
 915         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 916 };
 917
 918 static struct clksrc_clk exynos4_clk_sclk_dac = {
 919         .clk            = {
 920                 .name           = "sclk_dac",
 921                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 922                 .ctrlbit        = (1 << 8),
 923         },
 924         .sources = &exynos4_clkset_sclk_dac,
 925         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 926 };
 927
 928 static struct clksrc_clk exynos4_clk_sclk_pixel = {
 929         .clk            = {
 930                 .name           = "sclk_pixel",
 931                 .parent         = &exynos4_clk_sclk_vpll.clk,
 932         },
 933         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 934 };
 935
 936 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
 937         [0] = &exynos4_clk_sclk_pixel.clk,
 938         [1] = &exynos4_clk_sclk_hdmiphy,
 939 };
 940
 941 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
 942         .sources        = exynos4_clkset_sclk_hdmi_list,
 943         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 944 };
 945
 946 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 947         .clk            = {
 948                 .name           = "sclk_hdmi",
 949                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 950                 .ctrlbit        = (1 << 0),
 951         },
 952         .sources = &exynos4_clkset_sclk_hdmi,
 953         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 954 };
 955
 956 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
 957         [0] = &exynos4_clk_sclk_dac.clk,
 958         [1] = &exynos4_clk_sclk_hdmi.clk,
 959 };
 960
 961 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
 962         .sources        = exynos4_clkset_sclk_mixer_list,
 963         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 964 };
 965
 966 static struct clksrc_clk exynos4_clk_sclk_mixer = {
 967         .clk    = {
 968                 .name           = "sclk_mixer",
 969                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 970                 .ctrlbit        = (1 << 4),
 971         },
 972         .sources = &exynos4_clkset_sclk_mixer,
 973         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 974 };
 975
 976 static struct clksrc_clk *exynos4_sclk_tv[] = {
 977         &exynos4_clk_sclk_dac,
 978         &exynos4_clk_sclk_pixel,
 979         &exynos4_clk_sclk_hdmi,
 980         &exynos4_clk_sclk_mixer,
 981 };
 982
 983 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 984         .clk    = {
 985                 .name           = "dout_mmc0",
 986         },
 987         .sources = &exynos4_clkset_group,
 988         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
 989         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 990 };
 991
 992 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
 993         .clk    = {
 994                 .name           = "dout_mmc1",
 995         },
 996         .sources = &exynos4_clkset_group,
 997         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
 998         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
 999 };
1000
1001 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1002         .clk    = {
1003                 .name           = "dout_mmc2",
1004         },
1005         .sources = &exynos4_clkset_group,
1006         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1007         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1008 };
1009
1010 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1011         .clk    = {
1012                 .name           = "dout_mmc3",
1013         },
1014         .sources = &exynos4_clkset_group,
1015         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1016         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1017 };
1018
1019 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1020         .clk            = {
1021                 .name           = "dout_mmc4",
1022         },
1023         .sources = &exynos4_clkset_group,
1024         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1025         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1026 };
1027
1028 static struct clksrc_clk exynos4_clksrcs[] = {
1029         {
1030                 .clk    = {
1031                         .name           = "sclk_pwm",
1032                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1033                         .ctrlbit        = (1 << 24),
1034                 },
1035                 .sources = &exynos4_clkset_group,
1036                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1037                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1038         }, {
1039                 .clk    = {
1040                         .name           = "sclk_csis",
1041                         .devname        = "s5p-mipi-csis.0",
1042                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1043                         .ctrlbit        = (1 << 24),
1044                 },
1045                 .sources = &exynos4_clkset_group,
1046                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1047                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1048         }, {
1049                 .clk    = {
1050                         .name           = "sclk_csis",
1051                         .devname        = "s5p-mipi-csis.1",
1052                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1053                         .ctrlbit        = (1 << 28),
1054                 },
1055                 .sources = &exynos4_clkset_group,
1056                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1057                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1058         }, {
1059                 .clk    = {
1060                         .name           = "sclk_cam0",
1061                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1062                         .ctrlbit        = (1 << 16),
1063                 },
1064                 .sources = &exynos4_clkset_group,
1065                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1066                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1067         }, {
1068                 .clk    = {
1069                         .name           = "sclk_cam1",
1070                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1071                         .ctrlbit        = (1 << 20),
1072                 },
1073                 .sources = &exynos4_clkset_group,
1074                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1075                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1076         }, {
1077                 .clk    = {
1078                         .name           = "sclk_fimc",
1079                         .devname        = "exynos4-fimc.0",
1080                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1081                         .ctrlbit        = (1 << 0),
1082                 },
1083                 .sources = &exynos4_clkset_group,
1084                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1085                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1086         }, {
1087                 .clk    = {
1088                         .name           = "sclk_fimc",
1089                         .devname        = "exynos4-fimc.1",
1090                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1091                         .ctrlbit        = (1 << 4),
1092                 },
1093                 .sources = &exynos4_clkset_group,
1094                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1095                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1096         }, {
1097                 .clk    = {
1098                         .name           = "sclk_fimc",
1099                         .devname        = "exynos4-fimc.2",
1100                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1101                         .ctrlbit        = (1 << 8),
1102                 },
1103                 .sources = &exynos4_clkset_group,
1104                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1105                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1106         }, {
1107                 .clk    = {
1108                         .name           = "sclk_fimc",
1109                         .devname        = "exynos4-fimc.3",
1110                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1111                         .ctrlbit        = (1 << 12),
1112                 },
1113                 .sources = &exynos4_clkset_group,
1114                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1115                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1116         }, {
1117                 .clk    = {
1118                         .name           = "sclk_fimd",
1119                         .devname        = "exynos4-fb.0",
1120                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1121                         .ctrlbit        = (1 << 0),
1122                 },
1123                 .sources = &exynos4_clkset_group,
1124                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1125                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1126         }, {
1127                 .clk    = {
1128                         .name           = "sclk_mfc",
1129                         .devname        = "s5p-mfc",
1130                 },
1131                 .sources = &exynos4_clkset_mout_mfc,
1132                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1133                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1134         }, {
1135                 .clk    = {
1136                         .name           = "ciu",
1137                         .parent         = &exynos4_clk_dout_mmc4.clk,
1138                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1139                         .ctrlbit        = (1 << 16),
1140                 },
1141                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1142         }
1143 };
1144
1145 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1146         .clk    = {
1147                 .name           = "uclk1",
1148                 .devname        = "exynos4210-uart.0",
1149                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1150                 .ctrlbit        = (1 << 0),
1151         },
1152         .sources = &exynos4_clkset_group,
1153         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1154         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1155 };
1156
1157 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1158         .clk    = {
1159                 .name           = "uclk1",
1160                 .devname        = "exynos4210-uart.1",
1161                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1162                 .ctrlbit        = (1 << 4),
1163         },
1164         .sources = &exynos4_clkset_group,
1165         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1166         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1167 };
1168
1169 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1170         .clk    = {
1171                 .name           = "uclk1",
1172                 .devname        = "exynos4210-uart.2",
1173                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1174                 .ctrlbit        = (1 << 8),
1175         },
1176         .sources = &exynos4_clkset_group,
1177         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1178         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1179 };
1180
1181 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1182         .clk    = {
1183                 .name           = "uclk1",
1184                 .devname        = "exynos4210-uart.3",
1185                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1186                 .ctrlbit        = (1 << 12),
1187         },
1188         .sources = &exynos4_clkset_group,
1189         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1190         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1191 };
1192
1193 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1194         .clk    = {
1195                 .name           = "sclk_mmc",
1196                 .devname        = "exynos4-sdhci.0",
1197                 .parent         = &exynos4_clk_dout_mmc0.clk,
1198                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1199                 .ctrlbit        = (1 << 0),
1200         },
1201         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1202 };
1203
1204 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1205         .clk    = {
1206                 .name           = "sclk_mmc",
1207                 .devname        = "exynos4-sdhci.1",
1208                 .parent         = &exynos4_clk_dout_mmc1.clk,
1209                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1210                 .ctrlbit        = (1 << 4),
1211         },
1212         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1213 };
1214
1215 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1216         .clk    = {
1217                 .name           = "sclk_mmc",
1218                 .devname        = "exynos4-sdhci.2",
1219                 .parent         = &exynos4_clk_dout_mmc2.clk,
1220                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1221                 .ctrlbit        = (1 << 8),
1222         },
1223         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1224 };
1225
1226 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1227         .clk    = {
1228                 .name           = "sclk_mmc",
1229                 .devname        = "exynos4-sdhci.3",
1230                 .parent         = &exynos4_clk_dout_mmc3.clk,
1231                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1232                 .ctrlbit        = (1 << 12),
1233         },
1234         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1235 };
1236
1237 static struct clksrc_clk exynos4_clk_mdout_spi0 = {
1238         .clk    = {
1239                 .name           = "mdout_spi",
1240                 .devname        = "exynos4210-spi.0",
1241         },
1242         .sources = &exynos4_clkset_group,
1243         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1244         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1245 };
1246
1247 static struct clksrc_clk exynos4_clk_mdout_spi1 = {
1248         .clk    = {
1249                 .name           = "mdout_spi",
1250                 .devname        = "exynos4210-spi.1",
1251         },
1252         .sources = &exynos4_clkset_group,
1253         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1254         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1255 };
1256
1257 static struct clksrc_clk exynos4_clk_mdout_spi2 = {
1258         .clk    = {
1259                 .name           = "mdout_spi",
1260                 .devname        = "exynos4210-spi.2",
1261         },
1262         .sources = &exynos4_clkset_group,
1263         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1265 };
1266
1267 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1268         .clk    = {
1269                 .name           = "sclk_spi",
1270                 .devname        = "exynos4210-spi.0",
1271                 .parent         = &exynos4_clk_mdout_spi0.clk,
1272                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1273                 .ctrlbit        = (1 << 16),
1274         },
1275         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
1276 };
1277
1278 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1279         .clk    = {
1280                 .name           = "sclk_spi",
1281                 .devname        = "exynos4210-spi.1",
1282                 .parent         = &exynos4_clk_mdout_spi1.clk,
1283                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1284                 .ctrlbit        = (1 << 20),
1285         },
1286         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
1287 };
1288
1289 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1290         .clk    = {
1291                 .name           = "sclk_spi",
1292                 .devname        = "exynos4210-spi.2",
1293                 .parent         = &exynos4_clk_mdout_spi2.clk,
1294                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1295                 .ctrlbit        = (1 << 24),
1296         },
1297         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
1298 };
1299
1300 /* Clock initialization code */
1301 static struct clksrc_clk *exynos4_sysclks[] = {
1302         &exynos4_clk_mout_apll,
1303         &exynos4_clk_sclk_apll,
1304         &exynos4_clk_mout_epll,
1305         &exynos4_clk_mout_mpll,
1306         &exynos4_clk_moutcore,
1307         &exynos4_clk_coreclk,
1308         &exynos4_clk_armclk,
1309         &exynos4_clk_aclk_corem0,
1310         &exynos4_clk_aclk_cores,
1311         &exynos4_clk_aclk_corem1,
1312         &exynos4_clk_periphclk,
1313         &exynos4_clk_mout_corebus,
1314         &exynos4_clk_sclk_dmc,
1315         &exynos4_clk_aclk_cored,
1316         &exynos4_clk_aclk_corep,
1317         &exynos4_clk_aclk_acp,
1318         &exynos4_clk_pclk_acp,
1319         &exynos4_clk_vpllsrc,
1320         &exynos4_clk_sclk_vpll,
1321         &exynos4_clk_aclk_200,
1322         &exynos4_clk_aclk_100,
1323         &exynos4_clk_aclk_160,
1324         &exynos4_clk_aclk_133,
1325         &exynos4_clk_dout_mmc0,
1326         &exynos4_clk_dout_mmc1,
1327         &exynos4_clk_dout_mmc2,
1328         &exynos4_clk_dout_mmc3,
1329         &exynos4_clk_dout_mmc4,
1330         &exynos4_clk_mout_mfc0,
1331         &exynos4_clk_mout_mfc1,
1332 };
1333
1334 static struct clk *exynos4_clk_cdev[] = {
1335         &exynos4_clk_pdma0,
1336         &exynos4_clk_pdma1,
1337         &exynos4_clk_mdma1,
1338         &exynos4_clk_fimd0,
1339 };
1340
1341 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1342         &exynos4_clk_sclk_uart0,
1343         &exynos4_clk_sclk_uart1,
1344         &exynos4_clk_sclk_uart2,
1345         &exynos4_clk_sclk_uart3,
1346         &exynos4_clk_sclk_mmc0,
1347         &exynos4_clk_sclk_mmc1,
1348         &exynos4_clk_sclk_mmc2,
1349         &exynos4_clk_sclk_mmc3,
1350         &exynos4_clk_sclk_spi0,
1351         &exynos4_clk_sclk_spi1,
1352         &exynos4_clk_sclk_spi2,
1353         &exynos4_clk_mdout_spi0,
1354         &exynos4_clk_mdout_spi1,
1355         &exynos4_clk_mdout_spi2,
1356 };
1357
1358 static struct clk_lookup exynos4_clk_lookup[] = {
1359         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1360         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1361         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1362         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1363         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1364         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1365         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1366         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1367         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1368         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1369         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1370         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1371         CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1372         CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1373         CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1374 };
1375
1376 static int xtal_rate;
1377
1378 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1379 {
1380         if (soc_is_exynos4210())
1381                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1382                                         pll_4508);
1383         else if (soc_is_exynos4212() || soc_is_exynos4412())
1384                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1385         else
1386                 return 0;
1387 }
1388
1389 static struct clk_ops exynos4_fout_apll_ops = {
1390         .get_rate = exynos4_fout_apll_get_rate,
1391 };
1392
1393 static u32 exynos4_vpll_div[][8] = {
1394         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1395         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1396 };
1397
1398 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1399 {
1400         return clk->rate;
1401 }
1402
1403 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1404 {
1405         unsigned int vpll_con0, vpll_con1 = 0;
1406         unsigned int i;
1407
1408         /* Return if nothing changed */
1409         if (clk->rate == rate)
1410                 return 0;
1411
1412         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1413         vpll_con0 &= ~(0x1 << 27 |                                      \
1414                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1415                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1416                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1417
1418         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1419         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1420                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1421                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1422
1423         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1424                 if (exynos4_vpll_div[i][0] == rate) {
1425                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1426                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1427                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1428                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1429                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1430                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1431                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1432                         break;
1433                 }
1434         }
1435
1436         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1437                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1438                                 __func__);
1439                 return -EINVAL;
1440         }
1441
1442         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1443         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1444
1445         /* Wait for VPLL lock */
1446         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1447                 continue;
1448
1449         clk->rate = rate;
1450         return 0;
1451 }
1452
1453 static struct clk_ops exynos4_vpll_ops = {
1454         .get_rate = exynos4_vpll_get_rate,
1455         .set_rate = exynos4_vpll_set_rate,
1456 };
1457
1458 void __init_or_cpufreq exynos4_setup_clocks(void)
1459 {
1460         struct clk *xtal_clk;
1461         unsigned long apll = 0;
1462         unsigned long mpll = 0;
1463         unsigned long epll = 0;
1464         unsigned long vpll = 0;
1465         unsigned long vpllsrc;
1466         unsigned long xtal;
1467         unsigned long armclk;
1468         unsigned long sclk_dmc;
1469         unsigned long aclk_200;
1470         unsigned long aclk_100;
1471         unsigned long aclk_160;
1472         unsigned long aclk_133;
1473         unsigned int ptr;
1474
1475         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1476
1477         xtal_clk = clk_get(NULL, "xtal");
1478         BUG_ON(IS_ERR(xtal_clk));
1479
1480         xtal = clk_get_rate(xtal_clk);
1481
1482         xtal_rate = xtal;
1483
1484         clk_put(xtal_clk);
1485
1486         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1487
1488         if (soc_is_exynos4210()) {
1489                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1490                                         pll_4508);
1491                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1492                                         pll_4508);
1493                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1494                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1495
1496                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1497                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1498                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1499         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1500                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1501                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1502                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1503                                         __raw_readl(EXYNOS4_EPLL_CON1));
1504
1505                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1506                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1507                                         __raw_readl(EXYNOS4_VPLL_CON1));
1508         } else {
1509                 /* nothing */
1510         }
1511
1512         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1513         clk_fout_mpll.rate = mpll;
1514         clk_fout_epll.rate = epll;
1515         clk_fout_vpll.ops = &exynos4_vpll_ops;
1516         clk_fout_vpll.rate = vpll;
1517
1518         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1519                         apll, mpll, epll, vpll);
1520
1521         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1522         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1523
1524         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1525         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1526         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1527         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1528
1529         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1530                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1531                         armclk, sclk_dmc, aclk_200,
1532                         aclk_100, aclk_160, aclk_133);
1533
1534         clk_f.rate = armclk;
1535         clk_h.rate = sclk_dmc;
1536         clk_p.rate = aclk_100;
1537
1538         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1539                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1540 }
1541
1542 static struct clk *exynos4_clks[] __initdata = {
1543         &exynos4_clk_sclk_hdmi27m,
1544         &exynos4_clk_sclk_hdmiphy,
1545         &exynos4_clk_sclk_usbphy0,
1546         &exynos4_clk_sclk_usbphy1,
1547 };
1548
1549 #ifdef CONFIG_PM_SLEEP
1550 static int exynos4_clock_suspend(void)
1551 {
1552         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1553         return 0;
1554 }
1555
1556 static void exynos4_clock_resume(void)
1557 {
1558         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1559 }
1560
1561 #else
1562 #define exynos4_clock_suspend NULL
1563 #define exynos4_clock_resume NULL
1564 #endif
1565
1566 static struct syscore_ops exynos4_clock_syscore_ops = {
1567         .suspend        = exynos4_clock_suspend,
1568         .resume         = exynos4_clock_resume,
1569 };
1570
1571 void __init exynos4_register_clocks(void)
1572 {
1573         int ptr;
1574
1575         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1576
1577         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1578                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1579
1580         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1581                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1582
1583         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1584                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1585
1586         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1587         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1588
1589         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1590         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1591                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1592
1593         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1594         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1595         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1596
1597         register_syscore_ops(&exynos4_clock_syscore_ops);
1598         s3c24xx_register_clock(&dummy_apb_pclk);
1599
1600         s3c_pwmclk_init();
1601 }