2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS - Power Management support
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
21 #include <linux/irqchip/arm-gic.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
25 #include <asm/cacheflush.h>
26 #include <asm/hardware/cache-l2x0.h>
27 #include <asm/smp_scu.h>
28 #include <asm/suspend.h>
30 #include <plat/pm-common.h>
32 #include <plat/regs-srom.h>
41 * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
42 * @hwirq: Hardware IRQ signal of the GIC
43 * @mask: Mask in PMU wake-up mask register
45 struct exynos_wkup_irq {
50 static struct sleep_save exynos5_sys_save[] = {
51 SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
54 static struct sleep_save exynos_core_save[] = {
56 SAVE_ITEM(S5P_SROM_BW),
57 SAVE_ITEM(S5P_SROM_BC0),
58 SAVE_ITEM(S5P_SROM_BC1),
59 SAVE_ITEM(S5P_SROM_BC2),
60 SAVE_ITEM(S5P_SROM_BC3),
67 static u32 exynos_irqwake_intmask = 0xffffffff;
69 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
70 { 76, BIT(1) }, /* RTC alarm */
71 { 77, BIT(2) }, /* RTC tick */
75 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
76 { 75, BIT(1) }, /* RTC alarm */
77 { 76, BIT(2) }, /* RTC tick */
81 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
83 const struct exynos_wkup_irq *wkup_irq;
85 if (soc_is_exynos5250())
86 wkup_irq = exynos5250_wkup_irq;
88 wkup_irq = exynos4_wkup_irq;
90 while (wkup_irq->mask) {
91 if (wkup_irq->hwirq == data->hwirq) {
93 exynos_irqwake_intmask |= wkup_irq->mask;
95 exynos_irqwake_intmask &= ~wkup_irq->mask;
104 #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
105 S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
106 (sysram_base_addr + 0x24) : S5P_INFORM0))
107 #define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
108 S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
109 (sysram_base_addr + 0x20) : S5P_INFORM1))
111 #define S5P_CHECK_AFTR 0xFCBA0D10
112 #define S5P_CHECK_SLEEP 0x00000BAD
114 /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
115 static void exynos_set_wakeupmask(long mask)
117 __raw_writel(mask, S5P_WAKEUP_MASK);
120 static void exynos_cpu_set_boot_vector(long flags)
122 __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
123 __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
126 void exynos_enter_aftr(void)
128 exynos_set_wakeupmask(0x0000ff3e);
129 exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
130 /* Set value of power down register for aftr mode */
131 exynos_sys_powerdown_conf(SYS_AFTR);
134 /* For Cortex-A9 Diagnostic and Power control register */
135 static unsigned int save_arm_register[2];
137 static void exynos_cpu_save_register(void)
141 /* Save Power control register */
142 asm ("mrc p15, 0, %0, c15, c0, 0"
143 : "=r" (tmp) : : "cc");
145 save_arm_register[0] = tmp;
147 /* Save Diagnostic register */
148 asm ("mrc p15, 0, %0, c15, c0, 1"
149 : "=r" (tmp) : : "cc");
151 save_arm_register[1] = tmp;
154 static void exynos_cpu_restore_register(void)
158 /* Restore Power control register */
159 tmp = save_arm_register[0];
161 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
165 /* Restore Diagnostic register */
166 tmp = save_arm_register[1];
168 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
173 static int exynos_cpu_suspend(unsigned long arg)
175 #ifdef CONFIG_CACHE_L2X0
179 if (soc_is_exynos5250())
182 /* issue the standby signal into the pm unit. */
185 pr_info("Failed to suspend the system\n");
186 return 1; /* Aborting suspend */
189 static void exynos_pm_prepare(void)
193 /* Set wake-up mask registers */
194 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
195 __raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
197 s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
199 if (soc_is_exynos5250()) {
200 s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
201 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
202 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
203 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
204 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
207 /* Set value of power down register for sleep mode */
209 exynos_sys_powerdown_conf(SYS_SLEEP);
210 __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
212 /* ensure at least INFORM0 has the resume address */
214 __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
217 static void exynos_pm_central_suspend(void)
221 /* Setting Central Sequence Register for power down mode */
222 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
223 tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
224 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
227 static int exynos_pm_suspend(void)
231 exynos_pm_central_suspend();
233 /* Setting SEQ_OPTION register */
235 tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
236 __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
238 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
239 exynos_cpu_save_register();
244 static int exynos_pm_central_resume(void)
249 * If PMU failed while entering sleep mode, WFI will be
250 * ignored by PMU and then exiting cpu_do_idle().
251 * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
254 tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
255 if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
256 tmp |= S5P_CENTRAL_LOWPWR_CFG;
257 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
258 /* clear the wakeup state register */
259 __raw_writel(0x0, S5P_WAKEUP_STAT);
260 /* No need to perform below restore code */
267 static void exynos_pm_resume(void)
269 if (exynos_pm_central_resume())
272 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
273 exynos_cpu_restore_register();
275 /* For release retention */
277 __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
278 __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
279 __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
280 __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
281 __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
282 __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
283 __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
285 if (soc_is_exynos5250())
286 s3c_pm_do_restore(exynos5_sys_save,
287 ARRAY_SIZE(exynos5_sys_save));
289 s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
291 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
292 scu_enable(S5P_VA_SCU);
296 /* Clear SLEEP mode set in INFORM1 */
297 __raw_writel(0x0, S5P_INFORM1);
302 static struct syscore_ops exynos_pm_syscore_ops = {
303 .suspend = exynos_pm_suspend,
304 .resume = exynos_pm_resume,
311 static int exynos_suspend_enter(suspend_state_t state)
317 S3C_PMDBG("%s: suspending the system...\n", __func__);
319 S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
320 exynos_irqwake_intmask, exynos_get_eint_wake_mask());
322 if (exynos_irqwake_intmask == -1U
323 && exynos_get_eint_wake_mask() == -1U) {
324 pr_err("%s: No wake-up sources!\n", __func__);
325 pr_err("%s: Aborting sleep\n", __func__);
332 s3c_pm_check_store();
334 ret = cpu_suspend(0, exynos_cpu_suspend);
338 s3c_pm_restore_uarts();
340 S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
341 __raw_readl(S5P_WAKEUP_STAT));
343 s3c_pm_check_restore();
345 S3C_PMDBG("%s: resuming the system...\n", __func__);
350 static int exynos_suspend_prepare(void)
352 s3c_pm_check_prepare();
357 static void exynos_suspend_finish(void)
359 s3c_pm_check_cleanup();
362 static const struct platform_suspend_ops exynos_suspend_ops = {
363 .enter = exynos_suspend_enter,
364 .prepare = exynos_suspend_prepare,
365 .finish = exynos_suspend_finish,
366 .valid = suspend_valid_only_mem,
369 static int exynos_cpu_pm_notifier(struct notifier_block *self,
370 unsigned long cmd, void *v)
372 int cpu = smp_processor_id();
377 exynos_pm_central_suspend();
378 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
379 exynos_cpu_save_register();
385 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
386 scu_enable(S5P_VA_SCU);
387 exynos_cpu_restore_register();
389 exynos_pm_central_resume();
397 static struct notifier_block exynos_cpu_pm_notifier_block = {
398 .notifier_call = exynos_cpu_pm_notifier,
401 void __init exynos_pm_init(void)
405 cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
407 /* Platform-specific GIC callback */
408 gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
410 /* All wakeup disable */
411 tmp = __raw_readl(S5P_WAKEUP_MASK);
412 tmp |= ((0xFF << 8) | (0x1F << 1));
413 __raw_writel(tmp, S5P_WAKEUP_MASK);
415 register_syscore_ops(&exynos_pm_syscore_ops);
416 suspend_set_ops(&exynos_suspend_ops);