1 /* linux/arch/arm/mach-exynos4/mach-smdkc210.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/serial_core.h>
12 #include <linux/gpio.h>
13 #include <linux/mmc/host.h>
14 #include <linux/platform_device.h>
15 #include <linux/smsc911x.h>
17 #include <linux/i2c.h>
18 #include <linux/pwm_backlight.h>
20 #include <asm/mach/arch.h>
21 #include <asm/mach-types.h>
23 #include <plat/regs-serial.h>
24 #include <plat/regs-srom.h>
25 #include <plat/exynos4.h>
27 #include <plat/devs.h>
28 #include <plat/sdhci.h>
31 #include <plat/gpio-cfg.h>
32 #include <plat/backlight.h>
36 /* Following are default values for UCON, ULCON and UFCON UART registers */
37 #define SMDKC210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
38 S3C2410_UCON_RXILEVEL | \
39 S3C2410_UCON_TXIRQMODE | \
40 S3C2410_UCON_RXIRQMODE | \
41 S3C2410_UCON_RXFIFO_TOI | \
42 S3C2443_UCON_RXERR_IRQEN)
44 #define SMDKC210_ULCON_DEFAULT S3C2410_LCON_CS8
46 #define SMDKC210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
47 S5PV210_UFCON_TXTRIG4 | \
48 S5PV210_UFCON_RXTRIG4)
50 static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
54 .ucon = SMDKC210_UCON_DEFAULT,
55 .ulcon = SMDKC210_ULCON_DEFAULT,
56 .ufcon = SMDKC210_UFCON_DEFAULT,
61 .ucon = SMDKC210_UCON_DEFAULT,
62 .ulcon = SMDKC210_ULCON_DEFAULT,
63 .ufcon = SMDKC210_UFCON_DEFAULT,
68 .ucon = SMDKC210_UCON_DEFAULT,
69 .ulcon = SMDKC210_ULCON_DEFAULT,
70 .ufcon = SMDKC210_UFCON_DEFAULT,
75 .ucon = SMDKC210_UCON_DEFAULT,
76 .ulcon = SMDKC210_ULCON_DEFAULT,
77 .ufcon = SMDKC210_UFCON_DEFAULT,
81 static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
82 .cd_type = S3C_SDHCI_CD_GPIO,
83 .ext_cd_gpio = EXYNOS4_GPK0(2),
84 .ext_cd_gpio_invert = 1,
85 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
86 #ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
88 .host_caps = MMC_CAP_8_BIT_DATA,
92 static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
93 .cd_type = S3C_SDHCI_CD_GPIO,
94 .ext_cd_gpio = EXYNOS4_GPK0(2),
95 .ext_cd_gpio_invert = 1,
96 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
99 static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
100 .cd_type = S3C_SDHCI_CD_GPIO,
101 .ext_cd_gpio = EXYNOS4_GPK2(2),
102 .ext_cd_gpio_invert = 1,
103 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
104 #ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
106 .host_caps = MMC_CAP_8_BIT_DATA,
110 static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
111 .cd_type = S3C_SDHCI_CD_GPIO,
112 .ext_cd_gpio = EXYNOS4_GPK2(2),
113 .ext_cd_gpio_invert = 1,
114 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
117 static struct resource smdkc210_smsc911x_resources[] = {
119 .start = EXYNOS4_PA_SROM_BANK(1),
120 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
121 .flags = IORESOURCE_MEM,
124 .start = IRQ_EINT(5),
126 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
130 static struct smsc911x_platform_config smsc9215_config = {
131 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
132 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
133 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
134 .phy_interface = PHY_INTERFACE_MODE_MII,
135 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
138 static struct platform_device smdkc210_smsc911x = {
141 .num_resources = ARRAY_SIZE(smdkc210_smsc911x_resources),
142 .resource = smdkc210_smsc911x_resources,
144 .platform_data = &smsc9215_config,
148 static struct i2c_board_info i2c_devs1[] __initdata = {
149 {I2C_BOARD_INFO("wm8994", 0x1a),},
152 static struct platform_device *smdkc210_devices[] __initdata = {
160 &exynos4_device_ac97,
161 &exynos4_device_i2s0,
162 &exynos4_device_pd[PD_MFC],
163 &exynos4_device_pd[PD_G3D],
164 &exynos4_device_pd[PD_LCD0],
165 &exynos4_device_pd[PD_LCD1],
166 &exynos4_device_pd[PD_CAM],
167 &exynos4_device_pd[PD_TV],
168 &exynos4_device_pd[PD_GPS],
169 &exynos4_device_sysmmu,
174 static void __init smdkc210_smsc911x_init(void)
178 /* configure nCS1 width to 16 bits */
179 cs1 = __raw_readl(S5P_SROM_BW) &
180 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
181 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
182 (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
183 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
184 S5P_SROM_BW__NCS1__SHIFT;
185 __raw_writel(cs1, S5P_SROM_BW);
187 /* set timing for nCS1 suitable for ethernet chip */
188 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
189 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
190 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
191 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
192 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
193 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
194 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
197 /* LCD Backlight data */
198 static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
199 .no = EXYNOS4_GPD0(1),
200 .func = S3C_GPIO_SFN(2),
203 static struct platform_pwm_backlight_data smdkc210_bl_data = {
205 .pwm_period_ns = 1000,
208 static void __init smdkc210_map_io(void)
210 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
211 s3c24xx_init_clocks(24000000);
212 s3c24xx_init_uarts(smdkc210_uartcfgs, ARRAY_SIZE(smdkc210_uartcfgs));
215 static void __init smdkc210_machine_init(void)
217 s3c_i2c1_set_platdata(NULL);
218 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
220 smdkc210_smsc911x_init();
222 s3c_sdhci0_set_platdata(&smdkc210_hsmmc0_pdata);
223 s3c_sdhci1_set_platdata(&smdkc210_hsmmc1_pdata);
224 s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
225 s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
227 samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
229 platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
232 MACHINE_START(SMDKC210, "SMDKC210")
233 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
234 .boot_params = S5P_PA_SDRAM + 0x100,
235 .init_irq = exynos4_init_irq,
236 .map_io = smdkc210_map_io,
237 .init_machine = smdkc210_machine_init,
238 .timer = &exynos4_timer,