arch/arm/mach-imx/pm-imx6q.c

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/init.h>
  15 #include <linux/io.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/suspend.h>
  19 #include <asm/cacheflush.h>
  20 #include <asm/proc-fns.h>
  21 #include <asm/suspend.h>
  22 #include <asm/hardware/cache-l2x0.h>
  23
  24 #include "common.h"
  25 #include "hardware.h"
  26
  27 #define CCR                             0x0
  28 #define BM_CCR_WB_COUNT                 (0x7 << 16)
  29 #define BM_CCR_RBC_BYPASS_COUNT         (0x3f << 21)
  30 #define BM_CCR_RBC_EN                   (0x1 << 27)
  31
  32 #define CLPCR                           0x54
  33 #define BP_CLPCR_LPM                    0
  34 #define BM_CLPCR_LPM                    (0x3 << 0)
  35 #define BM_CLPCR_BYPASS_PMIC_READY      (0x1 << 2)
  36 #define BM_CLPCR_ARM_CLK_DIS_ON_LPM     (0x1 << 5)
  37 #define BM_CLPCR_SBYOS                  (0x1 << 6)
  38 #define BM_CLPCR_DIS_REF_OSC            (0x1 << 7)
  39 #define BM_CLPCR_VSTBY                  (0x1 << 8)
  40 #define BP_CLPCR_STBY_COUNT             9
  41 #define BM_CLPCR_STBY_COUNT             (0x3 << 9)
  42 #define BM_CLPCR_COSC_PWRDOWN           (0x1 << 11)
  43 #define BM_CLPCR_WB_PER_AT_LPM          (0x1 << 16)
  44 #define BM_CLPCR_WB_CORE_AT_LPM         (0x1 << 17)
  45 #define BM_CLPCR_BYP_MMDC_CH0_LPM_HS    (0x1 << 19)
  46 #define BM_CLPCR_BYP_MMDC_CH1_LPM_HS    (0x1 << 21)
  47 #define BM_CLPCR_MASK_CORE0_WFI         (0x1 << 22)
  48 #define BM_CLPCR_MASK_CORE1_WFI         (0x1 << 23)
  49 #define BM_CLPCR_MASK_CORE2_WFI         (0x1 << 24)
  50 #define BM_CLPCR_MASK_CORE3_WFI         (0x1 << 25)
  51 #define BM_CLPCR_MASK_SCU_IDLE          (0x1 << 26)
  52 #define BM_CLPCR_MASK_L2CC_IDLE         (0x1 << 27)
  53
  54 #define CGPR                            0x64
  55 #define BM_CGPR_CHICKEN_BIT             (0x1 << 17)
  56
  57 static void __iomem *ccm_base;
  58
  59 void imx6q_set_chicken_bit(void)
  60 {
  61         u32 val = readl_relaxed(ccm_base + CGPR);
  62
  63         val |= BM_CGPR_CHICKEN_BIT;
  64         writel_relaxed(val, ccm_base + CGPR);
  65 }
  66
  67 static void imx6q_enable_rbc(bool enable)
  68 {
  69         u32 val;
  70
  71         /*
  72          * need to mask all interrupts in GPC before
  73          * operating RBC configurations
  74          */
  75         imx_gpc_mask_all();
  76
  77         /* configure RBC enable bit */
  78         val = readl_relaxed(ccm_base + CCR);
  79         val &= ~BM_CCR_RBC_EN;
  80         val |= enable ? BM_CCR_RBC_EN : 0;
  81         writel_relaxed(val, ccm_base + CCR);
  82
  83         /* configure RBC count */
  84         val = readl_relaxed(ccm_base + CCR);
  85         val &= ~BM_CCR_RBC_BYPASS_COUNT;
  86         val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
  87         writel(val, ccm_base + CCR);
  88
  89         /*
  90          * need to delay at least 2 cycles of CKIL(32K)
  91          * due to hardware design requirement, which is
  92          * ~61us, here we use 65us for safe
  93          */
  94         udelay(65);
  95
  96         /* restore GPC interrupt mask settings */
  97         imx_gpc_restore_all();
  98 }
  99
 100 static void imx6q_enable_wb(bool enable)
 101 {
 102         u32 val;
 103
 104         /* configure well bias enable bit */
 105         val = readl_relaxed(ccm_base + CLPCR);
 106         val &= ~BM_CLPCR_WB_PER_AT_LPM;
 107         val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
 108         writel_relaxed(val, ccm_base + CLPCR);
 109
 110         /* configure well bias count */
 111         val = readl_relaxed(ccm_base + CCR);
 112         val &= ~BM_CCR_WB_COUNT;
 113         val |= enable ? BM_CCR_WB_COUNT : 0;
 114         writel_relaxed(val, ccm_base + CCR);
 115 }
 116
 117 int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
 118 {
 119         u32 val = readl_relaxed(ccm_base + CLPCR);
 120
 121         val &= ~BM_CLPCR_LPM;
 122         switch (mode) {
 123         case WAIT_CLOCKED:
 124                 break;
 125         case WAIT_UNCLOCKED:
 126                 val |= 0x1 << BP_CLPCR_LPM;
 127                 val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
 128                 break;
 129         case STOP_POWER_ON:
 130                 val |= 0x2 << BP_CLPCR_LPM;
 131                 break;
 132         case WAIT_UNCLOCKED_POWER_OFF:
 133                 val |= 0x1 << BP_CLPCR_LPM;
 134                 val &= ~BM_CLPCR_VSTBY;
 135                 val &= ~BM_CLPCR_SBYOS;
 136                 break;
 137         case STOP_POWER_OFF:
 138                 val |= 0x2 << BP_CLPCR_LPM;
 139                 val |= 0x3 << BP_CLPCR_STBY_COUNT;
 140                 val |= BM_CLPCR_VSTBY;
 141                 val |= BM_CLPCR_SBYOS;
 142                 break;
 143         default:
 144                 return -EINVAL;
 145         }
 146
 147         writel_relaxed(val, ccm_base + CLPCR);
 148
 149         return 0;
 150 }
 151
 152 static int imx6q_suspend_finish(unsigned long val)
 153 {
 154         cpu_do_idle();
 155         return 0;
 156 }
 157
 158 static int imx6q_pm_enter(suspend_state_t state)
 159 {
 160         switch (state) {
 161         case PM_SUSPEND_MEM:
 162                 imx6q_set_lpm(STOP_POWER_OFF);
 163                 imx6q_enable_wb(true);
 164                 imx6q_enable_rbc(true);
 165                 imx_gpc_pre_suspend();
 166                 imx_anatop_pre_suspend();
 167                 imx_set_cpu_jump(0, v7_cpu_resume);
 168                 /* Zzz ... */
 169                 cpu_suspend(0, imx6q_suspend_finish);
 170                 imx_smp_prepare();
 171                 imx_anatop_post_resume();
 172                 imx_gpc_post_resume();
 173                 imx6q_enable_rbc(false);
 174                 imx6q_enable_wb(false);
 175                 imx6q_set_lpm(WAIT_CLOCKED);
 176                 break;
 177         default:
 178                 return -EINVAL;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static const struct platform_suspend_ops imx6q_pm_ops = {
 185         .enter = imx6q_pm_enter,
 186         .valid = suspend_valid_only_mem,
 187 };
 188
 189 void __init imx6q_pm_set_ccm_base(void __iomem *base)
 190 {
 191         ccm_base = base;
 192 }
 193
 194 void __init imx6q_pm_init(void)
 195 {
 196         WARN_ON(!ccm_base);
 197
 198         /* Set initial power mode */
 199         imx6q_set_lpm(WAIT_CLOCKED);
 200
 201         suspend_set_ops(&imx6q_pm_ops);
 202 }