2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/init.h>
16 #include <linux/of_address.h>
17 #include <linux/smp.h>
18 #include <asm/smp_plat.h>
22 #define SRC_GPR1 0x020
23 #define BP_SRC_SCR_WARM_RESET_ENABLE 0
24 #define BP_SRC_SCR_CORE1_RST 14
25 #define BP_SRC_SCR_CORE1_ENABLE 22
27 static void __iomem *src_base;
29 void imx_enable_cpu(int cpu, bool enable)
33 cpu = cpu_logical_map(cpu);
34 mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
35 val = readl_relaxed(src_base + SRC_SCR);
36 val = enable ? val | mask : val & ~mask;
37 writel_relaxed(val, src_base + SRC_SCR);
40 void imx_set_cpu_jump(int cpu, void *jump_addr)
42 cpu = cpu_logical_map(cpu);
43 writel_relaxed(virt_to_phys(jump_addr),
44 src_base + SRC_GPR1 + cpu * 8);
47 u32 imx_get_cpu_arg(int cpu)
49 cpu = cpu_logical_map(cpu);
50 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4);
53 void imx_set_cpu_arg(int cpu, u32 arg)
55 cpu = cpu_logical_map(cpu);
56 writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4);
59 void imx_src_prepare_restart(void)
63 /* clear enable bits of secondary cores */
64 val = readl_relaxed(src_base + SRC_SCR);
65 val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
66 writel_relaxed(val, src_base + SRC_SCR);
68 /* clear persistent entry register of primary core */
69 writel_relaxed(0, src_base + SRC_GPR1);
72 void __init imx_src_init(void)
74 struct device_node *np;
77 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
80 src_base = of_iomap(np, 0);
84 * force warm reset sources to generate cold reset
85 * for a more reliable restart
87 val = readl_relaxed(src_base + SRC_SCR);
88 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
89 writel_relaxed(val, src_base + SRC_SCR);