2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/timex.h>
27 #include <linux/clocksource.h>
28 #include <linux/clockchips.h>
30 #include <linux/export.h>
33 #include <mach/hardware.h>
34 #include <asm/uaccess.h>
35 #include <asm/pgtable.h>
38 #include <asm/sched_clock.h>
39 #include <asm/system_misc.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/irq.h>
43 #include <asm/mach/time.h>
45 static void __init ixp4xx_clocksource_init(void);
46 static void __init ixp4xx_clockevent_init(void);
47 static struct clock_event_device clockevent_ixp4xx;
49 /*************************************************************************
50 * IXP4xx chipset I/O mapping
51 *************************************************************************/
52 static struct map_desc ixp4xx_io_desc[] __initdata = {
53 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
54 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
55 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
56 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
58 }, { /* Expansion Bus Config Registers */
59 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
60 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
61 .length = IXP4XX_EXP_CFG_REGION_SIZE,
63 }, { /* PCI Registers */
64 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
65 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
66 .length = IXP4XX_PCI_CFG_REGION_SIZE,
69 #ifdef CONFIG_DEBUG_LL
70 { /* Debug UART mapping */
71 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
72 .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
73 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
79 void __init ixp4xx_map_io(void)
81 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
85 /*************************************************************************
86 * IXP4xx chipset IRQ handling
88 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
89 * (be it PCI or something else) configures that GPIO line
91 **************************************************************************/
92 enum ixp4xx_irq_type {
93 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
96 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
97 static unsigned long long ixp4xx_irq_edge = 0;
100 * IRQ -> GPIO mapping table
102 static signed char irq2gpio[32] = {
103 -1, -1, -1, -1, -1, -1, 0, 1,
104 -1, -1, -1, -1, -1, -1, -1, -1,
105 -1, -1, -1, 2, 3, 4, 5, 6,
106 7, 8, 9, 10, 11, 12, -1, -1,
109 int gpio_to_irq(int gpio)
113 for (irq = 0; irq < 32; irq++) {
114 if (irq2gpio[irq] == gpio)
119 EXPORT_SYMBOL(gpio_to_irq);
121 int irq_to_gpio(unsigned int irq)
123 int gpio = (irq < 32) ? irq2gpio[irq] : -EINVAL;
130 EXPORT_SYMBOL(irq_to_gpio);
132 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
134 int line = irq2gpio[d->irq];
136 enum ixp4xx_irq_type irq_type;
137 volatile u32 *int_reg;
146 case IRQ_TYPE_EDGE_BOTH:
147 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
148 irq_type = IXP4XX_IRQ_EDGE;
150 case IRQ_TYPE_EDGE_RISING:
151 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
152 irq_type = IXP4XX_IRQ_EDGE;
154 case IRQ_TYPE_EDGE_FALLING:
155 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
156 irq_type = IXP4XX_IRQ_EDGE;
158 case IRQ_TYPE_LEVEL_HIGH:
159 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
160 irq_type = IXP4XX_IRQ_LEVEL;
162 case IRQ_TYPE_LEVEL_LOW:
163 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
164 irq_type = IXP4XX_IRQ_LEVEL;
170 if (irq_type == IXP4XX_IRQ_EDGE)
171 ixp4xx_irq_edge |= (1 << d->irq);
173 ixp4xx_irq_edge &= ~(1 << d->irq);
175 if (line >= 8) { /* pins 8-15 */
177 int_reg = IXP4XX_GPIO_GPIT2R;
178 } else { /* pins 0-7 */
179 int_reg = IXP4XX_GPIO_GPIT1R;
182 /* Clear the style for the appropriate pin */
183 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
184 (line * IXP4XX_GPIO_STYLE_SIZE));
186 *IXP4XX_GPIO_GPISR = (1 << line);
188 /* Set the new style */
189 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
191 /* Configure the line as an input */
192 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
197 static void ixp4xx_irq_mask(struct irq_data *d)
199 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
200 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
202 *IXP4XX_ICMR &= ~(1 << d->irq);
205 static void ixp4xx_irq_ack(struct irq_data *d)
207 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
210 *IXP4XX_GPIO_GPISR = (1 << line);
214 * Level triggered interrupts on GPIO lines can only be cleared when the
215 * interrupt condition disappears.
217 static void ixp4xx_irq_unmask(struct irq_data *d)
219 if (!(ixp4xx_irq_edge & (1 << d->irq)))
222 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
223 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
225 *IXP4XX_ICMR |= (1 << d->irq);
228 static struct irq_chip ixp4xx_irq_chip = {
230 .irq_ack = ixp4xx_irq_ack,
231 .irq_mask = ixp4xx_irq_mask,
232 .irq_unmask = ixp4xx_irq_unmask,
233 .irq_set_type = ixp4xx_set_irq_type,
236 void __init ixp4xx_init_irq(void)
241 * ixp4xx does not implement the XScale PWRMODE register
242 * so it must not call cpu_do_idle().
246 /* Route all sources to IRQ instead of FIQ */
249 /* Disable all interrupt */
252 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
253 /* Route upper 32 sources to IRQ instead of FIQ */
254 *IXP4XX_ICLR2 = 0x00;
256 /* Disable upper 32 interrupts */
257 *IXP4XX_ICMR2 = 0x00;
260 /* Default to all level triggered */
261 for(i = 0; i < NR_IRQS; i++) {
262 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
264 set_irq_flags(i, IRQF_VALID);
269 /*************************************************************************
271 * We use OS timer1 on the CPU for the timer tick and the timestamp
272 * counter as a source of real clock ticks to account for missed jiffies.
273 *************************************************************************/
275 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
277 struct clock_event_device *evt = dev_id;
279 /* Clear Pending Interrupt by writing '1' to it */
280 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
282 evt->event_handler(evt);
287 static struct irqaction ixp4xx_timer_irq = {
289 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
290 .handler = ixp4xx_timer_interrupt,
291 .dev_id = &clockevent_ixp4xx,
294 void __init ixp4xx_timer_init(void)
296 /* Reset/disable counter */
299 /* Clear Pending Interrupt by writing '1' to it */
300 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
302 /* Reset time-stamp counter */
305 /* Connect the interrupt handler and enable the interrupt */
306 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
308 ixp4xx_clocksource_init();
309 ixp4xx_clockevent_init();
312 struct sys_timer ixp4xx_timer = {
313 .init = ixp4xx_timer_init,
316 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
318 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
320 memcpy(&ixp4xx_udc_info, info, sizeof *info);
323 static struct resource ixp4xx_udc_resources[] = {
327 .flags = IORESOURCE_MEM,
330 .start = IRQ_IXP4XX_USB,
331 .end = IRQ_IXP4XX_USB,
332 .flags = IORESOURCE_IRQ,
337 * USB device controller. The IXP4xx uses the same controller as PXA25X,
338 * so we just use the same device.
340 static struct platform_device ixp4xx_udc_device = {
341 .name = "pxa25x-udc",
344 .resource = ixp4xx_udc_resources,
346 .platform_data = &ixp4xx_udc_info,
350 static struct platform_device *ixp4xx_devices[] __initdata = {
354 static struct resource ixp46x_i2c_resources[] = {
358 .flags = IORESOURCE_MEM,
361 .start = IRQ_IXP4XX_I2C,
362 .end = IRQ_IXP4XX_I2C,
363 .flags = IORESOURCE_IRQ
368 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
369 * we just use the same device name.
371 static struct platform_device ixp46x_i2c_controller = {
372 .name = "IOP3xx-I2C",
375 .resource = ixp46x_i2c_resources
378 static struct platform_device *ixp46x_devices[] __initdata = {
379 &ixp46x_i2c_controller
382 unsigned long ixp4xx_exp_bus_size;
383 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
385 void __init ixp4xx_sys_init(void)
387 ixp4xx_exp_bus_size = SZ_16M;
389 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
391 if (cpu_is_ixp46x()) {
394 platform_add_devices(ixp46x_devices,
395 ARRAY_SIZE(ixp46x_devices));
397 for (region = 0; region < 7; region++) {
398 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
399 ixp4xx_exp_bus_size = SZ_32M;
405 printk("IXP4xx: Using %luMiB expansion bus window size\n",
406 ixp4xx_exp_bus_size >> 20);
412 static u32 notrace ixp4xx_read_sched_clock(void)
421 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
426 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
427 EXPORT_SYMBOL(ixp4xx_timer_freq);
428 static void __init ixp4xx_clocksource_init(void)
430 setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
432 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
433 ixp4xx_clocksource_read);
439 static int ixp4xx_set_next_event(unsigned long evt,
440 struct clock_event_device *unused)
442 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
444 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
449 static void ixp4xx_set_mode(enum clock_event_mode mode,
450 struct clock_event_device *evt)
452 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
453 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
456 case CLOCK_EVT_MODE_PERIODIC:
457 osrt = LATCH & ~IXP4XX_OST_RELOAD_MASK;
458 opts = IXP4XX_OST_ENABLE;
460 case CLOCK_EVT_MODE_ONESHOT:
461 /* period set by 'set next_event' */
463 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
465 case CLOCK_EVT_MODE_SHUTDOWN:
466 opts &= ~IXP4XX_OST_ENABLE;
468 case CLOCK_EVT_MODE_RESUME:
469 opts |= IXP4XX_OST_ENABLE;
471 case CLOCK_EVT_MODE_UNUSED:
477 *IXP4XX_OSRT1 = osrt | opts;
480 static struct clock_event_device clockevent_ixp4xx = {
481 .name = "ixp4xx timer1",
482 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
485 .set_mode = ixp4xx_set_mode,
486 .set_next_event = ixp4xx_set_next_event,
489 static void __init ixp4xx_clockevent_init(void)
491 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
492 clockevent_ixp4xx.shift);
493 clockevent_ixp4xx.max_delta_ns =
494 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
495 clockevent_ixp4xx.min_delta_ns =
496 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
497 clockevent_ixp4xx.cpumask = cpumask_of(0);
499 clockevents_register_device(&clockevent_ixp4xx);
502 void ixp4xx_restart(char mode, const char *cmd)
504 if ( 1 && mode == 's') {
505 /* Jump into ROM at address 0 */
508 /* Use on-chip reset capability */
510 /* set the "key" register to enable access to
511 * "timer" and "enable" registers
513 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
515 /* write 0 to the timer register for an immediate reset */
518 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;