2 * arch/arm/mach-ixp4xx/include/mach/io.h
4 * Author: Deepak Saxena <dsaxena@plexity.net>
6 * Copyright (C) 2002-2005 MontaVista Software, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __ASM_ARM_ARCH_IO_H
14 #define __ASM_ARM_ARCH_IO_H
16 #include <linux/bitops.h>
18 #include <mach/hardware.h>
20 #define IO_SPACE_LIMIT 0x0000ffff
22 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
23 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
27 * IXP4xx provides two methods of accessing PCI memory space:
29 * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
30 * To access PCI via this space, we simply ioremap() the BAR
31 * into the kernel and we can use the standard read[bwl]/write[bwl]
32 * macros. This is the preffered method due to speed but it
33 * limits the system to just 64MB of PCI memory. This can be
34 * problamatic if using video cards and other memory-heavy
37 * 2) If > 64MB of memory space is required, the IXP4xx can be configured
38 * to use indirect registers to access PCI (as we do below for I/O
39 * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
40 * of memory on the bus. The disadvantage of this is that every
41 * PCI access requires three local register accesses plus a spinlock,
42 * but in some cases the performance hit is acceptable. In addition,
43 * you cannot mmap() PCI devices in this case.
46 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
48 #define __mem_pci(a) (a)
53 * In the case of using indirect PCI, we simply return the actual PCI
54 * address and our read/write implementation use that to drive the
55 * access registers. If something outside of PCI is ioremap'd, we
56 * fallback to the default.
58 static inline void __iomem *
59 __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
61 if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
62 return __arm_ioremap(addr, size, mtype);
64 return (void __iomem *)addr;
68 __ixp4xx_iounmap(void __iomem *addr)
70 if ((__force u32)addr >= VMALLOC_START)
74 #define __arch_ioremap(a, s, f) __ixp4xx_ioremap(a, s, f)
75 #define __arch_iounmap(a) __ixp4xx_iounmap(a)
77 #define writeb(v, p) __ixp4xx_writeb(v, p)
78 #define writew(v, p) __ixp4xx_writew(v, p)
79 #define writel(v, p) __ixp4xx_writel(v, p)
81 #define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
82 #define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
83 #define writesl(p, v, l) __ixp4xx_writesl(p, v, l)
85 #define readb(p) __ixp4xx_readb(p)
86 #define readw(p) __ixp4xx_readw(p)
87 #define readl(p) __ixp4xx_readl(p)
89 #define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
90 #define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
91 #define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
94 __ixp4xx_writeb(u8 value, volatile void __iomem *p)
97 u32 n, byte_enables, data;
99 if (addr >= VMALLOC_START) {
100 __raw_writeb(value, addr);
105 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
106 data = value << (8*n);
107 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
111 __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count)
114 writeb(*vaddr++, bus_addr);
118 __ixp4xx_writew(u16 value, volatile void __iomem *p)
121 u32 n, byte_enables, data;
123 if (addr >= VMALLOC_START) {
124 __raw_writew(value, addr);
129 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
130 data = value << (8*n);
131 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
135 __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count)
138 writew(*vaddr++, bus_addr);
142 __ixp4xx_writel(u32 value, volatile void __iomem *p)
144 u32 addr = (__force u32)p;
145 if (addr >= VMALLOC_START) {
146 __raw_writel(value, p);
150 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
154 __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count)
157 writel(*vaddr++, bus_addr);
160 static inline unsigned char
161 __ixp4xx_readb(const volatile void __iomem *p)
164 u32 n, byte_enables, data;
166 if (addr >= VMALLOC_START)
167 return __raw_readb(addr);
170 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
171 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
174 return data >> (8*n);
178 __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count)
181 *vaddr++ = readb(bus_addr);
184 static inline unsigned short
185 __ixp4xx_readw(const volatile void __iomem *p)
188 u32 n, byte_enables, data;
190 if (addr >= VMALLOC_START)
191 return __raw_readw(addr);
194 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
195 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
202 __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count)
205 *vaddr++ = readw(bus_addr);
208 static inline unsigned long
209 __ixp4xx_readl(const volatile void __iomem *p)
211 u32 addr = (__force u32)p;
214 if (addr >= VMALLOC_START)
215 return __raw_readl(p);
217 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
224 __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count)
227 *vaddr++ = readl(bus_addr);
232 * We can use the built-in functions b/c they end up calling writeb/readb
234 #define memset_io(c,v,l) _memset_io((c),(v),(l))
235 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
236 #define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
242 #define __io(v) __typesafe_io(v)
247 * IXP4xx does not have a transparent cpu -> PCI I/O translation
248 * window. Instead, it has a set of registers that must be tweaked
249 * with the proper byte lanes, command types, and address for the
250 * transaction. This means that we need to override the default
253 #define outb(p, v) __ixp4xx_outb(p, v)
254 #define outw(p, v) __ixp4xx_outw(p, v)
255 #define outl(p, v) __ixp4xx_outl(p, v)
257 #define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
258 #define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
259 #define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
261 #define inb(p) __ixp4xx_inb(p)
262 #define inw(p) __ixp4xx_inw(p)
263 #define inl(p) __ixp4xx_inl(p)
265 #define insb(p, v, l) __ixp4xx_insb(p, v, l)
266 #define insw(p, v, l) __ixp4xx_insw(p, v, l)
267 #define insl(p, v, l) __ixp4xx_insl(p, v, l)
271 __ixp4xx_outb(u8 value, u32 addr)
273 u32 n, byte_enables, data;
275 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
276 data = value << (8*n);
277 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
281 __ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
284 outb(*vaddr++, io_addr);
288 __ixp4xx_outw(u16 value, u32 addr)
290 u32 n, byte_enables, data;
292 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
293 data = value << (8*n);
294 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
298 __ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
301 outw(cpu_to_le16(*vaddr++), io_addr);
305 __ixp4xx_outl(u32 value, u32 addr)
307 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
311 __ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
314 outl(cpu_to_le32(*vaddr++), io_addr);
318 __ixp4xx_inb(u32 addr)
320 u32 n, byte_enables, data;
322 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
323 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
326 return data >> (8*n);
330 __ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
333 *vaddr++ = inb(io_addr);
337 __ixp4xx_inw(u32 addr)
339 u32 n, byte_enables, data;
341 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
342 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
349 __ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
352 *vaddr++ = le16_to_cpu(inw(io_addr));
356 __ixp4xx_inl(u32 addr)
359 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
366 __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
369 *vaddr++ = le32_to_cpu(inl(io_addr));
372 #define PIO_OFFSET 0x10000UL
373 #define PIO_MASK 0x0ffffUL
375 #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
376 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
378 static inline unsigned int
379 __ixp4xx_ioread8(const void __iomem *addr)
381 unsigned long port = (unsigned long __force)addr;
382 if (__is_io_address(port))
383 return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
385 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
386 return (unsigned int)__raw_readb(port);
388 return (unsigned int)__ixp4xx_readb(addr);
393 __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count)
395 unsigned long port = (unsigned long __force)addr;
396 if (__is_io_address(port))
397 __ixp4xx_insb(port & PIO_MASK, vaddr, count);
399 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
400 __raw_readsb(addr, vaddr, count);
402 __ixp4xx_readsb(addr, vaddr, count);
406 static inline unsigned int
407 __ixp4xx_ioread16(const void __iomem *addr)
409 unsigned long port = (unsigned long __force)addr;
410 if (__is_io_address(port))
411 return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
413 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
414 return le16_to_cpu(__raw_readw((u32)port));
416 return (unsigned int)__ixp4xx_readw(addr);
421 __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count)
423 unsigned long port = (unsigned long __force)addr;
424 if (__is_io_address(port))
425 __ixp4xx_insw(port & PIO_MASK, vaddr, count);
427 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
428 __raw_readsw(addr, vaddr, count);
430 __ixp4xx_readsw(addr, vaddr, count);
434 static inline unsigned int
435 __ixp4xx_ioread32(const void __iomem *addr)
437 unsigned long port = (unsigned long __force)addr;
438 if (__is_io_address(port))
439 return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
441 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
442 return le32_to_cpu((__force __le32)__raw_readl(addr));
444 return (unsigned int)__ixp4xx_readl(addr);
450 __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count)
452 unsigned long port = (unsigned long __force)addr;
453 if (__is_io_address(port))
454 __ixp4xx_insl(port & PIO_MASK, vaddr, count);
456 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
457 __raw_readsl(addr, vaddr, count);
459 __ixp4xx_readsl(addr, vaddr, count);
464 __ixp4xx_iowrite8(u8 value, void __iomem *addr)
466 unsigned long port = (unsigned long __force)addr;
467 if (__is_io_address(port))
468 __ixp4xx_outb(value, port & PIO_MASK);
470 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
471 __raw_writeb(value, port);
473 __ixp4xx_writeb(value, addr);
478 __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
480 unsigned long port = (unsigned long __force)addr;
481 if (__is_io_address(port))
482 __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
484 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
485 __raw_writesb(addr, vaddr, count);
487 __ixp4xx_writesb(addr, vaddr, count);
492 __ixp4xx_iowrite16(u16 value, void __iomem *addr)
494 unsigned long port = (unsigned long __force)addr;
495 if (__is_io_address(port))
496 __ixp4xx_outw(value, port & PIO_MASK);
498 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
499 __raw_writew(cpu_to_le16(value), addr);
501 __ixp4xx_writew(value, addr);
506 __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
508 unsigned long port = (unsigned long __force)addr;
509 if (__is_io_address(port))
510 __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
512 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
513 __raw_writesw(addr, vaddr, count);
515 __ixp4xx_writesw(addr, vaddr, count);
520 __ixp4xx_iowrite32(u32 value, void __iomem *addr)
522 unsigned long port = (unsigned long __force)addr;
523 if (__is_io_address(port))
524 __ixp4xx_outl(value, port & PIO_MASK);
526 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
527 __raw_writel((u32 __force)cpu_to_le32(value), addr);
529 __ixp4xx_writel(value, addr);
534 __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
536 unsigned long port = (unsigned long __force)addr;
537 if (__is_io_address(port))
538 __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
540 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
541 __raw_writesl(addr, vaddr, count);
543 __ixp4xx_writesl(addr, vaddr, count);
547 #define ioread8(p) __ixp4xx_ioread8(p)
548 #define ioread16(p) __ixp4xx_ioread16(p)
549 #define ioread32(p) __ixp4xx_ioread32(p)
551 #define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
552 #define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
553 #define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
555 #define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
556 #define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
557 #define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
559 #define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
560 #define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
561 #define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
563 #define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
564 #define ioport_unmap(addr)
565 #endif // !CONFIG_PCI
567 #endif // __ASM_ARM_ARCH_IO_H