2 * K2L: Clock management APIs
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ASM_ARCH_CLOCK_K2L_H
11 #define __ASM_ARCH_CLOCK_K2L_H
23 ext_clk_count /* number of external clocks */
26 extern unsigned int external_clk[ext_clk_count];
28 #define CLK_LIST(CLK)\
31 CLK(2, tetris_pll_clk)\
34 CLK(5, sys_clk0_1_clk)\
35 CLK(6, sys_clk0_2_clk)\
36 CLK(7, sys_clk0_3_clk)\
37 CLK(8, sys_clk0_4_clk)\
38 CLK(9, sys_clk0_6_clk)\
39 CLK(10, sys_clk0_8_clk)\
40 CLK(11, sys_clk0_12_clk)\
41 CLK(12, sys_clk0_24_clk)\
42 CLK(13, sys_clk1_clk)\
43 CLK(14, sys_clk1_3_clk)\
44 CLK(15, sys_clk1_4_clk)\
45 CLK(16, sys_clk1_6_clk)\
46 CLK(17, sys_clk1_12_clk)\
47 CLK(18, sys_clk2_clk)\
48 CLK(19, sys_clk3_clk)\
50 #define PLLSET_CMD_LIST "<pa|arm|ddr3>"
52 #define KS2_CLK1_6 sys_clk0_6_clk
71 #define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
72 #define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
73 #define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
74 #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
75 #define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
76 #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
77 #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
78 #define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
79 #define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
80 #define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
81 #define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
82 #define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
83 #define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
84 #define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
85 #define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
86 #define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
87 #define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
88 #define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
89 #define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
90 #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
91 #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
92 #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
93 #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}