1 /* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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30 #ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
31 #define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
49 L_7X30_GRP_3D_SRC_CLK,
63 L_7X30_MDP_LCDC_PCLK_CLK,
64 L_7X30_MDP_LCDC_PAD_PCLK_CLK,
66 L_7X30_MI2S_CODEC_RX_M_CLK,
67 L_7X30_MI2S_CODEC_RX_S_CLK,
68 L_7X30_MI2S_CODEC_TX_M_CLK,
69 L_7X30_MI2S_CODEC_TX_S_CLK,
77 L_7X30_ROTATOR_IMEM_CLK,
90 L_7X30_USB_HS_SRC_CLK,
92 L_7X30_USB_HS_CORE_CLK,
95 L_7X30_USB_HS2_CORE_CLK,
98 L_7X30_USB_HS3_CORE_CLK,
103 L_7X30_VFE_CAMIF_CLK,
104 L_7X30_CAMIF_PAD_P_CLK,
120 L_7X30_GLBL_ROOT_CLK,
122 L_7X30_AXI_LI_VG_CLK,
123 L_7X30_AXI_LI_GRP_CLK,
124 L_7X30_AXI_LI_JPEG_CLK,
125 L_7X30_AXI_GRP_2D_CLK,
128 L_7X30_AXI_LI_VFE_CLK,
129 L_7X30_AXI_LI_APPS_CLK,
132 L_7X30_AXI_LI_ADSP_A_CLK,
133 L_7X30_AXI_ROTATOR_CLK,
139 extern struct clk_ops clk_ops_7x30;
141 struct clk_ops *clk_7x30_is_local(uint32_t id);
142 int clk_7x30_init(void);
144 void pll_enable(uint32_t pll);
145 void pll_disable(uint32_t pll);
147 extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
149 #define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) { \
151 .id = L_7X30_##clk_id, \
152 .remote_id = P_##clk_id, \
153 .flags = clk_flags, \
155 .dbg_name = #clk_id, \
158 #define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) { \
160 .id = L_7X30_##l_id, \
161 .remote_id = P_##r_id, \
162 .flags = clk_flags, \