2 * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/gpio.h>
16 #include <mach/hardware.h>
17 #include <mach/imx-uart.h>
18 #include <mach/irqs.h>
20 static struct resource uart0[] = {
22 .start = MX51_UART1_BASE_ADDR,
23 .end = MX51_UART1_BASE_ADDR + 0xfff,
24 .flags = IORESOURCE_MEM,
26 .start = MX51_MXC_INT_UART1,
27 .end = MX51_MXC_INT_UART1,
28 .flags = IORESOURCE_IRQ,
32 struct platform_device mxc_uart_device0 = {
36 .num_resources = ARRAY_SIZE(uart0),
39 static struct resource uart1[] = {
41 .start = MX51_UART2_BASE_ADDR,
42 .end = MX51_UART2_BASE_ADDR + 0xfff,
43 .flags = IORESOURCE_MEM,
45 .start = MX51_MXC_INT_UART2,
46 .end = MX51_MXC_INT_UART2,
47 .flags = IORESOURCE_IRQ,
51 struct platform_device mxc_uart_device1 = {
55 .num_resources = ARRAY_SIZE(uart1),
58 static struct resource uart2[] = {
60 .start = MX51_UART3_BASE_ADDR,
61 .end = MX51_UART3_BASE_ADDR + 0xfff,
62 .flags = IORESOURCE_MEM,
64 .start = MX51_MXC_INT_UART3,
65 .end = MX51_MXC_INT_UART3,
66 .flags = IORESOURCE_IRQ,
70 struct platform_device mxc_uart_device2 = {
74 .num_resources = ARRAY_SIZE(uart2),
77 static struct resource mxc_fec_resources[] = {
79 .start = MX51_MXC_FEC_BASE_ADDR,
80 .end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
81 .flags = IORESOURCE_MEM,
83 .start = MX51_MXC_INT_FEC,
84 .end = MX51_MXC_INT_FEC,
85 .flags = IORESOURCE_IRQ,
89 struct platform_device mxc_fec_device = {
92 .num_resources = ARRAY_SIZE(mxc_fec_resources),
93 .resource = mxc_fec_resources,
96 static struct resource mxc_i2c0_resources[] = {
98 .start = MX51_I2C1_BASE_ADDR,
99 .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
100 .flags = IORESOURCE_MEM,
102 .start = MX51_MXC_INT_I2C1,
103 .end = MX51_MXC_INT_I2C1,
104 .flags = IORESOURCE_IRQ,
108 struct platform_device mxc_i2c_device0 = {
111 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
112 .resource = mxc_i2c0_resources,
115 static struct resource mxc_i2c1_resources[] = {
117 .start = MX51_I2C2_BASE_ADDR,
118 .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
121 .start = MX51_MXC_INT_I2C2,
122 .end = MX51_MXC_INT_I2C2,
123 .flags = IORESOURCE_IRQ,
127 struct platform_device mxc_i2c_device1 = {
130 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
131 .resource = mxc_i2c1_resources,
134 static struct resource mxc_hsi2c_resources[] = {
136 .start = MX51_HSI2C_DMA_BASE_ADDR,
137 .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
138 .flags = IORESOURCE_MEM,
141 .start = MX51_MXC_INT_HS_I2C,
142 .end = MX51_MXC_INT_HS_I2C,
143 .flags = IORESOURCE_IRQ,
147 struct platform_device mxc_hsi2c_device = {
150 .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
151 .resource = mxc_hsi2c_resources
154 static u64 usb_dma_mask = DMA_BIT_MASK(32);
156 static struct resource usbotg_resources[] = {
158 .start = MX51_OTG_BASE_ADDR,
159 .end = MX51_OTG_BASE_ADDR + 0x1ff,
160 .flags = IORESOURCE_MEM,
163 .start = MX51_MXC_INT_USB_OTG,
164 .flags = IORESOURCE_IRQ,
168 /* OTG gadget device */
169 struct platform_device mxc_usbdr_udc_device = {
170 .name = "fsl-usb2-udc",
172 .num_resources = ARRAY_SIZE(usbotg_resources),
173 .resource = usbotg_resources,
175 .dma_mask = &usb_dma_mask,
176 .coherent_dma_mask = DMA_BIT_MASK(32),
180 struct platform_device mxc_usbdr_host_device = {
183 .num_resources = ARRAY_SIZE(usbotg_resources),
184 .resource = usbotg_resources,
186 .dma_mask = &usb_dma_mask,
187 .coherent_dma_mask = DMA_BIT_MASK(32),
191 static struct resource usbh1_resources[] = {
193 .start = MX51_OTG_BASE_ADDR + 0x200,
194 .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff,
195 .flags = IORESOURCE_MEM,
198 .start = MX51_MXC_INT_USB_H1,
199 .flags = IORESOURCE_IRQ,
203 struct platform_device mxc_usbh1_device = {
206 .num_resources = ARRAY_SIZE(usbh1_resources),
207 .resource = usbh1_resources,
209 .dma_mask = &usb_dma_mask,
210 .coherent_dma_mask = DMA_BIT_MASK(32),
214 static struct resource mxc_wdt_resources[] = {
216 .start = MX51_WDOG_BASE_ADDR,
217 .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1,
218 .flags = IORESOURCE_MEM,
222 struct platform_device mxc_wdt = {
225 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
226 .resource = mxc_wdt_resources,
229 static struct mxc_gpio_port mxc_gpio_ports[] = {
231 .chip.label = "gpio-0",
232 .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
233 .irq = MX51_MXC_INT_GPIO1_LOW,
234 .virtual_irq_start = MXC_GPIO_IRQ_START
237 .chip.label = "gpio-1",
238 .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
239 .irq = MX51_MXC_INT_GPIO2_LOW,
240 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
243 .chip.label = "gpio-2",
244 .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
245 .irq = MX51_MXC_INT_GPIO3_LOW,
246 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
249 .chip.label = "gpio-3",
250 .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
251 .irq = MX51_MXC_INT_GPIO4_LOW,
252 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
256 int __init mxc_register_gpios(void)
258 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));