arch/arm/mach-mx6/board-mx6q_sabresd.c

   1 /*
   2  * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/delay.h>
  22 #include <linux/pm.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/init.h>
  26 #include <linux/input.h>
  27 #include <linux/nodemask.h>
  28 #include <linux/clk.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/fsl_devices.h>
  31 #include <linux/spi/spi.h>
  32 #include <linux/spi/flash.h>
  33 #include <linux/i2c.h>
  34 #include <linux/i2c/pca953x.h>
  35 #include <linux/ata.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/map.h>
  38 #include <linux/mtd/partitions.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/pmic_external.h>
  41 #include <linux/pmic_status.h>
  42 #include <linux/ipu.h>
  43 #include <linux/mxcfb.h>
  44 #include <linux/pwm_backlight.h>
  45 #include <linux/fec.h>
  46 #include <linux/memblock.h>
  47 #include <linux/gpio.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/power/sabresd_battery.h>
  50 #include <linux/regulator/anatop-regulator.h>
  51 #include <linux/regulator/consumer.h>
  52 #include <linux/regulator/machine.h>
  53 #include <linux/regulator/fixed.h>
  54 #include <linux/mfd/max17135.h>
  55 #include <linux/mfd/wm8994/pdata.h>
  56 #include <linux/mfd/wm8994/gpio.h>
  57 #include <sound/wm8962.h>
  58 #include <linux/mfd/mxc-hdmi-core.h>
  59
  60 #include <mach/common.h>
  61 #include <mach/hardware.h>
  62 #include <mach/mxc_dvfs.h>
  63 #include <mach/memory.h>
  64 #include <mach/iomux-mx6q.h>
  65 #include <mach/imx-uart.h>
  66 #include <mach/viv_gpu.h>
  67 #include <mach/ahci_sata.h>
  68 #include <mach/ipu-v3.h>
  69 #include <mach/mxc_hdmi.h>
  70 #include <mach/mxc_asrc.h>
  71 #include <mach/mipi_dsi.h>
  72
  73 #include <asm/irq.h>
  74 #include <asm/setup.h>
  75 #include <asm/mach-types.h>
  76 #include <asm/mach/arch.h>
  77 #include <asm/mach/time.h>
  78
  79 #include "usb.h"
  80 #include "devices-imx6q.h"
  81 #include "crm_regs.h"
  82 #include "cpu_op-mx6.h"
  83 #include "board-mx6q_sabresd.h"
  84 #include "board-mx6dl_sabresd.h"
  85
  86 #define SABRESD_USR_DEF_GRN_LED IMX_GPIO_NR(1, 1)
  87 #define SABRESD_USR_DEF_RED_LED IMX_GPIO_NR(1, 2)
  88 #define SABRESD_VOLUME_UP       IMX_GPIO_NR(1, 4)
  89 #define SABRESD_VOLUME_DN       IMX_GPIO_NR(1, 5)
  90 #define SABRESD_MICROPHONE_DET  IMX_GPIO_NR(1, 9)
  91 #define SABRESD_CSI0_PWN        IMX_GPIO_NR(1, 16)
  92 #define SABRESD_CSI0_RST        IMX_GPIO_NR(1, 17)
  93 #define SABRESD_ACCL_INT        IMX_GPIO_NR(1, 18)
  94 #define SABRESD_MIPICSI_PWN     IMX_GPIO_NR(1, 19)
  95 #define SABRESD_MIPICSI_RST     IMX_GPIO_NR(1, 20)
  96 #define SABRESD_RGMII_RST       IMX_GPIO_NR(1, 25)
  97 #define SABRESD_RGMII_INT       IMX_GPIO_NR(1, 26)
  98 #define SABRESD_CHARGE_UOK_B    IMX_GPIO_NR(1, 27)
  99 #define SABRESD_USBH1_PWR_EN    IMX_GPIO_NR(1, 29)
 100 #define SABRESD_DISP0_PWR_EN    IMX_GPIO_NR(1, 30)
 101
 102 #define SABRESD_SD3_CD          IMX_GPIO_NR(2, 0)
 103 #define SABRESD_SD3_WP          IMX_GPIO_NR(2, 1)
 104 #define SABRESD_SD2_CD          IMX_GPIO_NR(2, 2)
 105 #define SABRESD_SD2_WP          IMX_GPIO_NR(2, 3)
 106 #define SABRESD_CHARGE_DOK_B    IMX_GPIO_NR(2, 24)
 107 #define SABRESD_GPS_RESET       IMX_GPIO_NR(2, 28)
 108 #define SABRESD_SENSOR_EN       IMX_GPIO_NR(2, 31)
 109
 110 #define SABRESD_GPS_EN  IMX_GPIO_NR(3, 0)
 111 #define SABRESD_DISP0_RST_B     IMX_GPIO_NR(3, 8)
 112 #define SABRESD_ALS_INT         IMX_GPIO_NR(3, 9)
 113 #define SABRESD_CHARGE_CHG_2_B  IMX_GPIO_NR(3, 13)
 114 #define SABRESD_CHARGE_FLT_2_B  IMX_GPIO_NR(3, 14)
 115 #define SABRESD_BAR0_INT        IMX_GPIO_NR(3, 15)
 116 #define SABRESD_eCOMPASS_INT    IMX_GPIO_NR(3, 16)
 117 #define SABRESD_GPS_PPS         IMX_GPIO_NR(3, 18)
 118 #define SABRESD_PCIE_PWR_EN     IMX_GPIO_NR(3, 19)
 119 #define SABRESD_USB_OTG_PWR     IMX_GPIO_NR(3, 22)
 120 #define SABRESD_USB_H1_PWR      IMX_GPIO_NR(1, 29)
 121 #define SABRESD_CHARGE_CHG_1_B  IMX_GPIO_NR(3, 23)
 122 #define SABRESD_TS_INT          IMX_GPIO_NR(3, 26)
 123 #define SABRESD_DISP0_RD        IMX_GPIO_NR(3, 28)
 124 #define SABRESD_POWER_OFF       IMX_GPIO_NR(3, 29)
 125
 126 #define SABRESD_CAN1_STBY       IMX_GPIO_NR(4, 5)
 127 #define SABRESD_ECSPI1_CS0  IMX_GPIO_NR(4, 9)
 128 #define SABRESD_CODEC_PWR_EN    IMX_GPIO_NR(4, 10)
 129 #define SABRESD_HDMI_CEC_IN     IMX_GPIO_NR(4, 11)
 130 #define SABRESD_PCIE_DIS_B      IMX_GPIO_NR(4, 14)
 131
 132 #define SABRESD_DI0_D0_CS       IMX_GPIO_NR(5, 0)
 133 #define SABRESD_CHARGE_FLT_1_B  IMX_GPIO_NR(5, 2)
 134 #define SABRESD_PCIE_WAKE_B     IMX_GPIO_NR(5, 20)
 135
 136 #define SABRESD_CAP_TCH_INT1    IMX_GPIO_NR(6, 7)
 137 #define SABRESD_CAP_TCH_INT0    IMX_GPIO_NR(6, 8)
 138 #define SABRESD_DISP_RST_B      IMX_GPIO_NR(6, 11)
 139 #define SABRESD_DISP_PWR_EN     IMX_GPIO_NR(6, 14)
 140 #define SABRESD_CABC_EN0        IMX_GPIO_NR(6, 15)
 141 #define SABRESD_CABC_EN1        IMX_GPIO_NR(6, 16)
 142 #define SABRESD_AUX_3V15_EN     IMX_GPIO_NR(6, 9)
 143 #define SABRESD_DISP0_WR_REVB   IMX_GPIO_NR(6, 9)
 144 #define SABRESD_AUX_5V_EN       IMX_GPIO_NR(6, 10)
 145 #define SABRESD_DI1_D0_CS       IMX_GPIO_NR(6, 31)
 146
 147 #define SABRESD_HEADPHONE_DET   IMX_GPIO_NR(7, 8)
 148 #define SABRESD_PCIE_RST_B_REVB IMX_GPIO_NR(7, 12)
 149 #define SABRESD_PMIC_INT_B      IMX_GPIO_NR(7, 13)
 150 #define SABRESD_PFUZE_INT       IMX_GPIO_NR(7, 13)
 151
 152 #define SABRESD_EPDC_SDDO_0     IMX_GPIO_NR(2, 22)
 153 #define SABRESD_EPDC_SDDO_1     IMX_GPIO_NR(3, 10)
 154 #define SABRESD_EPDC_SDDO_2     IMX_GPIO_NR(3, 12)
 155 #define SABRESD_EPDC_SDDO_3     IMX_GPIO_NR(3, 11)
 156 #define SABRESD_EPDC_SDDO_4     IMX_GPIO_NR(2, 27)
 157 #define SABRESD_EPDC_SDDO_5     IMX_GPIO_NR(2, 30)
 158 #define SABRESD_EPDC_SDDO_6     IMX_GPIO_NR(2, 23)
 159 #define SABRESD_EPDC_SDDO_7     IMX_GPIO_NR(2, 26)
 160 #define SABRESD_EPDC_SDDO_8     IMX_GPIO_NR(2, 24)
 161 #define SABRESD_EPDC_SDDO_9     IMX_GPIO_NR(3, 15)
 162 #define SABRESD_EPDC_SDDO_10    IMX_GPIO_NR(3, 16)
 163 #define SABRESD_EPDC_SDDO_11    IMX_GPIO_NR(3, 23)
 164 #define SABRESD_EPDC_SDDO_12    IMX_GPIO_NR(3, 19)
 165 #define SABRESD_EPDC_SDDO_13    IMX_GPIO_NR(3, 13)
 166 #define SABRESD_EPDC_SDDO_14    IMX_GPIO_NR(3, 14)
 167 #define SABRESD_EPDC_SDDO_15    IMX_GPIO_NR(5, 2)
 168 #define SABRESD_EPDC_GDCLK      IMX_GPIO_NR(2, 17)
 169 #define SABRESD_EPDC_GDSP       IMX_GPIO_NR(2, 16)
 170 #define SABRESD_EPDC_GDOE       IMX_GPIO_NR(6, 6)
 171 #define SABRESD_EPDC_GDRL       IMX_GPIO_NR(5, 4)
 172 #define SABRESD_EPDC_SDCLK      IMX_GPIO_NR(3, 31)
 173 #define SABRESD_EPDC_SDOEZ      IMX_GPIO_NR(3, 30)
 174 #define SABRESD_EPDC_SDOED      IMX_GPIO_NR(3, 26)
 175 #define SABRESD_EPDC_SDOE       IMX_GPIO_NR(3, 27)
 176 #define SABRESD_EPDC_SDLE       IMX_GPIO_NR(3, 1)
 177 #define SABRESD_EPDC_SDCLKN     IMX_GPIO_NR(3, 0)
 178 #define SABRESD_EPDC_SDSHR      IMX_GPIO_NR(2, 29)
 179 #define SABRESD_EPDC_PWRCOM     IMX_GPIO_NR(2, 28)
 180 #define SABRESD_EPDC_PWRSTAT    IMX_GPIO_NR(2, 21)
 181 #define SABRESD_EPDC_PWRCTRL0   IMX_GPIO_NR(2, 20)
 182 #define SABRESD_EPDC_PWRCTRL1   IMX_GPIO_NR(2, 19)
 183 #define SABRESD_EPDC_PWRCTRL2   IMX_GPIO_NR(2, 18)
 184 #define SABRESD_EPDC_PWRCTRL3   IMX_GPIO_NR(3, 28)
 185 #define SABRESD_EPDC_BDR0       IMX_GPIO_NR(3, 2)
 186 #define SABRESD_EPDC_BDR1       IMX_GPIO_NR(3, 3)
 187 #define SABRESD_EPDC_SDCE0      IMX_GPIO_NR(3, 4)
 188 #define SABRESD_EPDC_SDCE1      IMX_GPIO_NR(3, 5)
 189 #define SABRESD_EPDC_SDCE2      IMX_GPIO_NR(3, 6)
 190 #define SABRESD_EPDC_SDCE3      IMX_GPIO_NR(3, 7)
 191 #define SABRESD_EPDC_SDCE4      IMX_GPIO_NR(3, 8)
 192 #define SABRESD_EPDC_PMIC_WAKE  IMX_GPIO_NR(3, 20)
 193 #define SABRESD_EPDC_PMIC_INT   IMX_GPIO_NR(2, 25)
 194 #define SABRESD_EPDC_VCOM       IMX_GPIO_NR(3, 17)
 195 #define SABRESD_CHARGE_NOW      IMX_GPIO_NR(1, 2)
 196 #define SABRESD_CHARGE_DONE     IMX_GPIO_NR(1, 1)
 197 #define SABRESD_ELAN_CE         IMX_GPIO_NR(2, 18)
 198 #define SABRESD_ELAN_RST        IMX_GPIO_NR(3, 8)
 199 #define SABRESD_ELAN_INT        IMX_GPIO_NR(3, 28)
 200
 201 static struct clk *sata_clk;
 202 static struct clk *clko;
 203 static int mma8451_position = 1;
 204 static int mag3110_position = 2;
 205 static int max11801_mode = 1;
 206 static int enable_lcd_ldb;
 207 static int caam_enabled;
 208
 209 extern char *gp_reg_id;
 210 extern char *soc_reg_id;
 211 extern char *pu_reg_id;
 212 extern int epdc_enabled;
 213
 214 static int max17135_regulator_init(struct max17135 *max17135);
 215
 216 static const struct esdhc_platform_data mx6q_sabresd_sd2_data __initconst = {
 217         .cd_gpio = SABRESD_SD2_CD,
 218         .wp_gpio = SABRESD_SD2_WP,
 219         .keep_power_at_suspend = 1,
 220         .support_8bit = 1,
 221         .delay_line = 0,
 222         .cd_type = ESDHC_CD_CONTROLLER,
 223 };
 224
 225 static const struct esdhc_platform_data mx6q_sabresd_sd3_data __initconst = {
 226         .cd_gpio = SABRESD_SD3_CD,
 227         .wp_gpio = SABRESD_SD3_WP,
 228         .keep_power_at_suspend = 1,
 229         .support_8bit = 1,
 230         .delay_line = 0,
 231         .cd_type = ESDHC_CD_CONTROLLER,
 232 };
 233
 234 static const struct esdhc_platform_data mx6q_sabresd_sd4_data __initconst = {
 235         .always_present = 1,
 236         .keep_power_at_suspend = 1,
 237         .support_8bit = 1,
 238         .delay_line = 0,
 239         .cd_type = ESDHC_CD_PERMANENT,
 240 };
 241
 242 static const struct anatop_thermal_platform_data
 243         mx6q_sabresd_anatop_thermal_data __initconst = {
 244                 .name = "anatop_thermal",
 245 };
 246
 247 static inline void mx6q_sabresd_init_uart(void)
 248 {
 249         imx6q_add_imx_uart(2, NULL);
 250         imx6q_add_imx_uart(0, NULL);
 251 }
 252
 253 static int mx6q_sabresd_fec_phy_init(struct phy_device *phydev)
 254 {
 255         unsigned short val;
 256
 257         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 258         phy_write(phydev, 0xd, 0x7);
 259         phy_write(phydev, 0xe, 0x8016);
 260         phy_write(phydev, 0xd, 0x4007);
 261         val = phy_read(phydev, 0xe);
 262
 263         val &= 0xffe3;
 264         val |= 0x18;
 265         phy_write(phydev, 0xe, val);
 266
 267         /* Introduce tx clock delay */
 268         phy_write(phydev, 0x1d, 0x5);
 269         val = phy_read(phydev, 0x1e);
 270         val |= 0x0100;
 271         phy_write(phydev, 0x1e, val);
 272
 273         /*check phy power*/
 274         val = phy_read(phydev, 0x0);
 275
 276         if (val & BMCR_PDOWN)
 277                 phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));
 278
 279         return 0;
 280 }
 281
 282 static struct fec_platform_data fec_data __initdata = {
 283         .init = mx6q_sabresd_fec_phy_init,
 284         .phy = PHY_INTERFACE_MODE_RGMII,
 285 };
 286
 287 static int mx6q_sabresd_spi_cs[] = {
 288         SABRESD_ECSPI1_CS0,
 289 };
 290
 291 static const struct spi_imx_master mx6q_sabresd_spi_data __initconst = {
 292         .chipselect     = mx6q_sabresd_spi_cs,
 293         .num_chipselect = ARRAY_SIZE(mx6q_sabresd_spi_cs),
 294 };
 295
 296 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
 297 static struct mtd_partition imx6_sabresd_spi_nor_partitions[] = {
 298         {
 299          .name = "bootloader",
 300          .offset = 0,
 301          .size = 0x00100000,
 302         },
 303         {
 304          .name = "kernel",
 305          .offset = MTDPART_OFS_APPEND,
 306          .size = MTDPART_SIZ_FULL,
 307         },
 308 };
 309
 310 static struct flash_platform_data imx6_sabresd__spi_flash_data = {
 311         .name = "m25p80",
 312         .parts = imx6_sabresd_spi_nor_partitions,
 313         .nr_parts = ARRAY_SIZE(imx6_sabresd_spi_nor_partitions),
 314         .type = "sst25vf016b",
 315 };
 316 #endif
 317
 318 static struct spi_board_info imx6_sabresd_spi_nor_device[] __initdata = {
 319 #if defined(CONFIG_MTD_M25P80)
 320         {
 321                 .modalias = "m25p80",
 322                 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
 323                 .bus_num = 0,
 324                 .chip_select = 0,
 325                 .platform_data = &imx6_sabresd__spi_flash_data,
 326         },
 327 #endif
 328 };
 329
 330 static void spi_device_init(void)
 331 {
 332         spi_register_board_info(imx6_sabresd_spi_nor_device,
 333                                 ARRAY_SIZE(imx6_sabresd_spi_nor_device));
 334 }
 335
 336 static struct imx_ssi_platform_data mx6_sabresd_ssi_pdata = {
 337         .flags = IMX_SSI_DMA | IMX_SSI_SYN,
 338 };
 339
 340 static struct platform_device mx6_sabresd_audio_wm8958_device = {
 341         .name = "imx-wm8958",
 342 };
 343
 344 static struct mxc_audio_platform_data wm8958_data = {
 345         .ssi_num = 1,
 346         .src_port = 2,
 347         .ext_port = 3,
 348         .hp_gpio = SABRESD_HEADPHONE_DET,
 349         .hp_active_low = 1,
 350 };
 351
 352 static struct wm8994_pdata wm8958_config_data = {
 353         .gpio_defaults = {
 354                 [0] = WM8994_GP_FN_GPIO | WM8994_GPN_DB,
 355                 [1] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 356                 [2] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 357                 [3] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 358                 [4] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 359                 [5] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 360                 [7] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 361                 [8] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 362                 [9] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 363                 [10] = WM8994_GP_FN_GPIO | WM8994_GPN_DB | WM8994_GPN_PD,
 364         },
 365 };
 366
 367 static int mxc_wm8958_init(void)
 368 {
 369         struct clk *clko;
 370         int rate;
 371
 372         clko = clk_get(NULL, "clko_clk");
 373         if (IS_ERR(clko)) {
 374                 pr_err("can't get CLKO clock.\n");
 375                 return PTR_ERR(clko);
 376         }
 377         /* both audio codec and comera use CLKO clk*/
 378         rate = clk_round_rate(clko, 24000000);
 379
 380         wm8958_data.sysclk = rate;
 381         clk_set_rate(clko, rate);
 382
 383         /* enable wm8958 4.2v power supply */
 384         gpio_request(SABRESD_CODEC_PWR_EN, "aud_4v2");
 385         gpio_direction_output(SABRESD_CODEC_PWR_EN, 1);
 386         msleep(1);
 387         gpio_set_value(SABRESD_CODEC_PWR_EN, 1);
 388
 389         return 0;
 390 }
 391
 392 static struct platform_device mx6_sabresd_audio_wm8962_device = {
 393         .name = "imx-wm8962",
 394 };
 395
 396 static struct mxc_audio_platform_data wm8962_data;
 397
 398 static int wm8962_clk_enable(int enable)
 399 {
 400         if (enable)
 401                 clk_enable(clko);
 402         else
 403                 clk_disable(clko);
 404
 405         return 0;
 406 }
 407
 408 static int mxc_wm8962_init(void)
 409 {
 410         int rate;
 411
 412         clko = clk_get(NULL, "clko_clk");
 413         if (IS_ERR(clko)) {
 414                 pr_err("can't get CLKO clock.\n");
 415                 return PTR_ERR(clko);
 416         }
 417         /* both audio codec and comera use CLKO clk*/
 418         rate = clk_round_rate(clko, 24000000);
 419         clk_set_rate(clko, rate);
 420
 421         wm8962_data.sysclk = rate;
 422
 423         return 0;
 424 }
 425
 426 static struct wm8962_pdata wm8962_config_data = {
 427         .gpio_init = {
 428                 [2] = WM8962_GPIO_FN_DMICCLK,
 429                 [4] = 0x8000 | WM8962_GPIO_FN_DMICDAT,
 430         },
 431 };
 432
 433 static struct mxc_audio_platform_data wm8962_data = {
 434         .ssi_num = 1,
 435         .src_port = 2,
 436         .ext_port = 3,
 437         .hp_gpio = SABRESD_HEADPHONE_DET,
 438         .hp_active_low = 1,
 439         .mic_gpio = SABRESD_MICROPHONE_DET,
 440         .mic_active_low = 1,
 441         .init = mxc_wm8962_init,
 442         .clock_enable = wm8962_clk_enable,
 443 };
 444
 445 static struct regulator_consumer_supply sabresd_vwm8962_consumers[] = {
 446         REGULATOR_SUPPLY("SPKVDD1", "0-001a"),
 447         REGULATOR_SUPPLY("SPKVDD2", "0-001a"),
 448 };
 449
 450 static struct regulator_init_data sabresd_vwm8962_init = {
 451         .constraints = {
 452                 .name = "SPKVDD",
 453                 .valid_ops_mask =  REGULATOR_CHANGE_STATUS,
 454                 .boot_on = 1,
 455         },
 456         .num_consumer_supplies = ARRAY_SIZE(sabresd_vwm8962_consumers),
 457         .consumer_supplies = sabresd_vwm8962_consumers,
 458 };
 459
 460 static struct fixed_voltage_config sabresd_vwm8962_reg_config = {
 461         .supply_name    = "SPKVDD",
 462         .microvolts             = 4200000,
 463         .gpio                   = SABRESD_CODEC_PWR_EN,
 464         .enable_high    = 1,
 465         .enabled_at_boot = 1,
 466         .init_data              = &sabresd_vwm8962_init,
 467 };
 468
 469 static struct platform_device sabresd_vwm8962_reg_devices = {
 470         .name   = "reg-fixed-voltage",
 471         .id             = 4,
 472         .dev    = {
 473                 .platform_data = &sabresd_vwm8962_reg_config,
 474         },
 475 };
 476
 477 static void mx6q_csi0_cam_powerdown(int powerdown)
 478 {
 479         if (powerdown)
 480                 gpio_set_value(SABRESD_CSI0_PWN, 1);
 481         else
 482                 gpio_set_value(SABRESD_CSI0_PWN, 0);
 483
 484         msleep(2);
 485 }
 486
 487 static void mx6q_csi0_io_init(void)
 488 {
 489         if (cpu_is_mx6q())
 490                 mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_csi0_sensor_pads,
 491                         ARRAY_SIZE(mx6q_sabresd_csi0_sensor_pads));
 492         else if (cpu_is_mx6dl())
 493                 mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_csi0_sensor_pads,
 494                         ARRAY_SIZE(mx6dl_sabresd_csi0_sensor_pads));
 495
 496         /* Camera reset */
 497         gpio_request(SABRESD_CSI0_RST, "cam-reset");
 498         gpio_direction_output(SABRESD_CSI0_RST, 1);
 499
 500         /* Camera power down */
 501         gpio_request(SABRESD_CSI0_PWN, "cam-pwdn");
 502         gpio_direction_output(SABRESD_CSI0_PWN, 1);
 503         msleep(5);
 504         gpio_set_value(SABRESD_CSI0_PWN, 0);
 505         msleep(5);
 506         gpio_set_value(SABRESD_CSI0_RST, 0);
 507         msleep(1);
 508         gpio_set_value(SABRESD_CSI0_RST, 1);
 509         msleep(5);
 510         gpio_set_value(SABRESD_CSI0_PWN, 1);
 511
 512         /* For MX6Q:
 513          * GPR1 bit19 and bit20 meaning:
 514          * Bit19:       0 - Enable mipi to IPU1 CSI0
 515          *                      virtual channel is fixed to 0
 516          *              1 - Enable parallel interface to IPU1 CSI0
 517          * Bit20:       0 - Enable mipi to IPU2 CSI1
 518          *                      virtual channel is fixed to 3
 519          *              1 - Enable parallel interface to IPU2 CSI1
 520          * IPU1 CSI1 directly connect to mipi csi2,
 521          *      virtual channel is fixed to 1
 522          * IPU2 CSI0 directly connect to mipi csi2,
 523          *      virtual channel is fixed to 2
 524          *
 525          * For MX6DL:
 526          * GPR13 bit 0-2 IPU_CSI0_MUX
 527          *   000 MIPI_CSI0
 528          *   100 IPU CSI0
 529          */
 530         if (cpu_is_mx6q())
 531                 mxc_iomux_set_gpr_register(1, 19, 1, 1);
 532         else if (cpu_is_mx6dl())
 533                 mxc_iomux_set_gpr_register(13, 0, 3, 4);
 534 }
 535
 536 static struct fsl_mxc_camera_platform_data camera_data = {
 537         .mclk = 24000000,
 538         .mclk_source = 0,
 539         .csi = 0,
 540         .io_init = mx6q_csi0_io_init,
 541         .pwdn = mx6q_csi0_cam_powerdown,
 542 };
 543
 544 static void mx6q_mipi_powerdown(int powerdown)
 545 {
 546         if (powerdown)
 547                 gpio_set_value(SABRESD_MIPICSI_PWN, 1);
 548         else
 549                 gpio_set_value(SABRESD_MIPICSI_PWN, 0);
 550
 551         msleep(2);
 552 }
 553
 554 static void mx6q_mipi_sensor_io_init(void)
 555 {
 556         if (cpu_is_mx6q())
 557                 mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_mipi_sensor_pads,
 558                         ARRAY_SIZE(mx6q_sabresd_mipi_sensor_pads));
 559         else if (cpu_is_mx6dl())
 560                 mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_mipi_sensor_pads,
 561                         ARRAY_SIZE(mx6dl_sabresd_mipi_sensor_pads));
 562
 563         /* Camera reset */
 564         gpio_request(SABRESD_MIPICSI_RST, "cam-reset");
 565         gpio_direction_output(SABRESD_MIPICSI_RST, 1);
 566
 567         /* Camera power down */
 568         gpio_request(SABRESD_MIPICSI_PWN, "cam-pwdn");
 569         gpio_direction_output(SABRESD_MIPICSI_PWN, 1);
 570         msleep(5);
 571         gpio_set_value(SABRESD_MIPICSI_PWN, 0);
 572         msleep(5);
 573         gpio_set_value(SABRESD_MIPICSI_RST, 0);
 574         msleep(1);
 575         gpio_set_value(SABRESD_MIPICSI_RST, 1);
 576         msleep(5);
 577         gpio_set_value(SABRESD_MIPICSI_PWN, 1);
 578
 579         /*for mx6dl, mipi virtual channel 1 connect to csi 1*/
 580         if (cpu_is_mx6dl())
 581                 mxc_iomux_set_gpr_register(13, 3, 3, 1);
 582 }
 583
 584 static struct fsl_mxc_camera_platform_data mipi_csi2_data = {
 585         .mclk = 24000000,
 586         .mclk_source = 0,
 587         .csi = 1,
 588         .io_init = mx6q_mipi_sensor_io_init,
 589         .pwdn = mx6q_mipi_powerdown,
 590 };
 591
 592 #define mV_to_uV(mV) (mV * 1000)
 593 #define uV_to_mV(uV) (uV / 1000)
 594 #define V_to_uV(V) (mV_to_uV(V * 1000))
 595 #define uV_to_V(uV) (uV_to_mV(uV) / 1000)
 596
 597 static struct regulator_consumer_supply display_consumers[] = {
 598         {
 599                 /* MAX17135 */
 600                 .supply = "DISPLAY",
 601         },
 602 };
 603
 604 static struct regulator_consumer_supply vcom_consumers[] = {
 605         {
 606                 /* MAX17135 */
 607                 .supply = "VCOM",
 608         },
 609 };
 610
 611 static struct regulator_consumer_supply v3p3_consumers[] = {
 612         {
 613                 /* MAX17135 */
 614                 .supply = "V3P3",
 615         },
 616 };
 617
 618 static struct regulator_init_data max17135_init_data[] = {
 619         {
 620                 .constraints = {
 621                         .name = "DISPLAY",
 622                         .valid_ops_mask =  REGULATOR_CHANGE_STATUS,
 623                 },
 624                 .num_consumer_supplies = ARRAY_SIZE(display_consumers),
 625                 .consumer_supplies = display_consumers,
 626         }, {
 627                 .constraints = {
 628                         .name = "GVDD",
 629                         .min_uV = V_to_uV(20),
 630                         .max_uV = V_to_uV(20),
 631                 },
 632         }, {
 633                 .constraints = {
 634                         .name = "GVEE",
 635                         .min_uV = V_to_uV(-22),
 636                         .max_uV = V_to_uV(-22),
 637                 },
 638         }, {
 639                 .constraints = {
 640                         .name = "HVINN",
 641                         .min_uV = V_to_uV(-22),
 642                         .max_uV = V_to_uV(-22),
 643                 },
 644         }, {
 645                 .constraints = {
 646                         .name = "HVINP",
 647                         .min_uV = V_to_uV(20),
 648                         .max_uV = V_to_uV(20),
 649                 },
 650         }, {
 651                 .constraints = {
 652                         .name = "VCOM",
 653                         .min_uV = mV_to_uV(-4325),
 654                         .max_uV = mV_to_uV(-500),
 655                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 656                         REGULATOR_CHANGE_STATUS,
 657                 },
 658                 .num_consumer_supplies = ARRAY_SIZE(vcom_consumers),
 659                 .consumer_supplies = vcom_consumers,
 660         }, {
 661                 .constraints = {
 662                         .name = "VNEG",
 663                         .min_uV = V_to_uV(-15),
 664                         .max_uV = V_to_uV(-15),
 665                 },
 666         }, {
 667                 .constraints = {
 668                         .name = "VPOS",
 669                         .min_uV = V_to_uV(15),
 670                         .max_uV = V_to_uV(15),
 671                 },
 672         }, {
 673                 .constraints = {
 674                         .name = "V3P3",
 675                         .valid_ops_mask =  REGULATOR_CHANGE_STATUS,
 676                 },
 677                 .num_consumer_supplies = ARRAY_SIZE(v3p3_consumers),
 678                 .consumer_supplies = v3p3_consumers,
 679         },
 680 };
 681
 682 static struct platform_device max17135_sensor_device = {
 683         .name = "max17135_sensor",
 684         .id = 0,
 685 };
 686
 687 static struct max17135_platform_data max17135_pdata __initdata = {
 688         .vneg_pwrup = 1,
 689         .gvee_pwrup = 1,
 690         .vpos_pwrup = 2,
 691         .gvdd_pwrup = 1,
 692         .gvdd_pwrdn = 1,
 693         .vpos_pwrdn = 2,
 694         .gvee_pwrdn = 1,
 695         .vneg_pwrdn = 1,
 696         .gpio_pmic_pwrgood = SABRESD_EPDC_PWRSTAT,
 697         .gpio_pmic_vcom_ctrl = SABRESD_EPDC_VCOM,
 698         .gpio_pmic_wakeup = SABRESD_EPDC_PMIC_WAKE,
 699         .gpio_pmic_v3p3 = SABRESD_EPDC_PWRCTRL0,
 700         .gpio_pmic_intr = SABRESD_EPDC_PMIC_INT,
 701         .regulator_init = max17135_init_data,
 702         .init = max17135_regulator_init,
 703 };
 704
 705 static int __init max17135_regulator_init(struct max17135 *max17135)
 706 {
 707         struct max17135_platform_data *pdata = &max17135_pdata;
 708         int i, ret;
 709
 710         if (!epdc_enabled) {
 711                 printk(KERN_DEBUG
 712                         "max17135_regulator_init abort: EPDC not enabled\n");
 713                 return 0;
 714         }
 715
 716         max17135->gvee_pwrup = pdata->gvee_pwrup;
 717         max17135->vneg_pwrup = pdata->vneg_pwrup;
 718         max17135->vpos_pwrup = pdata->vpos_pwrup;
 719         max17135->gvdd_pwrup = pdata->gvdd_pwrup;
 720         max17135->gvdd_pwrdn = pdata->gvdd_pwrdn;
 721         max17135->vpos_pwrdn = pdata->vpos_pwrdn;
 722         max17135->vneg_pwrdn = pdata->vneg_pwrdn;
 723         max17135->gvee_pwrdn = pdata->gvee_pwrdn;
 724
 725         max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup +
 726                 pdata->gvdd_pwrup + pdata->gvee_pwrup;
 727
 728         max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood;
 729         max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl;
 730         max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup;
 731         max17135->gpio_pmic_v3p3 = pdata->gpio_pmic_v3p3;
 732         max17135->gpio_pmic_intr = pdata->gpio_pmic_intr;
 733
 734         gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake");
 735         gpio_direction_output(max17135->gpio_pmic_wakeup, 0);
 736
 737         gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom");
 738         gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0);
 739
 740         gpio_request(max17135->gpio_pmic_v3p3, "epdc-v3p3");
 741         gpio_direction_output(max17135->gpio_pmic_v3p3, 0);
 742
 743         gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int");
 744         gpio_direction_input(max17135->gpio_pmic_intr);
 745
 746         gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat");
 747         gpio_direction_input(max17135->gpio_pmic_pwrgood);
 748
 749         max17135->vcom_setup = false;
 750         max17135->init_done = false;
 751
 752         for (i = 0; i < MAX17135_NUM_REGULATORS; i++) {
 753                 ret = max17135_register_regulator(max17135, i,
 754                         &pdata->regulator_init[i]);
 755                 if (ret != 0) {
 756                         printk(KERN_ERR"max17135 regulator init failed: %d\n",
 757                                 ret);
 758                         return ret;
 759                 }
 760         }
 761
 762         /*
 763          * TODO: We cannot enable full constraints for now, since
 764          * it results in the PFUZE regulators being disabled
 765          * at the end of boot, which disables critical regulators.
 766          */
 767         /*regulator_has_full_constraints();*/
 768
 769         return 0;
 770 }
 771
 772 static struct imxi2c_platform_data mx6q_sabresd_i2c_data = {
 773         .bitrate = 100000,
 774 };
 775
 776 static struct fsl_mxc_lightsensor_platform_data ls_data = {
 777         .rext = 499,    /* calibration: 499K->700K */
 778 };
 779
 780 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 781         {
 782                 I2C_BOARD_INFO("wm89**", 0x1a),
 783         },
 784         {
 785                 I2C_BOARD_INFO("ov5642", 0x3c),
 786                 .platform_data = (void *)&camera_data,
 787         },
 788         {
 789                 I2C_BOARD_INFO("mma8451", 0x1c),
 790                 .platform_data = (void *)&mma8451_position,
 791         },
 792 };
 793
 794 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 795         {
 796                 I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
 797         },
 798         {
 799                 I2C_BOARD_INFO("ov5640_mipi", 0x3c),
 800                 .platform_data = (void *)&mipi_csi2_data,
 801         },
 802         {
 803                 I2C_BOARD_INFO("egalax_ts", 0x4),
 804                 .irq = gpio_to_irq(SABRESD_CAP_TCH_INT0),
 805         },
 806         {
 807                 I2C_BOARD_INFO("max11801", 0x48),
 808                 .platform_data = (void *)&max11801_mode,
 809                 .irq = gpio_to_irq(SABRESD_TS_INT),
 810         },
 811 };
 812
 813 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 814         {
 815                 I2C_BOARD_INFO("max17135", 0x48),
 816                 .platform_data = &max17135_pdata,
 817         },
 818         {
 819                 I2C_BOARD_INFO("egalax_ts", 0x4),
 820                 .irq = gpio_to_irq(SABRESD_CAP_TCH_INT1),
 821         },
 822         {
 823                 I2C_BOARD_INFO("mag3110", 0x0e),
 824                 .irq = gpio_to_irq(SABRESD_eCOMPASS_INT),
 825                 .platform_data = (void *)&mag3110_position,
 826         },
 827         {
 828                 I2C_BOARD_INFO("isl29023", 0x44),
 829                 .irq  = gpio_to_irq(SABRESD_ALS_INT),
 830                 .platform_data = &ls_data,
 831         }, {
 832                 I2C_BOARD_INFO("elan-touch", 0x10),
 833                 .irq = gpio_to_irq(SABRESD_ELAN_INT),
 834         },
 835 };
 836
 837 static int epdc_get_pins(void)
 838 {
 839         int ret = 0;
 840
 841         /* Claim GPIOs for EPDC pins - used during power up/down */
 842         ret |= gpio_request(SABRESD_EPDC_SDDO_0, "epdc_d0");
 843         ret |= gpio_request(SABRESD_EPDC_SDDO_1, "epdc_d1");
 844         ret |= gpio_request(SABRESD_EPDC_SDDO_2, "epdc_d2");
 845         ret |= gpio_request(SABRESD_EPDC_SDDO_3, "epdc_d3");
 846         ret |= gpio_request(SABRESD_EPDC_SDDO_4, "epdc_d4");
 847         ret |= gpio_request(SABRESD_EPDC_SDDO_5, "epdc_d5");
 848         ret |= gpio_request(SABRESD_EPDC_SDDO_6, "epdc_d6");
 849         ret |= gpio_request(SABRESD_EPDC_SDDO_7, "epdc_d7");
 850         ret |= gpio_request(SABRESD_EPDC_GDCLK, "epdc_gdclk");
 851         ret |= gpio_request(SABRESD_EPDC_GDSP, "epdc_gdsp");
 852         ret |= gpio_request(SABRESD_EPDC_GDOE, "epdc_gdoe");
 853         ret |= gpio_request(SABRESD_EPDC_GDRL, "epdc_gdrl");
 854         ret |= gpio_request(SABRESD_EPDC_SDCLK, "epdc_sdclk");
 855         ret |= gpio_request(SABRESD_EPDC_SDOE, "epdc_sdoe");
 856         ret |= gpio_request(SABRESD_EPDC_SDLE, "epdc_sdle");
 857         ret |= gpio_request(SABRESD_EPDC_SDSHR, "epdc_sdshr");
 858         ret |= gpio_request(SABRESD_EPDC_BDR0, "epdc_bdr0");
 859         ret |= gpio_request(SABRESD_EPDC_SDCE0, "epdc_sdce0");
 860         ret |= gpio_request(SABRESD_EPDC_SDCE1, "epdc_sdce1");
 861         ret |= gpio_request(SABRESD_EPDC_SDCE2, "epdc_sdce2");
 862
 863         return ret;
 864 }
 865
 866 static void epdc_put_pins(void)
 867 {
 868         gpio_free(SABRESD_EPDC_SDDO_0);
 869         gpio_free(SABRESD_EPDC_SDDO_1);
 870         gpio_free(SABRESD_EPDC_SDDO_2);
 871         gpio_free(SABRESD_EPDC_SDDO_3);
 872         gpio_free(SABRESD_EPDC_SDDO_4);
 873         gpio_free(SABRESD_EPDC_SDDO_5);
 874         gpio_free(SABRESD_EPDC_SDDO_6);
 875         gpio_free(SABRESD_EPDC_SDDO_7);
 876         gpio_free(SABRESD_EPDC_GDCLK);
 877         gpio_free(SABRESD_EPDC_GDSP);
 878         gpio_free(SABRESD_EPDC_GDOE);
 879         gpio_free(SABRESD_EPDC_GDRL);
 880         gpio_free(SABRESD_EPDC_SDCLK);
 881         gpio_free(SABRESD_EPDC_SDOE);
 882         gpio_free(SABRESD_EPDC_SDLE);
 883         gpio_free(SABRESD_EPDC_SDSHR);
 884         gpio_free(SABRESD_EPDC_BDR0);
 885         gpio_free(SABRESD_EPDC_SDCE0);
 886         gpio_free(SABRESD_EPDC_SDCE1);
 887         gpio_free(SABRESD_EPDC_SDCE2);
 888 }
 889
 890 static void epdc_enable_pins(void)
 891 {
 892         /* Configure MUX settings to enable EPDC use */
 893         mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_epdc_enable_pads, \
 894                                 ARRAY_SIZE(mx6dl_sabresd_epdc_enable_pads));
 895
 896         gpio_direction_input(SABRESD_EPDC_SDDO_0);
 897         gpio_direction_input(SABRESD_EPDC_SDDO_1);
 898         gpio_direction_input(SABRESD_EPDC_SDDO_2);
 899         gpio_direction_input(SABRESD_EPDC_SDDO_3);
 900         gpio_direction_input(SABRESD_EPDC_SDDO_4);
 901         gpio_direction_input(SABRESD_EPDC_SDDO_5);
 902         gpio_direction_input(SABRESD_EPDC_SDDO_6);
 903         gpio_direction_input(SABRESD_EPDC_SDDO_7);
 904         gpio_direction_input(SABRESD_EPDC_GDCLK);
 905         gpio_direction_input(SABRESD_EPDC_GDSP);
 906         gpio_direction_input(SABRESD_EPDC_GDOE);
 907         gpio_direction_input(SABRESD_EPDC_GDRL);
 908         gpio_direction_input(SABRESD_EPDC_SDCLK);
 909         gpio_direction_input(SABRESD_EPDC_SDOE);
 910         gpio_direction_input(SABRESD_EPDC_SDLE);
 911         gpio_direction_input(SABRESD_EPDC_SDSHR);
 912         gpio_direction_input(SABRESD_EPDC_BDR0);
 913         gpio_direction_input(SABRESD_EPDC_SDCE0);
 914         gpio_direction_input(SABRESD_EPDC_SDCE1);
 915         gpio_direction_input(SABRESD_EPDC_SDCE2);
 916 }
 917
 918 static void epdc_disable_pins(void)
 919 {
 920         /* Configure MUX settings for EPDC pins to
 921          * GPIO and drive to 0. */
 922         mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_epdc_disable_pads, \
 923                                 ARRAY_SIZE(mx6dl_sabresd_epdc_disable_pads));
 924
 925         gpio_direction_output(SABRESD_EPDC_SDDO_0, 0);
 926         gpio_direction_output(SABRESD_EPDC_SDDO_1, 0);
 927         gpio_direction_output(SABRESD_EPDC_SDDO_2, 0);
 928         gpio_direction_output(SABRESD_EPDC_SDDO_3, 0);
 929         gpio_direction_output(SABRESD_EPDC_SDDO_4, 0);
 930         gpio_direction_output(SABRESD_EPDC_SDDO_5, 0);
 931         gpio_direction_output(SABRESD_EPDC_SDDO_6, 0);
 932         gpio_direction_output(SABRESD_EPDC_SDDO_7, 0);
 933         gpio_direction_output(SABRESD_EPDC_GDCLK, 0);
 934         gpio_direction_output(SABRESD_EPDC_GDSP, 0);
 935         gpio_direction_output(SABRESD_EPDC_GDOE, 0);
 936         gpio_direction_output(SABRESD_EPDC_GDRL, 0);
 937         gpio_direction_output(SABRESD_EPDC_SDCLK, 0);
 938         gpio_direction_output(SABRESD_EPDC_SDOE, 0);
 939         gpio_direction_output(SABRESD_EPDC_SDLE, 0);
 940         gpio_direction_output(SABRESD_EPDC_SDSHR, 0);
 941         gpio_direction_output(SABRESD_EPDC_BDR0, 0);
 942         gpio_direction_output(SABRESD_EPDC_SDCE0, 0);
 943         gpio_direction_output(SABRESD_EPDC_SDCE1, 0);
 944         gpio_direction_output(SABRESD_EPDC_SDCE2, 0);
 945 }
 946
 947 static struct fb_videomode e60_v110_mode = {
 948         .name = "E60_V110",
 949         .refresh = 50,
 950         .xres = 800,
 951         .yres = 600,
 952         .pixclock = 18604700,
 953         .left_margin = 8,
 954         .right_margin = 178,
 955         .upper_margin = 4,
 956         .lower_margin = 10,
 957         .hsync_len = 20,
 958         .vsync_len = 4,
 959         .sync = 0,
 960         .vmode = FB_VMODE_NONINTERLACED,
 961         .flag = 0,
 962 };
 963 static struct fb_videomode e60_v220_mode = {
 964         .name = "E60_V220",
 965         .refresh = 85,
 966         .xres = 800,
 967         .yres = 600,
 968         .pixclock = 30000000,
 969         .left_margin = 8,
 970         .right_margin = 164,
 971         .upper_margin = 4,
 972         .lower_margin = 8,
 973         .hsync_len = 4,
 974         .vsync_len = 1,
 975         .sync = 0,
 976         .vmode = FB_VMODE_NONINTERLACED,
 977         .flag = 0,
 978         .refresh = 85,
 979         .xres = 800,
 980         .yres = 600,
 981 };
 982 static struct fb_videomode e060scm_mode = {
 983         .name = "E060SCM",
 984         .refresh = 85,
 985         .xres = 800,
 986         .yres = 600,
 987         .pixclock = 26666667,
 988         .left_margin = 8,
 989         .right_margin = 100,
 990         .upper_margin = 4,
 991         .lower_margin = 8,
 992         .hsync_len = 4,
 993         .vsync_len = 1,
 994         .sync = 0,
 995         .vmode = FB_VMODE_NONINTERLACED,
 996         .flag = 0,
 997 };
 998 static struct fb_videomode e97_v110_mode = {
 999         .name = "E97_V110",
1000         .refresh = 50,
1001         .xres = 1200,
1002         .yres = 825,
1003         .pixclock = 32000000,
1004         .left_margin = 12,
1005         .right_margin = 128,
1006         .upper_margin = 4,
1007         .lower_margin = 10,
1008         .hsync_len = 20,
1009         .vsync_len = 4,
1010         .sync = 0,
1011         .vmode = FB_VMODE_NONINTERLACED,
1012         .flag = 0,
1013 };
1014
1015 static struct imx_epdc_fb_mode panel_modes[] = {
1016         {
1017                 &e60_v110_mode,
1018                 4,      /* vscan_holdoff */
1019                 10,     /* sdoed_width */
1020                 20,     /* sdoed_delay */
1021                 10,     /* sdoez_width */
1022                 20,     /* sdoez_delay */
1023                 428,    /* gdclk_hp_offs */
1024                 20,     /* gdsp_offs */
1025                 0,      /* gdoe_offs */
1026                 1,      /* gdclk_offs */
1027                 1,      /* num_ce */
1028         },
1029         {
1030                 &e60_v220_mode,
1031                 4,      /* vscan_holdoff */
1032                 10,     /* sdoed_width */
1033                 20,     /* sdoed_delay */
1034                 10,     /* sdoez_width */
1035                 20,     /* sdoez_delay */
1036                 465,    /* gdclk_hp_offs */
1037                 20,     /* gdsp_offs */
1038                 0,      /* gdoe_offs */
1039                 9,      /* gdclk_offs */
1040                 1,      /* num_ce */
1041         },
1042         {
1043                 &e060scm_mode,
1044                 4,      /* vscan_holdoff */
1045                 10,     /* sdoed_width */
1046                 20,     /* sdoed_delay */
1047                 10,     /* sdoez_width */
1048                 20,     /* sdoez_delay */
1049                 419,    /* gdclk_hp_offs */
1050                 20,     /* gdsp_offs */
1051                 0,      /* gdoe_offs */
1052                 5,      /* gdclk_offs */
1053                 1,      /* num_ce */
1054         },
1055         {
1056                 &e97_v110_mode,
1057                 8,      /* vscan_holdoff */
1058                 10,     /* sdoed_width */
1059                 20,     /* sdoed_delay */
1060                 10,     /* sdoez_width */
1061                 20,     /* sdoez_delay */
1062                 632,    /* gdclk_hp_offs */
1063                 20,     /* gdsp_offs */
1064                 0,      /* gdoe_offs */
1065                 1,      /* gdclk_offs */
1066                 3,      /* num_ce */
1067         }
1068 };
1069
1070 static struct imx_epdc_fb_platform_data epdc_data = {
1071         .epdc_mode = panel_modes,
1072         .num_modes = ARRAY_SIZE(panel_modes),
1073         .get_pins = epdc_get_pins,
1074         .put_pins = epdc_put_pins,
1075         .enable_pins = epdc_enable_pins,
1076         .disable_pins = epdc_disable_pins,
1077 };
1078
1079 static void imx6q_sabresd_usbotg_vbus(bool on)
1080 {
1081         if (on)
1082                 gpio_set_value(SABRESD_USB_OTG_PWR, 1);
1083         else
1084                 gpio_set_value(SABRESD_USB_OTG_PWR, 0);
1085 }
1086
1087 static void __init imx6q_sabresd_init_usb(void)
1088 {
1089         int ret = 0;
1090
1091         imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
1092         /* disable external charger detect,
1093          * or it will affect signal quality at dp .
1094          */
1095         ret = gpio_request(SABRESD_USB_OTG_PWR, "usb-pwr");
1096         if (ret) {
1097                 pr_err("failed to get GPIO SABRESD_USB_OTG_PWR: %d\n",
1098                         ret);
1099                 return;
1100         }
1101         gpio_direction_output(SABRESD_USB_OTG_PWR, 0);
1102         /* keep USB host1 VBUS always on */
1103         ret = gpio_request(SABRESD_USB_H1_PWR, "usb-h1-pwr");
1104         if (ret) {
1105                 pr_err("failed to get GPIO SABRESD_USB_H1_PWR: %d\n",
1106                         ret);
1107                 return;
1108         }
1109         gpio_direction_output(SABRESD_USB_H1_PWR, 1);
1110         if (board_is_mx6_reva())
1111                 mxc_iomux_set_gpr_register(1, 13, 1, 1);
1112         else
1113                 mxc_iomux_set_gpr_register(1, 13, 1, 0);
1114
1115         mx6_set_otghost_vbus_func(imx6q_sabresd_usbotg_vbus);
1116
1117 }
1118
1119 /* HW Initialization, if return 0, initialization is successful. */
1120 static int mx6q_sabresd_sata_init(struct device *dev, void __iomem *addr)
1121 {
1122         u32 tmpdata;
1123         int ret = 0;
1124         struct clk *clk;
1125
1126         sata_clk = clk_get(dev, "imx_sata_clk");
1127         if (IS_ERR(sata_clk)) {
1128                 dev_err(dev, "no sata clock.\n");
1129                 return PTR_ERR(sata_clk);
1130         }
1131         ret = clk_enable(sata_clk);
1132         if (ret) {
1133                 dev_err(dev, "can't enable sata clock.\n");
1134                 goto put_sata_clk;
1135         }
1136
1137         /* Set PHY Paremeters, two steps to configure the GPR13,
1138          * one write for rest of parameters, mask of first write is 0x07FFFFFD,
1139          * and the other one write for setting the mpll_clk_off_b
1140          *.rx_eq_val_0(iomuxc_gpr13[26:24]),
1141          *.los_lvl(iomuxc_gpr13[23:19]),
1142          *.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
1143          *.sata_speed(iomuxc_gpr13[15]),
1144          *.mpll_ss_en(iomuxc_gpr13[14]),
1145          *.tx_atten_0(iomuxc_gpr13[13:11]),
1146          *.tx_boost_0(iomuxc_gpr13[10:7]),
1147          *.tx_lvl(iomuxc_gpr13[6:2]),
1148          *.mpll_ck_off(iomuxc_gpr13[1]),
1149          *.tx_edgerate_0(iomuxc_gpr13[0]),
1150          */
1151         tmpdata = readl(IOMUXC_GPR13);
1152         writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
1153
1154         /* enable SATA_PHY PLL */
1155         tmpdata = readl(IOMUXC_GPR13);
1156         writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
1157
1158         /* Get the AHB clock rate, and configure the TIMER1MS reg later */
1159         clk = clk_get(NULL, "ahb");
1160         if (IS_ERR(clk)) {
1161                 dev_err(dev, "no ahb clock.\n");
1162                 ret = PTR_ERR(clk);
1163                 goto release_sata_clk;
1164         }
1165         tmpdata = clk_get_rate(clk) / 1000;
1166         clk_put(clk);
1167
1168 #ifdef CONFIG_SATA_AHCI_PLATFORM
1169         ret = sata_init(addr, tmpdata);
1170         if (ret == 0)
1171                 return ret;
1172 #else
1173         usleep_range(1000, 2000);
1174         /* AHCI PHY enter into PDDQ mode if the AHCI module is not enabled */
1175         tmpdata = readl(addr + PORT_PHY_CTL);
1176         writel(tmpdata | PORT_PHY_CTL_PDDQ_LOC, addr + PORT_PHY_CTL);
1177         pr_info("No AHCI save PWR: PDDQ %s\n", ((readl(addr + PORT_PHY_CTL)
1178                                         >> 20) & 1) ? "enabled" : "disabled");
1179 #endif
1180
1181 release_sata_clk:
1182         /* disable SATA_PHY PLL */
1183         writel((readl(IOMUXC_GPR13) & ~0x2), IOMUXC_GPR13);
1184         clk_disable(sata_clk);
1185 put_sata_clk:
1186         clk_put(sata_clk);
1187
1188         return ret;
1189 }
1190
1191 #ifdef CONFIG_SATA_AHCI_PLATFORM
1192 static void mx6q_sabresd_sata_exit(struct device *dev)
1193 {
1194         clk_disable(sata_clk);
1195         clk_put(sata_clk);
1196 }
1197
1198 static struct ahci_platform_data mx6q_sabresd_sata_data = {
1199         .init = mx6q_sabresd_sata_init,
1200         .exit = mx6q_sabresd_sata_exit,
1201 };
1202 #endif
1203
1204 static void mx6q_sabresd_flexcan0_switch(int enable)
1205 {
1206         if (enable) {
1207                 gpio_set_value(SABRESD_CAN1_STBY, 1);
1208         } else {
1209                 gpio_set_value(SABRESD_CAN1_STBY, 0);
1210         }
1211 }
1212
1213 static const struct flexcan_platform_data
1214         mx6q_sabresd_flexcan0_pdata __initconst = {
1215         .transceiver_switch = mx6q_sabresd_flexcan0_switch,
1216 };
1217
1218 static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
1219         .reserved_mem_size = SZ_128M,
1220 };
1221
1222 static struct imx_asrc_platform_data imx_asrc_data = {
1223         .channel_bits = 4,
1224         .clk_map_ver = 2,
1225 };
1226
1227 static void mx6_reset_mipi_dsi(void)
1228 {
1229         gpio_set_value(SABRESD_DISP_PWR_EN, 1);
1230         gpio_set_value(SABRESD_DISP_RST_B, 1);
1231         udelay(10);
1232         gpio_set_value(SABRESD_DISP_RST_B, 0);
1233         udelay(50);
1234         gpio_set_value(SABRESD_DISP_RST_B, 1);
1235
1236         /*
1237          * it needs to delay 120ms minimum for reset complete
1238          */
1239         msleep(120);
1240 }
1241
1242 static struct mipi_dsi_platform_data mipi_dsi_pdata = {
1243         .ipu_id         = 0,
1244         .disp_id        = 1,
1245         .lcd_panel      = "TRULY-WVGA",
1246         .reset          = mx6_reset_mipi_dsi,
1247 };
1248
1249 static struct ipuv3_fb_platform_data sabresd_fb_data[] = {
1250         { /*fb0*/
1251         .disp_dev = "ldb",
1252         .interface_pix_fmt = IPU_PIX_FMT_RGB666,
1253         .mode_str = "LDB-XGA",
1254         .default_bpp = 16,
1255         .int_clk = false,
1256         .late_init = false,
1257         }, {
1258         .disp_dev = "ldb",
1259         .interface_pix_fmt = IPU_PIX_FMT_RGB666,
1260         .mode_str = "LDB-XGA",
1261         .default_bpp = 16,
1262         .int_clk = false,
1263         }, {
1264         .disp_dev = "lcd",
1265         .interface_pix_fmt = IPU_PIX_FMT_RGB565,
1266         .mode_str = "CLAA-WVGA",
1267         .default_bpp = 16,
1268         .int_clk = false,
1269         .late_init = false,
1270         }, {
1271         .disp_dev = "ldb",
1272         .interface_pix_fmt = IPU_PIX_FMT_RGB666,
1273         .mode_str = "LDB-VGA",
1274         .default_bpp = 16,
1275         .int_clk = false,
1276         .late_init = false,
1277         },
1278 };
1279
1280 static void hdmi_init(int ipu_id, int disp_id)
1281 {
1282         int hdmi_mux_setting;
1283
1284         if ((ipu_id > 1) || (ipu_id < 0)) {
1285                 pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
1286                 ipu_id = 0;
1287         }
1288
1289         if ((disp_id > 1) || (disp_id < 0)) {
1290                 pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
1291                 disp_id = 0;
1292         }
1293
1294         /* Configure the connection between IPU1/2 and HDMI */
1295         hdmi_mux_setting = 2*ipu_id + disp_id;
1296
1297         /* GPR3, bits 2-3 = HDMI_MUX_CTL */
1298         mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
1299
1300         /* Set HDMI event as SDMA event2 while Chip version later than TO1.2 */
1301         if (hdmi_SDMA_check())
1302                 mxc_iomux_set_gpr_register(0, 0, 1, 1);
1303 }
1304
1305 /* On mx6x sabresd board i2c2 iomux with hdmi ddc,
1306  * the pins default work at i2c2 function,
1307  when hdcp enable, the pins should work at ddc function */
1308
1309 static void hdmi_enable_ddc_pin(void)
1310 {
1311         if (cpu_is_mx6dl())
1312                 mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_hdmi_ddc_pads,
1313                         ARRAY_SIZE(mx6dl_sabresd_hdmi_ddc_pads));
1314         else
1315                 mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_hdmi_ddc_pads,
1316                         ARRAY_SIZE(mx6q_sabresd_hdmi_ddc_pads));
1317 }
1318
1319 static void hdmi_disable_ddc_pin(void)
1320 {
1321         if (cpu_is_mx6dl())
1322                 mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_i2c2_pads,
1323                         ARRAY_SIZE(mx6dl_sabresd_i2c2_pads));
1324         else
1325                 mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_i2c2_pads,
1326                         ARRAY_SIZE(mx6q_sabresd_i2c2_pads));
1327 }
1328
1329 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
1330         .init = hdmi_init,
1331         .enable_pins = hdmi_enable_ddc_pin,
1332         .disable_pins = hdmi_disable_ddc_pin,
1333 };
1334
1335 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
1336         .ipu_id = 0,
1337         .disp_id = 0,
1338 };
1339
1340 static struct fsl_mxc_lcd_platform_data lcdif_data = {
1341         .ipu_id = 0,
1342         .disp_id = 0,
1343         .default_ifmt = IPU_PIX_FMT_RGB565,
1344 };
1345
1346 static struct fsl_mxc_ldb_platform_data ldb_data = {
1347         .ipu_id = 1,
1348         .disp_id = 0,
1349         .ext_ref = 1,
1350         .mode = LDB_SEP0,
1351         .sec_ipu_id = 1,
1352         .sec_disp_id = 1,
1353 };
1354
1355 static struct max8903_pdata charger1_data = {
1356         .dok = SABRESD_CHARGE_DOK_B,
1357         .uok = SABRESD_CHARGE_UOK_B,
1358         .chg = SABRESD_CHARGE_CHG_1_B,
1359         .flt = SABRESD_CHARGE_FLT_1_B,
1360         .dcm_always_high = true,
1361         .dc_valid = true,
1362         .usb_valid = true,
1363 };
1364
1365 static struct platform_device sabresd_max8903_charger_1 = {
1366         .name   = "max8903-charger",
1367         .id     = 1,
1368         .dev    = {
1369                 .platform_data = &charger1_data,
1370         },
1371 };
1372
1373 static struct imx_ipuv3_platform_data ipu_data[] = {
1374         {
1375         .rev = 4,
1376         .csi_clk[0] = "clko_clk",
1377         .bypass_reset = false,
1378         }, {
1379         .rev = 4,
1380         .csi_clk[0] = "clko_clk",
1381         .bypass_reset = false,
1382         },
1383 };
1384
1385 static struct fsl_mxc_capture_platform_data capture_data[] = {
1386         {
1387                 .csi = 0,
1388                 .ipu = 0,
1389                 .mclk_source = 0,
1390                 .is_mipi = 0,
1391         }, {
1392                 .csi = 1,
1393                 .ipu = 0,
1394                 .mclk_source = 0,
1395                 .is_mipi = 1,
1396         },
1397 };
1398
1399
1400 static void sabresd_suspend_enter(void)
1401 {
1402         /* suspend preparation */
1403         /* Disable AUX 5V */
1404         gpio_set_value(SABRESD_AUX_5V_EN, 0);
1405 }
1406
1407 static void sabresd_suspend_exit(void)
1408 {
1409         /* resume restore */
1410         /* Enable AUX 5V */
1411         gpio_set_value(SABRESD_AUX_5V_EN, 1);
1412 }
1413 static const struct pm_platform_data mx6q_sabresd_pm_data __initconst = {
1414         .name = "imx_pm",
1415         .suspend_enter = sabresd_suspend_enter,
1416         .suspend_exit = sabresd_suspend_exit,
1417 };
1418
1419 static struct regulator_consumer_supply sabresd_vmmc_consumers[] = {
1420         REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
1421         REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
1422         REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
1423 };
1424
1425 static struct regulator_init_data sabresd_vmmc_init = {
1426         .num_consumer_supplies = ARRAY_SIZE(sabresd_vmmc_consumers),
1427         .consumer_supplies = sabresd_vmmc_consumers,
1428 };
1429
1430 static struct fixed_voltage_config sabresd_vmmc_reg_config = {
1431         .supply_name            = "vmmc",
1432         .microvolts             = 3300000,
1433         .gpio                   = -1,
1434         .init_data              = &sabresd_vmmc_init,
1435 };
1436
1437 static struct platform_device sabresd_vmmc_reg_devices = {
1438         .name   = "reg-fixed-voltage",
1439         .id     = 3,
1440         .dev    = {
1441                 .platform_data = &sabresd_vmmc_reg_config,
1442         },
1443 };
1444
1445 static int __init imx6q_init_audio(void)
1446 {
1447         if (board_is_mx6_reva()) {
1448                 mxc_register_device(&mx6_sabresd_audio_wm8958_device,
1449                                     &wm8958_data);
1450                 imx6q_add_imx_ssi(1, &mx6_sabresd_ssi_pdata);
1451
1452                 mxc_wm8958_init();
1453         } else {
1454                 platform_device_register(&sabresd_vwm8962_reg_devices);
1455                 mxc_register_device(&mx6_sabresd_audio_wm8962_device,
1456                                     &wm8962_data);
1457                 imx6q_add_imx_ssi(1, &mx6_sabresd_ssi_pdata);
1458
1459                 mxc_wm8962_init();
1460         }
1461
1462         return 0;
1463 }
1464
1465 #ifndef CONFIG_IMX_PCIE
1466 static void pcie_3v3_power(void)
1467 {
1468         /* disable PCIE_3V3 first */
1469         gpio_request(SABRESD_PCIE_PWR_EN, "pcie_3v3_en");
1470         gpio_direction_output(SABRESD_PCIE_PWR_EN, 0);
1471         mdelay(10);
1472         /* enable PCIE_3V3 again */
1473         gpio_set_value(SABRESD_PCIE_PWR_EN, 1);
1474         gpio_free(SABRESD_PCIE_PWR_EN);
1475 }
1476
1477 static void pcie_3v3_reset(void)
1478 {
1479         /* reset miniPCIe */
1480         gpio_request(SABRESD_PCIE_RST_B_REVB, "pcie_reset_rebB");
1481         gpio_direction_output(SABRESD_PCIE_RST_B_REVB, 0);
1482         /* The PCI Express Mini CEM specification states that PREST# is
1483         deasserted minimum 1ms after 3.3vVaux has been applied and stable*/
1484         mdelay(1);
1485         gpio_set_value(SABRESD_PCIE_RST_B_REVB, 1);
1486         gpio_free(SABRESD_PCIE_RST_B_REVB);
1487 }
1488 #endif
1489
1490 static void gps_power_on(bool on)
1491 {
1492         /* Enable/disable aux_3v15 */
1493         gpio_request(SABRESD_AUX_3V15_EN, "aux_3v15_en");
1494         gpio_direction_output(SABRESD_AUX_3V15_EN, 1);
1495         gpio_set_value(SABRESD_AUX_3V15_EN, on);
1496         gpio_free(SABRESD_AUX_3V15_EN);
1497         /*Enable/disable gps_en*/
1498         gpio_request(SABRESD_GPS_EN, "gps_en");
1499         gpio_direction_output(SABRESD_GPS_EN, 1);
1500         gpio_set_value(SABRESD_GPS_EN, on);
1501         gpio_free(SABRESD_GPS_EN);
1502
1503 }
1504
1505 #if defined(CONFIG_LEDS_TRIGGER) || defined(CONFIG_LEDS_GPIO)
1506
1507 #define GPIO_LED(gpio_led, name_led, act_low, state_suspend, trigger)   \
1508 {                                                                       \
1509         .gpio                   = gpio_led,                             \
1510         .name                   = name_led,                             \
1511         .active_low             = act_low,                              \
1512         .retain_state_suspended = state_suspend,                        \
1513         .default_state          = 0,                                    \
1514         .default_trigger        = "max8903-"trigger,            \
1515 }
1516
1517 /* use to show a external power source is connected
1518  * GPIO_LED(SABRESD_CHARGE_DONE, "chg_detect", 0, 1, "ac-online"),
1519  */
1520 static struct gpio_led imx6q_gpio_leds[] = {
1521         GPIO_LED(SABRESD_CHARGE_NOW, "chg_now_led", 0, 1,
1522                 "charger-charging"),
1523 /* For the latest B4 board, this GPIO_1 is connected to POR_B,
1524 which will reset the whole board if this pin's level is changed,
1525 so, for the latest board, we have to avoid using this pin as
1526 GPIO.
1527         GPIO_LED(SABRESD_CHARGE_DONE, "chg_done_led", 0, 1,
1528                         "charger-full"),
1529 */
1530 };
1531
1532 static struct gpio_led_platform_data imx6q_gpio_leds_data = {
1533         .leds           = imx6q_gpio_leds,
1534         .num_leds       = ARRAY_SIZE(imx6q_gpio_leds),
1535 };
1536
1537 static struct platform_device imx6q_gpio_led_device = {
1538         .name           = "leds-gpio",
1539         .id             = -1,
1540         .num_resources  = 0,
1541         .dev            = {
1542                 .platform_data = &imx6q_gpio_leds_data,
1543         }
1544 };
1545
1546 static void __init imx6q_add_device_gpio_leds(void)
1547 {
1548         platform_device_register(&imx6q_gpio_led_device);
1549 }
1550 #else
1551 static void __init imx6q_add_device_gpio_leds(void) {}
1552 #endif
1553
1554 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
1555 #define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake, debounce)  \
1556 {                                                               \
1557         .gpio           = gpio_num,                             \
1558         .type           = EV_KEY,                               \
1559         .code           = ev_code,                              \
1560         .active_low     = act_low,                              \
1561         .desc           = "btn " descr,                         \
1562         .wakeup         = wake,                                 \
1563         .debounce_interval = debounce,                          \
1564 }
1565
1566 static struct gpio_keys_button imx6q_buttons[] = {
1567         GPIO_BUTTON(SABRESD_VOLUME_UP, KEY_VOLUMEUP, 1, "volume-up", 0, 1),
1568         GPIO_BUTTON(SABRESD_VOLUME_DN, KEY_VOLUMEDOWN, 1, "volume-down", 0, 1),
1569         GPIO_BUTTON(SABRESD_POWER_OFF, KEY_POWER, 1, "power", 1, 1),
1570 };
1571
1572 static struct gpio_keys_platform_data imx6q_button_data = {
1573         .buttons        = imx6q_buttons,
1574         .nbuttons       = ARRAY_SIZE(imx6q_buttons),
1575 };
1576
1577 static struct platform_device imx6q_button_device = {
1578         .name           = "gpio-keys",
1579         .id             = -1,
1580         .num_resources  = 0,
1581         .dev            = {
1582                 .platform_data = &imx6q_button_data,
1583         }
1584 };
1585
1586 static void __init imx6q_add_device_buttons(void)
1587 {
1588         platform_device_register(&imx6q_button_device);
1589 }
1590 #else
1591 static void __init imx6q_add_device_buttons(void) {}
1592 #endif
1593
1594 static struct platform_pwm_backlight_data mx6_sabresd_pwm_backlight_data = {
1595         .pwm_id = 0,
1596         .max_brightness = 248,
1597         .dft_brightness = 128,
1598         .pwm_period_ns = 50000,
1599 };
1600
1601 static struct mxc_dvfs_platform_data sabresd_dvfscore_data = {
1602         .reg_id = "VDDCORE",
1603         .soc_id = "VDDSOC",
1604         .clk1_id = "cpu_clk",
1605         .clk2_id = "gpc_dvfs_clk",
1606         .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
1607         .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
1608         .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
1609         .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
1610         .prediv_mask = 0x1F800,
1611         .prediv_offset = 11,
1612         .prediv_val = 3,
1613         .div3ck_mask = 0xE0000000,
1614         .div3ck_offset = 29,
1615         .div3ck_val = 2,
1616         .emac_val = 0x08,
1617         .upthr_val = 25,
1618         .dnthr_val = 9,
1619         .pncthr_val = 33,
1620         .upcnt_val = 10,
1621         .dncnt_val = 10,
1622         .delay_time = 80,
1623 };
1624
1625 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
1626                                    char **cmdline, struct meminfo *mi)
1627 {
1628 }
1629
1630 static struct mipi_csi2_platform_data mipi_csi2_pdata = {
1631         .ipu_id  = 0,
1632         .csi_id = 1,
1633         .v_channel = 0,
1634         .lanes = 2,
1635         .dphy_clk = "mipi_pllref_clk",
1636         .pixel_clk = "emi_clk",
1637 };
1638
1639 static int __init caam_setup(char *__unused)
1640 {
1641         caam_enabled = 1;
1642         return 1;
1643 }
1644 early_param("caam", caam_setup);
1645
1646 #define SNVS_LPCR 0x38
1647 static void mx6_snvs_poweroff(void)
1648 {
1649
1650         void __iomem *mx6_snvs_base =  MX6_IO_ADDRESS(MX6Q_SNVS_BASE_ADDR);
1651         u32 value;
1652         value = readl(mx6_snvs_base + SNVS_LPCR);
1653         /*set TOP and DP_EN bit*/
1654         writel(value | 0x60, mx6_snvs_base + SNVS_LPCR);
1655 }
1656
1657 static const struct imx_pcie_platform_data mx6_sabresd_pcie_data __initconst = {
1658         .pcie_pwr_en    = SABRESD_PCIE_PWR_EN,
1659         .pcie_rst       = SABRESD_PCIE_RST_B_REVB,
1660         .pcie_wake_up   = SABRESD_PCIE_WAKE_B,
1661         .pcie_dis       = SABRESD_PCIE_DIS_B,
1662 };
1663
1664 static int __init early_enable_lcd_ldb(char *p)
1665 {
1666         enable_lcd_ldb = 1;
1667         return 0;
1668 }
1669 early_param("enable_lcd_ldb", early_enable_lcd_ldb);
1670
1671 /*!
1672  * Board specific initialization.
1673  */
1674 static void __init mx6_sabresd_board_init(void)
1675 {
1676         int i;
1677         int ret;
1678         struct clk *clko, *clko2;
1679         struct clk *new_parent;
1680         int rate;
1681
1682         if (cpu_is_mx6q())
1683                 mxc_iomux_v3_setup_multiple_pads(mx6q_sabresd_pads,
1684                         ARRAY_SIZE(mx6q_sabresd_pads));
1685         else if (cpu_is_mx6dl()) {
1686                 mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_pads,
1687                         ARRAY_SIZE(mx6dl_sabresd_pads));
1688         }
1689
1690 #ifdef CONFIG_FEC_1588
1691         /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
1692          * For MX6 GPR1 bit21 meaning:
1693          * Bit21:       0 - GPIO_16 pad output
1694          *              1 - GPIO_16 pad input
1695          */
1696          mxc_iomux_set_gpr_register(1, 21, 1, 1);
1697 #endif
1698
1699         gp_reg_id = sabresd_dvfscore_data.reg_id;
1700         soc_reg_id = sabresd_dvfscore_data.soc_id;
1701         mx6q_sabresd_init_uart();
1702
1703         /*
1704          * MX6DL/Solo only supports single IPU
1705          * The following codes are used to change ipu id
1706          * and display id information for MX6DL/Solo. Then
1707          * register 1 IPU device and up to 2 displays for
1708          * MX6DL/Solo
1709          */
1710         if (cpu_is_mx6dl()) {
1711                 ldb_data.ipu_id = 0;
1712                 ldb_data.disp_id = 0;
1713                 ldb_data.sec_ipu_id = 0;
1714                 ldb_data.sec_disp_id = 1;
1715                 hdmi_core_data.disp_id = 1;
1716                 mipi_dsi_pdata.ipu_id = 0;
1717                 mipi_dsi_pdata.disp_id = 1;
1718                 if (enable_lcd_ldb) {
1719                         ldb_data.disp_id = 1;
1720                         ldb_data.mode = LDB_SIN1;
1721                 }
1722         }
1723         imx6q_add_mxc_hdmi_core(&hdmi_core_data);
1724
1725         imx6q_add_ipuv3(0, &ipu_data[0]);
1726         if (cpu_is_mx6q()) {
1727                 imx6q_add_ipuv3(1, &ipu_data[1]);
1728                 for (i = 0; i < 4 && i < ARRAY_SIZE(sabresd_fb_data); i++)
1729                         imx6q_add_ipuv3fb(i, &sabresd_fb_data[i]);
1730         } else
1731                 for (i = 0; i < 2 && i < ARRAY_SIZE(sabresd_fb_data); i++)
1732                         imx6q_add_ipuv3fb(i, &sabresd_fb_data[i]);
1733
1734         imx6q_add_vdoa();
1735         imx6q_add_mipi_dsi(&mipi_dsi_pdata);
1736         imx6q_add_lcdif(&lcdif_data);
1737         imx6q_add_ldb(&ldb_data);
1738         imx6q_add_v4l2_output(0);
1739         imx6q_add_v4l2_capture(0, &capture_data[0]);
1740         imx6q_add_v4l2_capture(1, &capture_data[1]);
1741         imx6q_add_mipi_csi2(&mipi_csi2_pdata);
1742         imx6q_add_imx_snvs_rtc();
1743
1744         if (1 == caam_enabled)
1745                 imx6q_add_imx_caam();
1746
1747         if (board_is_mx6_reva()) {
1748                 strcpy(mxc_i2c0_board_info[0].type, "wm8958");
1749                 mxc_i2c0_board_info[0].platform_data = &wm8958_config_data;
1750         } else {
1751                 strcpy(mxc_i2c0_board_info[0].type, "wm8962");
1752                 mxc_i2c0_board_info[0].platform_data = &wm8962_config_data;
1753         }
1754         imx6q_add_device_gpio_leds();
1755
1756         imx6q_add_imx_i2c(0, &mx6q_sabresd_i2c_data);
1757         imx6q_add_imx_i2c(1, &mx6q_sabresd_i2c_data);
1758         imx6q_add_imx_i2c(2, &mx6q_sabresd_i2c_data);
1759         i2c_register_board_info(0, mxc_i2c0_board_info,
1760                         ARRAY_SIZE(mxc_i2c0_board_info));
1761         i2c_register_board_info(1, mxc_i2c1_board_info,
1762                         ARRAY_SIZE(mxc_i2c1_board_info));
1763         i2c_register_board_info(2, mxc_i2c2_board_info,
1764                         ARRAY_SIZE(mxc_i2c2_board_info));
1765         ret = gpio_request(SABRESD_PFUZE_INT, "pFUZE-int");
1766         if (ret) {
1767                 printk(KERN_ERR"request pFUZE-int error!!\n");
1768                 return;
1769         } else {
1770                 gpio_direction_input(SABRESD_PFUZE_INT);
1771                 mx6q_sabresd_init_pfuze100(SABRESD_PFUZE_INT);
1772         }
1773         /* SPI */
1774         imx6q_add_ecspi(0, &mx6q_sabresd_spi_data);
1775         spi_device_init();
1776
1777         imx6q_add_mxc_hdmi(&hdmi_data);
1778
1779         imx6q_add_anatop_thermal_imx(1, &mx6q_sabresd_anatop_thermal_data);
1780         imx6_init_fec(fec_data);
1781         imx6q_add_pm_imx(0, &mx6q_sabresd_pm_data);
1782
1783         /* Move sd4 to first because sd4 connect to emmc.
1784            Mfgtools want emmc is mmcblk0 and other sd card is mmcblk1.
1785         */
1786         imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabresd_sd4_data);
1787         imx6q_add_sdhci_usdhc_imx(1, &mx6q_sabresd_sd2_data);
1788         imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabresd_sd3_data);
1789         imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
1790         imx6q_sabresd_init_usb();
1791         /* SATA is not supported by MX6DL/Solo */
1792         if (cpu_is_mx6q()) {
1793 #ifdef CONFIG_SATA_AHCI_PLATFORM
1794                 imx6q_add_ahci(0, &mx6q_sabresd_sata_data);
1795 #else
1796                 mx6q_sabresd_sata_init(NULL,
1797                         (void __iomem *)ioremap(MX6Q_SATA_BASE_ADDR, SZ_4K));
1798 #endif
1799         }
1800         imx6q_add_vpu();
1801         imx6q_init_audio();
1802         platform_device_register(&sabresd_vmmc_reg_devices);
1803         imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
1804         imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
1805         imx6q_add_asrc(&imx_asrc_data);
1806
1807         /*
1808          * Disable HannStar touch panel CABC function,
1809          * this function turns the panel's backlight automatically
1810          * according to the content shown on the panel which
1811          * may cause annoying unstable backlight issue.
1812          */
1813         gpio_request(SABRESD_CABC_EN0, "cabc-en0");
1814         gpio_direction_output(SABRESD_CABC_EN0, 0);
1815         gpio_request(SABRESD_CABC_EN1, "cabc-en1");
1816         gpio_direction_output(SABRESD_CABC_EN1, 0);
1817
1818         imx6q_add_mxc_pwm(0);
1819         imx6q_add_mxc_pwm(1);
1820         imx6q_add_mxc_pwm(2);
1821         imx6q_add_mxc_pwm(3);
1822         imx6q_add_mxc_pwm_backlight(0, &mx6_sabresd_pwm_backlight_data);
1823
1824         imx6q_add_otp();
1825         imx6q_add_viim();
1826         imx6q_add_imx2_wdt(0, NULL);
1827         imx6q_add_dma();
1828
1829         imx6q_add_dvfs_core(&sabresd_dvfscore_data);
1830         imx6q_add_device_buttons();
1831
1832         /* enable sensor 3v3 and 1v8 */
1833         gpio_request(SABRESD_SENSOR_EN, "sensor-en");
1834         gpio_direction_output(SABRESD_SENSOR_EN, 1);
1835
1836         /* enable ecompass intr */
1837         gpio_request(SABRESD_eCOMPASS_INT, "ecompass-int");
1838         gpio_direction_input(SABRESD_eCOMPASS_INT);
1839         /* enable light sensor intr */
1840         gpio_request(SABRESD_ALS_INT, "als-int");
1841         gpio_direction_input(SABRESD_ALS_INT);
1842
1843         imx6q_add_hdmi_soc();
1844         imx6q_add_hdmi_soc_dai();
1845
1846         if (cpu_is_mx6dl()) {
1847                 imx6dl_add_imx_pxp();
1848                 imx6dl_add_imx_pxp_client();
1849                 if (epdc_enabled) {
1850                         mxc_register_device(&max17135_sensor_device, NULL);
1851                         imx6dl_add_imx_epdc(&epdc_data);
1852                 }
1853         }
1854         /*
1855         ret = gpio_request_array(mx6q_sabresd_flexcan_gpios,
1856                         ARRAY_SIZE(mx6q_sabresd_flexcan_gpios));
1857         if (ret)
1858                 pr_err("failed to request flexcan1-gpios: %d\n", ret);
1859         else
1860                 imx6q_add_flexcan0(&mx6q_sabresd_flexcan0_pdata);
1861         */
1862
1863         clko2 = clk_get(NULL, "clko2_clk");
1864         if (IS_ERR(clko2))
1865                 pr_err("can't get CLKO2 clock.\n");
1866
1867         new_parent = clk_get(NULL, "osc_clk");
1868         if (!IS_ERR(new_parent)) {
1869                 clk_set_parent(clko2, new_parent);
1870                 clk_put(new_parent);
1871         }
1872         rate = clk_round_rate(clko2, 24000000);
1873         clk_set_rate(clko2, rate);
1874         clk_enable(clko2);
1875
1876         /* Camera and audio use osc clock */
1877         clko = clk_get(NULL, "clko_clk");
1878         if (!IS_ERR(clko))
1879                 clk_set_parent(clko, clko2);
1880
1881         /* Enable Aux_5V */
1882         gpio_request(SABRESD_AUX_5V_EN, "aux_5v_en");
1883         gpio_direction_output(SABRESD_AUX_5V_EN, 1);
1884         gpio_set_value(SABRESD_AUX_5V_EN, 1);
1885
1886 #ifndef CONFIG_IMX_PCIE
1887         /* enable pcie 3v3 power without pcie driver */
1888         pcie_3v3_power();
1889         mdelay(10);
1890         pcie_3v3_reset();
1891 #endif
1892
1893         gps_power_on(true);
1894         /* Register charger chips */
1895         platform_device_register(&sabresd_max8903_charger_1);
1896         pm_power_off = mx6_snvs_poweroff;
1897         imx6q_add_busfreq();
1898
1899         /* Add PCIe RC interface support */
1900         imx6q_add_pcie(&mx6_sabresd_pcie_data);
1901         if (cpu_is_mx6dl()) {
1902                 mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_elan_pads,
1903                                                 ARRAY_SIZE(mx6dl_arm2_elan_pads));
1904
1905                 /* ELAN Touchscreen */
1906                 gpio_request(SABRESD_ELAN_INT, "elan-interrupt");
1907                 gpio_direction_input(SABRESD_ELAN_INT);
1908
1909                 gpio_request(SABRESD_ELAN_CE, "elan-cs");
1910                 gpio_direction_output(SABRESD_ELAN_CE, 1);
1911                 gpio_direction_output(SABRESD_ELAN_CE, 0);
1912
1913                 gpio_request(SABRESD_ELAN_RST, "elan-rst");
1914                 gpio_direction_output(SABRESD_ELAN_RST, 1);
1915                 gpio_direction_output(SABRESD_ELAN_RST, 0);
1916                 mdelay(1);
1917                 gpio_direction_output(SABRESD_ELAN_RST, 1);
1918                 gpio_direction_output(SABRESD_ELAN_CE, 1);
1919         }
1920
1921         imx6_add_armpmu();
1922         imx6q_add_perfmon(0);
1923         imx6q_add_perfmon(1);
1924         imx6q_add_perfmon(2);
1925 }
1926
1927 extern void __iomem *twd_base;
1928 static void __init mx6_sabresd_timer_init(void)
1929 {
1930         struct clk *uart_clk;
1931 #ifdef CONFIG_LOCAL_TIMERS
1932         twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
1933         BUG_ON(!twd_base);
1934 #endif
1935         mx6_clocks_init(32768, 24000000, 0, 0);
1936
1937         uart_clk = clk_get_sys("imx-uart.0", NULL);
1938         early_console_setup(UART1_BASE_ADDR, uart_clk);
1939 }
1940
1941 static struct sys_timer mx6_sabresd_timer = {
1942         .init   = mx6_sabresd_timer_init,
1943 };
1944
1945 static void __init mx6q_sabresd_reserve(void)
1946 {
1947 #if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE)
1948         phys_addr_t phys;
1949
1950         if (imx6q_gpu_pdata.reserved_mem_size) {
1951                 phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
1952                                            SZ_4K, SZ_1G);
1953                 memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
1954                 imx6q_gpu_pdata.reserved_mem_base = phys;
1955         }
1956 #endif
1957 }
1958
1959 /*
1960  * initialize __mach_desc_MX6Q_SABRESD data structure.
1961  */
1962 MACHINE_START(MX6Q_SABRESD, "Freescale i.MX 6Quad/DualLite/Solo Sabre-SD Board")
1963         /* Maintainer: Freescale Semiconductor, Inc. */
1964         .boot_params = MX6_PHYS_OFFSET + 0x100,
1965         .fixup = fixup_mxc_board,
1966         .map_io = mx6_map_io,
1967         .init_irq = mx6_init_irq,
1968         .init_machine = mx6_sabresd_board_init,
1969         .timer = &mx6_sabresd_timer,
1970         .reserve = mx6q_sabresd_reserve,
1971 MACHINE_END