arch/arm/mach-omap1/clock_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock_data.c
   3  *
   4  *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * To do:
  13  * - Clocks that are only available on some chips should be marked with the
  14  *   chips that they are present on.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/delay.h>
  21
  22 #include <asm/mach-types.h>  /* for machine_is_* */
  23
  24 #include <plat/clock.h>
  25 #include <plat/cpu.h>
  26 #include <plat/clkdev_omap.h>
  27 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
  28 #include <plat/usb.h>   /* for OTG_BASE */
  29
  30 #include "iomap.h"
  31 #include "clock.h"
  32
  33 /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
  34 #define IDL_CLKOUT_ARM_SHIFT                    12
  35 #define IDLTIM_ARM_SHIFT                        9
  36 #define IDLAPI_ARM_SHIFT                        8
  37 #define IDLIF_ARM_SHIFT                         6
  38 #define IDLLB_ARM_SHIFT                         4       /* undocumented? */
  39 #define OMAP1510_IDLLCD_ARM_SHIFT               3       /* undocumented? */
  40 #define IDLPER_ARM_SHIFT                        2
  41 #define IDLXORP_ARM_SHIFT                       1
  42 #define IDLWDT_ARM_SHIFT                        0
  43
  44 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
  45 #define CONF_MOD_UART3_CLK_MODE_R               31
  46 #define CONF_MOD_UART2_CLK_MODE_R               30
  47 #define CONF_MOD_UART1_CLK_MODE_R               29
  48 #define CONF_MOD_MMC_SD_CLK_REQ_R               23
  49 #define CONF_MOD_MCBSP3_AUXON                   20
  50
  51 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
  52 #define CONF_MOD_SOSSI_CLK_EN_R                 16
  53
  54 /* Some OTG_SYSCON_2-specific bit fields */
  55 #define OTG_SYSCON_2_UHOST_EN_SHIFT             8
  56
  57 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
  58 #define SOFT_MMC2_DPLL_REQ_SHIFT        13
  59 #define SOFT_MMC_DPLL_REQ_SHIFT         12
  60 #define SOFT_UART3_DPLL_REQ_SHIFT       11
  61 #define SOFT_UART2_DPLL_REQ_SHIFT       10
  62 #define SOFT_UART1_DPLL_REQ_SHIFT       9
  63 #define SOFT_USB_OTG_DPLL_REQ_SHIFT     8
  64 #define SOFT_CAM_DPLL_REQ_SHIFT         7
  65 #define SOFT_COM_MCKO_REQ_SHIFT         6
  66 #define SOFT_PERIPH_REQ_SHIFT           5       /* sys_ck gate for UART2 ? */
  67 #define USB_REQ_EN_SHIFT                4
  68 #define SOFT_USB_REQ_SHIFT              3       /* sys_ck gate for USB host? */
  69 #define SOFT_SDW_REQ_SHIFT              2       /* sys_ck gate for Bluetooth? */
  70 #define SOFT_COM_REQ_SHIFT              1       /* sys_ck gate for com proc? */
  71 #define SOFT_DPLL_REQ_SHIFT             0
  72
  73 /*
  74  * Omap1 clocks
  75  */
  76
  77 static struct clk ck_ref = {
  78         .name           = "ck_ref",
  79         .ops            = &clkops_null,
  80         .rate           = 12000000,
  81 };
  82
  83 static struct clk ck_dpll1 = {
  84         .name           = "ck_dpll1",
  85         .ops            = &clkops_null,
  86         .parent         = &ck_ref,
  87 };
  88
  89 /*
  90  * FIXME: This clock seems to be necessary but no-one has asked for its
  91  * activation.  [ FIX: SoSSI, SSR ]
  92  */
  93 static struct arm_idlect1_clk ck_dpll1out = {
  94         .clk = {
  95                 .name           = "ck_dpll1out",
  96                 .ops            = &clkops_generic,
  97                 .parent         = &ck_dpll1,
  98                 .flags          = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
  99                                   ENABLE_ON_INIT,
 100                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 101                 .enable_bit     = EN_CKOUT_ARM,
 102                 .recalc         = &followparent_recalc,
 103         },
 104         .idlect_shift   = IDL_CLKOUT_ARM_SHIFT,
 105 };
 106
 107 static struct clk sossi_ck = {
 108         .name           = "ck_sossi",
 109         .ops            = &clkops_generic,
 110         .parent         = &ck_dpll1out.clk,
 111         .flags          = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
 112         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
 113         .enable_bit     = CONF_MOD_SOSSI_CLK_EN_R,
 114         .recalc         = &omap1_sossi_recalc,
 115         .set_rate       = &omap1_set_sossi_rate,
 116 };
 117
 118 static struct clk arm_ck = {
 119         .name           = "arm_ck",
 120         .ops            = &clkops_null,
 121         .parent         = &ck_dpll1,
 122         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 123         .recalc         = &omap1_ckctl_recalc,
 124         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 125         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 126 };
 127
 128 static struct arm_idlect1_clk armper_ck = {
 129         .clk = {
 130                 .name           = "armper_ck",
 131                 .ops            = &clkops_generic,
 132                 .parent         = &ck_dpll1,
 133                 .flags          = CLOCK_IDLE_CONTROL,
 134                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 135                 .enable_bit     = EN_PERCK,
 136                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 137                 .recalc         = &omap1_ckctl_recalc,
 138                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 139                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 140         },
 141         .idlect_shift   = IDLPER_ARM_SHIFT,
 142 };
 143
 144 /*
 145  * FIXME: This clock seems to be necessary but no-one has asked for its
 146  * activation.  [ GPIO code for 1510 ]
 147  */
 148 static struct clk arm_gpio_ck = {
 149         .name           = "ick",
 150         .ops            = &clkops_generic,
 151         .parent         = &ck_dpll1,
 152         .flags          = ENABLE_ON_INIT,
 153         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 154         .enable_bit     = EN_GPIOCK,
 155         .recalc         = &followparent_recalc,
 156 };
 157
 158 static struct arm_idlect1_clk armxor_ck = {
 159         .clk = {
 160                 .name           = "armxor_ck",
 161                 .ops            = &clkops_generic,
 162                 .parent         = &ck_ref,
 163                 .flags          = CLOCK_IDLE_CONTROL,
 164                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 165                 .enable_bit     = EN_XORPCK,
 166                 .recalc         = &followparent_recalc,
 167         },
 168         .idlect_shift   = IDLXORP_ARM_SHIFT,
 169 };
 170
 171 static struct arm_idlect1_clk armtim_ck = {
 172         .clk = {
 173                 .name           = "armtim_ck",
 174                 .ops            = &clkops_generic,
 175                 .parent         = &ck_ref,
 176                 .flags          = CLOCK_IDLE_CONTROL,
 177                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 178                 .enable_bit     = EN_TIMCK,
 179                 .recalc         = &followparent_recalc,
 180         },
 181         .idlect_shift   = IDLTIM_ARM_SHIFT,
 182 };
 183
 184 static struct arm_idlect1_clk armwdt_ck = {
 185         .clk = {
 186                 .name           = "armwdt_ck",
 187                 .ops            = &clkops_generic,
 188                 .parent         = &ck_ref,
 189                 .flags          = CLOCK_IDLE_CONTROL,
 190                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 191                 .enable_bit     = EN_WDTCK,
 192                 .fixed_div      = 14,
 193                 .recalc         = &omap_fixed_divisor_recalc,
 194         },
 195         .idlect_shift   = IDLWDT_ARM_SHIFT,
 196 };
 197
 198 static struct clk arminth_ck16xx = {
 199         .name           = "arminth_ck",
 200         .ops            = &clkops_null,
 201         .parent         = &arm_ck,
 202         .recalc         = &followparent_recalc,
 203         /* Note: On 16xx the frequency can be divided by 2 by programming
 204          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 205          *
 206          * 1510 version is in TC clocks.
 207          */
 208 };
 209
 210 static struct clk dsp_ck = {
 211         .name           = "dsp_ck",
 212         .ops            = &clkops_generic,
 213         .parent         = &ck_dpll1,
 214         .enable_reg     = OMAP1_IO_ADDRESS(ARM_CKCTL),
 215         .enable_bit     = EN_DSPCK,
 216         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 217         .recalc         = &omap1_ckctl_recalc,
 218         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 219         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 220 };
 221
 222 static struct clk dspmmu_ck = {
 223         .name           = "dspmmu_ck",
 224         .ops            = &clkops_null,
 225         .parent         = &ck_dpll1,
 226         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 227         .recalc         = &omap1_ckctl_recalc,
 228         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 229         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 230 };
 231
 232 static struct clk dspper_ck = {
 233         .name           = "dspper_ck",
 234         .ops            = &clkops_dspck,
 235         .parent         = &ck_dpll1,
 236         .enable_reg     = DSP_IDLECT2,
 237         .enable_bit     = EN_PERCK,
 238         .rate_offset    = CKCTL_PERDIV_OFFSET,
 239         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 240         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 241         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 242 };
 243
 244 static struct clk dspxor_ck = {
 245         .name           = "dspxor_ck",
 246         .ops            = &clkops_dspck,
 247         .parent         = &ck_ref,
 248         .enable_reg     = DSP_IDLECT2,
 249         .enable_bit     = EN_XORPCK,
 250         .recalc         = &followparent_recalc,
 251 };
 252
 253 static struct clk dsptim_ck = {
 254         .name           = "dsptim_ck",
 255         .ops            = &clkops_dspck,
 256         .parent         = &ck_ref,
 257         .enable_reg     = DSP_IDLECT2,
 258         .enable_bit     = EN_DSPTIMCK,
 259         .recalc         = &followparent_recalc,
 260 };
 261
 262 static struct arm_idlect1_clk tc_ck = {
 263         .clk = {
 264                 .name           = "tc_ck",
 265                 .ops            = &clkops_null,
 266                 .parent         = &ck_dpll1,
 267                 .flags          = CLOCK_IDLE_CONTROL,
 268                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 269                 .recalc         = &omap1_ckctl_recalc,
 270                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 271                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 272         },
 273         .idlect_shift   = IDLIF_ARM_SHIFT,
 274 };
 275
 276 static struct clk arminth_ck1510 = {
 277         .name           = "arminth_ck",
 278         .ops            = &clkops_null,
 279         .parent         = &tc_ck.clk,
 280         .recalc         = &followparent_recalc,
 281         /* Note: On 1510 the frequency follows TC_CK
 282          *
 283          * 16xx version is in MPU clocks.
 284          */
 285 };
 286
 287 static struct clk tipb_ck = {
 288         /* No-idle controlled by "tc_ck" */
 289         .name           = "tipb_ck",
 290         .ops            = &clkops_null,
 291         .parent         = &tc_ck.clk,
 292         .recalc         = &followparent_recalc,
 293 };
 294
 295 static struct clk l3_ocpi_ck = {
 296         /* No-idle controlled by "tc_ck" */
 297         .name           = "l3_ocpi_ck",
 298         .ops            = &clkops_generic,
 299         .parent         = &tc_ck.clk,
 300         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 301         .enable_bit     = EN_OCPI_CK,
 302         .recalc         = &followparent_recalc,
 303 };
 304
 305 static struct clk tc1_ck = {
 306         .name           = "tc1_ck",
 307         .ops            = &clkops_generic,
 308         .parent         = &tc_ck.clk,
 309         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 310         .enable_bit     = EN_TC1_CK,
 311         .recalc         = &followparent_recalc,
 312 };
 313
 314 /*
 315  * FIXME: This clock seems to be necessary but no-one has asked for its
 316  * activation.  [ pm.c (SRAM), CCP, Camera ]
 317  */
 318 static struct clk tc2_ck = {
 319         .name           = "tc2_ck",
 320         .ops            = &clkops_generic,
 321         .parent         = &tc_ck.clk,
 322         .flags          = ENABLE_ON_INIT,
 323         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT3),
 324         .enable_bit     = EN_TC2_CK,
 325         .recalc         = &followparent_recalc,
 326 };
 327
 328 static struct clk dma_ck = {
 329         /* No-idle controlled by "tc_ck" */
 330         .name           = "dma_ck",
 331         .ops            = &clkops_null,
 332         .parent         = &tc_ck.clk,
 333         .recalc         = &followparent_recalc,
 334 };
 335
 336 static struct clk dma_lcdfree_ck = {
 337         .name           = "dma_lcdfree_ck",
 338         .ops            = &clkops_null,
 339         .parent         = &tc_ck.clk,
 340         .recalc         = &followparent_recalc,
 341 };
 342
 343 static struct arm_idlect1_clk api_ck = {
 344         .clk = {
 345                 .name           = "api_ck",
 346                 .ops            = &clkops_generic,
 347                 .parent         = &tc_ck.clk,
 348                 .flags          = CLOCK_IDLE_CONTROL,
 349                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 350                 .enable_bit     = EN_APICK,
 351                 .recalc         = &followparent_recalc,
 352         },
 353         .idlect_shift   = IDLAPI_ARM_SHIFT,
 354 };
 355
 356 static struct arm_idlect1_clk lb_ck = {
 357         .clk = {
 358                 .name           = "lb_ck",
 359                 .ops            = &clkops_generic,
 360                 .parent         = &tc_ck.clk,
 361                 .flags          = CLOCK_IDLE_CONTROL,
 362                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 363                 .enable_bit     = EN_LBCK,
 364                 .recalc         = &followparent_recalc,
 365         },
 366         .idlect_shift   = IDLLB_ARM_SHIFT,
 367 };
 368
 369 static struct clk rhea1_ck = {
 370         .name           = "rhea1_ck",
 371         .ops            = &clkops_null,
 372         .parent         = &tc_ck.clk,
 373         .recalc         = &followparent_recalc,
 374 };
 375
 376 static struct clk rhea2_ck = {
 377         .name           = "rhea2_ck",
 378         .ops            = &clkops_null,
 379         .parent         = &tc_ck.clk,
 380         .recalc         = &followparent_recalc,
 381 };
 382
 383 static struct clk lcd_ck_16xx = {
 384         .name           = "lcd_ck",
 385         .ops            = &clkops_generic,
 386         .parent         = &ck_dpll1,
 387         .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 388         .enable_bit     = EN_LCDCK,
 389         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 390         .recalc         = &omap1_ckctl_recalc,
 391         .round_rate     = omap1_clk_round_rate_ckctl_arm,
 392         .set_rate       = omap1_clk_set_rate_ckctl_arm,
 393 };
 394
 395 static struct arm_idlect1_clk lcd_ck_1510 = {
 396         .clk = {
 397                 .name           = "lcd_ck",
 398                 .ops            = &clkops_generic,
 399                 .parent         = &ck_dpll1,
 400                 .flags          = CLOCK_IDLE_CONTROL,
 401                 .enable_reg     = OMAP1_IO_ADDRESS(ARM_IDLECT2),
 402                 .enable_bit     = EN_LCDCK,
 403                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 404                 .recalc         = &omap1_ckctl_recalc,
 405                 .round_rate     = omap1_clk_round_rate_ckctl_arm,
 406                 .set_rate       = omap1_clk_set_rate_ckctl_arm,
 407         },
 408         .idlect_shift   = OMAP1510_IDLLCD_ARM_SHIFT,
 409 };
 410
 411 /*
 412  * XXX The enable_bit here is misused - it simply switches between 12MHz
 413  * and 48MHz.  Reimplement with clksel.
 414  *
 415  * XXX does this need SYSC register handling?
 416  */
 417 static struct clk uart1_1510 = {
 418         .name           = "uart1_ck",
 419         .ops            = &clkops_null,
 420         /* Direct from ULPD, no real parent */
 421         .parent         = &armper_ck.clk,
 422         .rate           = 12000000,
 423         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 424         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 425         .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
 426         .set_rate       = &omap1_set_uart_rate,
 427         .recalc         = &omap1_uart_recalc,
 428 };
 429
 430 /*
 431  * XXX The enable_bit here is misused - it simply switches between 12MHz
 432  * and 48MHz.  Reimplement with clksel.
 433  *
 434  * XXX SYSC register handling does not belong in the clock framework
 435  */
 436 static struct uart_clk uart1_16xx = {
 437         .clk    = {
 438                 .name           = "uart1_ck",
 439                 .ops            = &clkops_uart_16xx,
 440                 /* Direct from ULPD, no real parent */
 441                 .parent         = &armper_ck.clk,
 442                 .rate           = 48000000,
 443                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 444                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 445                 .enable_bit     = CONF_MOD_UART1_CLK_MODE_R,
 446         },
 447         .sysc_addr      = 0xfffb0054,
 448 };
 449
 450 /*
 451  * XXX The enable_bit here is misused - it simply switches between 12MHz
 452  * and 48MHz.  Reimplement with clksel.
 453  *
 454  * XXX does this need SYSC register handling?
 455  */
 456 static struct clk uart2_ck = {
 457         .name           = "uart2_ck",
 458         .ops            = &clkops_null,
 459         /* Direct from ULPD, no real parent */
 460         .parent         = &armper_ck.clk,
 461         .rate           = 12000000,
 462         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 463         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 464         .enable_bit     = CONF_MOD_UART2_CLK_MODE_R,
 465         .set_rate       = &omap1_set_uart_rate,
 466         .recalc         = &omap1_uart_recalc,
 467 };
 468
 469 /*
 470  * XXX The enable_bit here is misused - it simply switches between 12MHz
 471  * and 48MHz.  Reimplement with clksel.
 472  *
 473  * XXX does this need SYSC register handling?
 474  */
 475 static struct clk uart3_1510 = {
 476         .name           = "uart3_ck",
 477         .ops            = &clkops_null,
 478         /* Direct from ULPD, no real parent */
 479         .parent         = &armper_ck.clk,
 480         .rate           = 12000000,
 481         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 482         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 483         .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
 484         .set_rate       = &omap1_set_uart_rate,
 485         .recalc         = &omap1_uart_recalc,
 486 };
 487
 488 /*
 489  * XXX The enable_bit here is misused - it simply switches between 12MHz
 490  * and 48MHz.  Reimplement with clksel.
 491  *
 492  * XXX SYSC register handling does not belong in the clock framework
 493  */
 494 static struct uart_clk uart3_16xx = {
 495         .clk    = {
 496                 .name           = "uart3_ck",
 497                 .ops            = &clkops_uart_16xx,
 498                 /* Direct from ULPD, no real parent */
 499                 .parent         = &armper_ck.clk,
 500                 .rate           = 48000000,
 501                 .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 502                 .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 503                 .enable_bit     = CONF_MOD_UART3_CLK_MODE_R,
 504         },
 505         .sysc_addr      = 0xfffb9854,
 506 };
 507
 508 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 509         .name           = "usb_clko",
 510         .ops            = &clkops_generic,
 511         /* Direct from ULPD, no parent */
 512         .rate           = 6000000,
 513         .flags          = ENABLE_REG_32BIT,
 514         .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
 515         .enable_bit     = USB_MCLK_EN_BIT,
 516 };
 517
 518 static struct clk usb_hhc_ck1510 = {
 519         .name           = "usb_hhc_ck",
 520         .ops            = &clkops_generic,
 521         /* Direct from ULPD, no parent */
 522         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 523         .flags          = ENABLE_REG_32BIT,
 524         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 525         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 526 };
 527
 528 static struct clk usb_hhc_ck16xx = {
 529         .name           = "usb_hhc_ck",
 530         .ops            = &clkops_generic,
 531         /* Direct from ULPD, no parent */
 532         .rate           = 48000000,
 533         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 534         .flags          = ENABLE_REG_32BIT,
 535         .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
 536         .enable_bit     = OTG_SYSCON_2_UHOST_EN_SHIFT
 537 };
 538
 539 static struct clk usb_dc_ck = {
 540         .name           = "usb_dc_ck",
 541         .ops            = &clkops_generic,
 542         /* Direct from ULPD, no parent */
 543         .rate           = 48000000,
 544         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 545         .enable_bit     = USB_REQ_EN_SHIFT,
 546 };
 547
 548 static struct clk usb_dc_ck7xx = {
 549         .name           = "usb_dc_ck",
 550         .ops            = &clkops_generic,
 551         /* Direct from ULPD, no parent */
 552         .rate           = 48000000,
 553         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 554         .enable_bit     = SOFT_USB_OTG_DPLL_REQ_SHIFT,
 555 };
 556
 557 static struct clk uart1_7xx = {
 558         .name           = "uart1_ck",
 559         .ops            = &clkops_generic,
 560         /* Direct from ULPD, no parent */
 561         .rate           = 12000000,
 562         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 563         .enable_bit     = 9,
 564 };
 565
 566 static struct clk uart2_7xx = {
 567         .name           = "uart2_ck",
 568         .ops            = &clkops_generic,
 569         /* Direct from ULPD, no parent */
 570         .rate           = 12000000,
 571         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 572         .enable_bit     = 11,
 573 };
 574
 575 static struct clk mclk_1510 = {
 576         .name           = "mclk",
 577         .ops            = &clkops_generic,
 578         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 579         .rate           = 12000000,
 580         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 581         .enable_bit     = SOFT_COM_MCKO_REQ_SHIFT,
 582 };
 583
 584 static struct clk mclk_16xx = {
 585         .name           = "mclk",
 586         .ops            = &clkops_generic,
 587         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 588         .enable_reg     = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
 589         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 590         .set_rate       = &omap1_set_ext_clk_rate,
 591         .round_rate     = &omap1_round_ext_clk_rate,
 592         .init           = &omap1_init_ext_clk,
 593 };
 594
 595 static struct clk bclk_1510 = {
 596         .name           = "bclk",
 597         .ops            = &clkops_generic,
 598         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 599         .rate           = 12000000,
 600 };
 601
 602 static struct clk bclk_16xx = {
 603         .name           = "bclk",
 604         .ops            = &clkops_generic,
 605         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 606         .enable_reg     = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
 607         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 608         .set_rate       = &omap1_set_ext_clk_rate,
 609         .round_rate     = &omap1_round_ext_clk_rate,
 610         .init           = &omap1_init_ext_clk,
 611 };
 612
 613 static struct clk mmc1_ck = {
 614         .name           = "mmc1_ck",
 615         .ops            = &clkops_generic,
 616         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 617         .parent         = &armper_ck.clk,
 618         .rate           = 48000000,
 619         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 620         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 621         .enable_bit     = CONF_MOD_MMC_SD_CLK_REQ_R,
 622 };
 623
 624 /*
 625  * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
 626  * CONF_MOD_MCBSP3_AUXON ??
 627  */
 628 static struct clk mmc2_ck = {
 629         .name           = "mmc2_ck",
 630         .ops            = &clkops_generic,
 631         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 632         .parent         = &armper_ck.clk,
 633         .rate           = 48000000,
 634         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 635         .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
 636         .enable_bit     = 20,
 637 };
 638
 639 static struct clk mmc3_ck = {
 640         .name           = "mmc3_ck",
 641         .ops            = &clkops_generic,
 642         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 643         .parent         = &armper_ck.clk,
 644         .rate           = 48000000,
 645         .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 646         .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
 647         .enable_bit     = SOFT_MMC_DPLL_REQ_SHIFT,
 648 };
 649
 650 static struct clk virtual_ck_mpu = {
 651         .name           = "mpu",
 652         .ops            = &clkops_null,
 653         .parent         = &arm_ck, /* Is smarter alias for */
 654         .recalc         = &followparent_recalc,
 655         .set_rate       = &omap1_select_table_rate,
 656         .round_rate     = &omap1_round_to_table_rate,
 657 };
 658
 659 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 660 remains active during MPU idle whenever this is enabled */
 661 static struct clk i2c_fck = {
 662         .name           = "i2c_fck",
 663         .ops            = &clkops_null,
 664         .flags          = CLOCK_NO_IDLE_PARENT,
 665         .parent         = &armxor_ck.clk,
 666         .recalc         = &followparent_recalc,
 667 };
 668
 669 static struct clk i2c_ick = {
 670         .name           = "i2c_ick",
 671         .ops            = &clkops_null,
 672         .flags          = CLOCK_NO_IDLE_PARENT,
 673         .parent         = &armper_ck.clk,
 674         .recalc         = &followparent_recalc,
 675 };
 676
 677 /*
 678  * clkdev integration
 679  */
 680
 681 static struct omap_clk omap_clks[] = {
 682         /* non-ULPD clocks */
 683         CLK(NULL,       "ck_ref",       &ck_ref,        CK_16XX | CK_1510 | CK_310 | CK_7XX),
 684         CLK(NULL,       "ck_dpll1",     &ck_dpll1,      CK_16XX | CK_1510 | CK_310 | CK_7XX),
 685         /* CK_GEN1 clocks */
 686         CLK(NULL,       "ck_dpll1out",  &ck_dpll1out.clk, CK_16XX),
 687         CLK(NULL,       "ck_sossi",     &sossi_ck,      CK_16XX),
 688         CLK(NULL,       "arm_ck",       &arm_ck,        CK_16XX | CK_1510 | CK_310),
 689         CLK(NULL,       "armper_ck",    &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 690         CLK("omap_gpio.0", "ick",       &arm_gpio_ck,   CK_1510 | CK_310),
 691         CLK(NULL,       "armxor_ck",    &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 692         CLK(NULL,       "armtim_ck",    &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
 693         CLK("omap_wdt", "fck",          &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
 694         CLK("omap_wdt", "ick",          &armper_ck.clk, CK_16XX),
 695         CLK("omap_wdt", "ick",          &dummy_ck,      CK_1510 | CK_310),
 696         CLK(NULL,       "arminth_ck",   &arminth_ck1510, CK_1510 | CK_310),
 697         CLK(NULL,       "arminth_ck",   &arminth_ck16xx, CK_16XX),
 698         /* CK_GEN2 clocks */
 699         CLK(NULL,       "dsp_ck",       &dsp_ck,        CK_16XX | CK_1510 | CK_310),
 700         CLK(NULL,       "dspmmu_ck",    &dspmmu_ck,     CK_16XX | CK_1510 | CK_310),
 701         CLK(NULL,       "dspper_ck",    &dspper_ck,     CK_16XX | CK_1510 | CK_310),
 702         CLK(NULL,       "dspxor_ck",    &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 703         CLK(NULL,       "dsptim_ck",    &dsptim_ck,     CK_16XX | CK_1510 | CK_310),
 704         /* CK_GEN3 clocks */
 705         CLK(NULL,       "tc_ck",        &tc_ck.clk,     CK_16XX | CK_1510 | CK_310 | CK_7XX),
 706         CLK(NULL,       "tipb_ck",      &tipb_ck,       CK_1510 | CK_310),
 707         CLK(NULL,       "l3_ocpi_ck",   &l3_ocpi_ck,    CK_16XX | CK_7XX),
 708         CLK(NULL,       "tc1_ck",       &tc1_ck,        CK_16XX),
 709         CLK(NULL,       "tc2_ck",       &tc2_ck,        CK_16XX),
 710         CLK(NULL,       "dma_ck",       &dma_ck,        CK_16XX | CK_1510 | CK_310),
 711         CLK(NULL,       "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
 712         CLK(NULL,       "api_ck",       &api_ck.clk,    CK_16XX | CK_1510 | CK_310 | CK_7XX),
 713         CLK(NULL,       "lb_ck",        &lb_ck.clk,     CK_1510 | CK_310),
 714         CLK(NULL,       "rhea1_ck",     &rhea1_ck,      CK_16XX),
 715         CLK(NULL,       "rhea2_ck",     &rhea2_ck,      CK_16XX),
 716         CLK(NULL,       "lcd_ck",       &lcd_ck_16xx,   CK_16XX | CK_7XX),
 717         CLK(NULL,       "lcd_ck",       &lcd_ck_1510.clk, CK_1510 | CK_310),
 718         /* ULPD clocks */
 719         CLK(NULL,       "uart1_ck",     &uart1_1510,    CK_1510 | CK_310),
 720         CLK(NULL,       "uart1_ck",     &uart1_16xx.clk, CK_16XX),
 721         CLK(NULL,       "uart1_ck",     &uart1_7xx,     CK_7XX),
 722         CLK(NULL,       "uart2_ck",     &uart2_ck,      CK_16XX | CK_1510 | CK_310),
 723         CLK(NULL,       "uart2_ck",     &uart2_7xx,     CK_7XX),
 724         CLK(NULL,       "uart3_ck",     &uart3_1510,    CK_1510 | CK_310),
 725         CLK(NULL,       "uart3_ck",     &uart3_16xx.clk, CK_16XX),
 726         CLK(NULL,       "usb_clko",     &usb_clko,      CK_16XX | CK_1510 | CK_310),
 727         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck1510, CK_1510 | CK_310),
 728         CLK(NULL,       "usb_hhc_ck",   &usb_hhc_ck16xx, CK_16XX),
 729         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck,     CK_16XX),
 730         CLK(NULL,       "usb_dc_ck",    &usb_dc_ck7xx,  CK_7XX),
 731         CLK(NULL,       "mclk",         &mclk_1510,     CK_1510 | CK_310),
 732         CLK(NULL,       "mclk",         &mclk_16xx,     CK_16XX),
 733         CLK(NULL,       "bclk",         &bclk_1510,     CK_1510 | CK_310),
 734         CLK(NULL,       "bclk",         &bclk_16xx,     CK_16XX),
 735         CLK("mmci-omap.0", "fck",       &mmc1_ck,       CK_16XX | CK_1510 | CK_310),
 736         CLK("mmci-omap.0", "fck",       &mmc3_ck,       CK_7XX),
 737         CLK("mmci-omap.0", "ick",       &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
 738         CLK("mmci-omap.1", "fck",       &mmc2_ck,       CK_16XX),
 739         CLK("mmci-omap.1", "ick",       &armper_ck.clk, CK_16XX),
 740         /* Virtual clocks */
 741         CLK(NULL,       "mpu",          &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
 742         CLK("omap_i2c.1", "fck",        &i2c_fck,       CK_16XX | CK_1510 | CK_310 | CK_7XX),
 743         CLK("omap_i2c.1", "ick",        &i2c_ick,       CK_16XX),
 744         CLK("omap_i2c.1", "ick",        &dummy_ck,      CK_1510 | CK_310 | CK_7XX),
 745         CLK("omap1_spi100k.1", "fck",   &dummy_ck,      CK_7XX),
 746         CLK("omap1_spi100k.1", "ick",   &dummy_ck,      CK_7XX),
 747         CLK("omap1_spi100k.2", "fck",   &dummy_ck,      CK_7XX),
 748         CLK("omap1_spi100k.2", "ick",   &dummy_ck,      CK_7XX),
 749         CLK("omap_uwire", "fck",        &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
 750         CLK("omap-mcbsp.1", "ick",      &dspper_ck,     CK_16XX),
 751         CLK("omap-mcbsp.1", "ick",      &dummy_ck,      CK_1510 | CK_310),
 752         CLK("omap-mcbsp.2", "ick",      &armper_ck.clk, CK_16XX),
 753         CLK("omap-mcbsp.2", "ick",      &dummy_ck,      CK_1510 | CK_310),
 754         CLK("omap-mcbsp.3", "ick",      &dspper_ck,     CK_16XX),
 755         CLK("omap-mcbsp.3", "ick",      &dummy_ck,      CK_1510 | CK_310),
 756         CLK("omap-mcbsp.1", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 757         CLK("omap-mcbsp.2", "fck",      &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
 758         CLK("omap-mcbsp.3", "fck",      &dspxor_ck,     CK_16XX | CK_1510 | CK_310),
 759 };
 760
 761 /*
 762  * init
 763  */
 764
 765 static struct clk_functions omap1_clk_functions = {
 766         .clk_enable             = omap1_clk_enable,
 767         .clk_disable            = omap1_clk_disable,
 768         .clk_round_rate         = omap1_clk_round_rate,
 769         .clk_set_rate           = omap1_clk_set_rate,
 770         .clk_disable_unused     = omap1_clk_disable_unused,
 771 };
 772
 773 static void __init omap1_show_rates(void)
 774 {
 775         pr_notice("Clocking rate (xtal/DPLL1/MPU): "
 776                         "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
 777                 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
 778                 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
 779                 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 780 }
 781
 782 u32 cpu_mask;
 783
 784 int __init omap1_clk_init(void)
 785 {
 786         struct omap_clk *c;
 787         const struct omap_clock_config *info;
 788         int crystal_type = 0; /* Default 12 MHz */
 789         u32 reg;
 790
 791 #ifdef CONFIG_DEBUG_LL
 792         /*
 793          * Resets some clocks that may be left on from bootloader,
 794          * but leaves serial clocks on.
 795          */
 796         omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
 797 #endif
 798
 799         /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
 800         reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
 801         omap_writew(reg, SOFT_REQ_REG);
 802         if (!cpu_is_omap15xx())
 803                 omap_writew(0, SOFT_REQ_REG2);
 804
 805         clk_init(&omap1_clk_functions);
 806
 807         /* By default all idlect1 clocks are allowed to idle */
 808         arm_idlect1_mask = ~0;
 809
 810         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 811                 clk_preinit(c->lk.clk);
 812
 813         cpu_mask = 0;
 814         if (cpu_is_omap1710())
 815                 cpu_mask |= CK_1710;
 816         if (cpu_is_omap16xx())
 817                 cpu_mask |= CK_16XX;
 818         if (cpu_is_omap1510())
 819                 cpu_mask |= CK_1510;
 820         if (cpu_is_omap7xx())
 821                 cpu_mask |= CK_7XX;
 822         if (cpu_is_omap310())
 823                 cpu_mask |= CK_310;
 824
 825         for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
 826                 if (c->cpu & cpu_mask) {
 827                         clkdev_add(&c->lk);
 828                         clk_register(c->lk.clk);
 829                 }
 830
 831         /* Pointers to these clocks are needed by code in clock.c */
 832         api_ck_p = clk_get(NULL, "api_ck");
 833         ck_dpll1_p = clk_get(NULL, "ck_dpll1");
 834         ck_ref_p = clk_get(NULL, "ck_ref");
 835
 836         info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
 837         if (info != NULL) {
 838                 if (!cpu_is_omap15xx())
 839                         crystal_type = info->system_clock_type;
 840         }
 841
 842         if (cpu_is_omap7xx())
 843                 ck_ref.rate = 13000000;
 844         if (cpu_is_omap16xx() && crystal_type == 2)
 845                 ck_ref.rate = 19200000;
 846
 847         pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
 848                 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
 849                 omap_readw(ARM_CKCTL));
 850
 851         /* We want to be in syncronous scalable mode */
 852         omap_writew(0x1000, ARM_SYSST);
 853
 854
 855         /*
 856          * Initially use the values set by bootloader. Determine PLL rate and
 857          * recalculate dependent clocks as if kernel had changed PLL or
 858          * divisors. See also omap1_clk_late_init() that can reprogram dpll1
 859          * after the SRAM is initialized.
 860          */
 861         {
 862                 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
 863
 864                 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
 865                 if (pll_ctl_val & 0x10) {
 866                         /* PLL enabled, apply multiplier and divisor */
 867                         if (pll_ctl_val & 0xf80)
 868                                 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
 869                         ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
 870                 } else {
 871                         /* PLL disabled, apply bypass divisor */
 872                         switch (pll_ctl_val & 0xc) {
 873                         case 0:
 874                                 break;
 875                         case 0x4:
 876                                 ck_dpll1.rate /= 2;
 877                                 break;
 878                         default:
 879                                 ck_dpll1.rate /= 4;
 880                                 break;
 881                         }
 882                 }
 883         }
 884         propagate_rate(&ck_dpll1);
 885         /* Cache rates for clocks connected to ck_ref (not dpll1) */
 886         propagate_rate(&ck_ref);
 887         omap1_show_rates();
 888         if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
 889                 /* Select slicer output as OMAP input clock */
 890                 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
 891                                 OMAP7XX_PCC_UPLD_CTRL);
 892         }
 893
 894         /* Amstrad Delta wants BCLK high when inactive */
 895         if (machine_is_ams_delta())
 896                 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
 897                                 (1 << SDW_MCLK_INV_BIT),
 898                                 ULPD_CLOCK_CTRL);
 899
 900         /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
 901         /* (on 730, bit 13 must not be cleared) */
 902         if (cpu_is_omap7xx())
 903                 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
 904         else
 905                 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
 906
 907         /* Put DSP/MPUI into reset until needed */
 908         omap_writew(0, ARM_RSTCT1);
 909         omap_writew(1, ARM_RSTCT2);
 910         omap_writew(0x400, ARM_IDLECT1);
 911
 912         /*
 913          * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
 914          * of the ARM_IDLECT2 register must be set to zero. The power-on
 915          * default value of this bit is one.
 916          */
 917         omap_writew(0x0000, ARM_IDLECT2);       /* Turn LCD clock off also */
 918
 919         /*
 920          * Only enable those clocks we will need, let the drivers
 921          * enable other clocks as necessary
 922          */
 923         clk_enable(&armper_ck.clk);
 924         clk_enable(&armxor_ck.clk);
 925         clk_enable(&armtim_ck.clk); /* This should be done by timer code */
 926
 927         if (cpu_is_omap15xx())
 928                 clk_enable(&arm_gpio_ck);
 929
 930         return 0;
 931 }
 932
 933 #define OMAP1_DPLL1_SANE_VALUE  60000000
 934
 935 void __init omap1_clk_late_init(void)
 936 {
 937         unsigned long rate = ck_dpll1.rate;
 938
 939         /* Find the highest supported frequency and enable it */
 940         if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
 941                 pr_err("System frequencies not set, using default. Check your config.\n");
 942                 /*
 943                  * Reprogramming the DPLL is tricky, it must be done from SRAM.
 944                  */
 945                 omap_sram_reprogram_clock(0x2290, 0x0005);
 946                 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
 947         }
 948         propagate_rate(&ck_dpll1);
 949         omap1_show_rates();
 950         loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
 951 }