arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/suspend.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/sysfs.h>
  43 #include <linux/module.h>
  44 #include <linux/io.h>
  45 #include <linux/atomic.h>
  46
  47 #include <asm/irq.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/irq.h>
  50
  51 #include <plat/cpu.h>
  52 #include <plat/clock.h>
  53 #include <plat/sram.h>
  54 #include <plat/tc.h>
  55 #include <plat/mux.h>
  56 #include <plat/dma.h>
  57 #include <plat/dmtimer.h>
  58
  59 #include <mach/irqs.h>
  60
  61 #include "iomap.h"
  62 #include "pm.h"
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  66 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  69 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  70
  71 #ifdef CONFIG_OMAP_32K_TIMER
  72
  73 static unsigned short enable_dyn_sleep = 1;
  74
  75 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  76                          char *buf)
  77 {
  78         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  79 }
  80
  81 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  82                           const char * buf, size_t n)
  83 {
  84         unsigned short value;
  85         if (sscanf(buf, "%hu", &value) != 1 ||
  86             (value != 0 && value != 1)) {
  87                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  88                 return -EINVAL;
  89         }
  90         enable_dyn_sleep = value;
  91         return n;
  92 }
  93
  94 static struct kobj_attribute sleep_while_idle_attr =
  95         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  96
  97 #endif
  98
  99 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 100
 101 /*
 102  * Let's power down on idle, but only if we are really
 103  * idle, because once we start down the path of
 104  * going idle we continue to do idle even if we get
 105  * a clock tick interrupt . .
 106  */
 107 void omap1_pm_idle(void)
 108 {
 109         extern __u32 arm_idlect1_mask;
 110         __u32 use_idlect1 = arm_idlect1_mask;
 111         int do_sleep = 0;
 112
 113         local_irq_disable();
 114         local_fiq_disable();
 115         if (need_resched()) {
 116                 local_fiq_enable();
 117                 local_irq_enable();
 118                 return;
 119         }
 120
 121 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
 122 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 123         use_idlect1 = use_idlect1 & ~(1 << 9);
 124 #else
 125
 126         while (enable_dyn_sleep) {
 127
 128 #ifdef CONFIG_CBUS_TAHVO_USB
 129                 extern int vbus_active;
 130                 /* Clock requirements? */
 131                 if (vbus_active)
 132                         break;
 133 #endif
 134                 do_sleep = 1;
 135                 break;
 136         }
 137
 138 #endif
 139
 140 #ifdef CONFIG_OMAP_DM_TIMER
 141         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 142 #endif
 143
 144         if (omap_dma_running())
 145                 use_idlect1 &= ~(1 << 6);
 146
 147         /* We should be able to remove the do_sleep variable and multiple
 148          * tests above as soon as drivers, timer and DMA code have been fixed.
 149          * Even the sleep block count should become obsolete. */
 150         if ((use_idlect1 != ~0) || !do_sleep) {
 151
 152                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 153                 if (cpu_is_omap15xx())
 154                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 155                 else
 156                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 157                 omap_writel(use_idlect1, ARM_IDLECT1);
 158                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 159                 omap_writel(saved_idlect1, ARM_IDLECT1);
 160
 161                 local_fiq_enable();
 162                 local_irq_enable();
 163                 return;
 164         }
 165         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 166                           omap_readl(ARM_IDLECT2));
 167
 168         local_fiq_enable();
 169         local_irq_enable();
 170 }
 171
 172 /*
 173  * Configuration of the wakeup event is board specific. For the
 174  * moment we put it into this helper function. Later it may move
 175  * to board specific files.
 176  */
 177 static void omap_pm_wakeup_setup(void)
 178 {
 179         u32 level1_wake = 0;
 180         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 181
 182         /*
 183          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 184          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 185          * drivers must still separately call omap_set_gpio_wakeup() to
 186          * wake up to a GPIO interrupt.
 187          */
 188         if (cpu_is_omap7xx())
 189                 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
 190                         OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
 191         else if (cpu_is_omap15xx())
 192                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 193                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 194         else if (cpu_is_omap16xx())
 195                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 196                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 197
 198         omap_writel(~level1_wake, OMAP_IH1_MIR);
 199
 200         if (cpu_is_omap7xx()) {
 201                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 202                 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
 203                                 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
 204                                 OMAP_IH2_1_MIR);
 205         } else if (cpu_is_omap15xx()) {
 206                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 207                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 208         } else if (cpu_is_omap16xx()) {
 209                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 210                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 211
 212                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 213                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 214                             OMAP_IH2_1_MIR);
 215                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 216                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 217         }
 218
 219         /*  New IRQ agreement, recalculate in cascade order */
 220         omap_writel(1, OMAP_IH2_CONTROL);
 221         omap_writel(1, OMAP_IH1_CONTROL);
 222 }
 223
 224 #define EN_DSPCK        13      /* ARM_CKCTL */
 225 #define EN_APICK        6       /* ARM_IDLECT2 */
 226 #define DSP_EN          1       /* ARM_RSTCT1 */
 227
 228 void omap1_pm_suspend(void)
 229 {
 230         unsigned long arg0 = 0, arg1 = 0;
 231
 232         printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
 233                 omap_rev());
 234
 235         omap_serial_wake_trigger(1);
 236
 237         if (!cpu_is_omap15xx())
 238                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 239
 240         /*
 241          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 242          */
 243
 244         local_irq_disable();
 245         local_fiq_disable();
 246
 247         /*
 248          * Step 2: save registers
 249          *
 250          * The omap is a strange/beautiful device. The caches, memory
 251          * and register state are preserved across power saves.
 252          * We have to save and restore very little register state to
 253          * idle the omap.
 254          *
 255          * Save interrupt, MPUI, ARM and UPLD control registers.
 256          */
 257
 258         if (cpu_is_omap7xx()) {
 259                 MPUI7XX_SAVE(OMAP_IH1_MIR);
 260                 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
 261                 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
 262                 MPUI7XX_SAVE(MPUI_CTRL);
 263                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 264                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 265                 MPUI7XX_SAVE(EMIFS_CONFIG);
 266                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 267
 268         } else if (cpu_is_omap15xx()) {
 269                 MPUI1510_SAVE(OMAP_IH1_MIR);
 270                 MPUI1510_SAVE(OMAP_IH2_MIR);
 271                 MPUI1510_SAVE(MPUI_CTRL);
 272                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 273                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 274                 MPUI1510_SAVE(EMIFS_CONFIG);
 275                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 276         } else if (cpu_is_omap16xx()) {
 277                 MPUI1610_SAVE(OMAP_IH1_MIR);
 278                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 279                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 280                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 281                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 282                 MPUI1610_SAVE(MPUI_CTRL);
 283                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 284                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 285                 MPUI1610_SAVE(EMIFS_CONFIG);
 286                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 287         }
 288
 289         ARM_SAVE(ARM_CKCTL);
 290         ARM_SAVE(ARM_IDLECT1);
 291         ARM_SAVE(ARM_IDLECT2);
 292         if (!(cpu_is_omap15xx()))
 293                 ARM_SAVE(ARM_IDLECT3);
 294         ARM_SAVE(ARM_EWUPCT);
 295         ARM_SAVE(ARM_RSTCT1);
 296         ARM_SAVE(ARM_RSTCT2);
 297         ARM_SAVE(ARM_SYSST);
 298         ULPD_SAVE(ULPD_CLOCK_CTRL);
 299         ULPD_SAVE(ULPD_STATUS_REQ);
 300
 301         /* (Step 3 removed - we now allow deep sleep by default) */
 302
 303         /*
 304          * Step 4: OMAP DSP Shutdown
 305          */
 306
 307         /* stop DSP */
 308         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 309
 310                 /* shut down dsp_ck */
 311         if (!cpu_is_omap7xx())
 312                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 313
 314         /* temporarily enabling api_ck to access DSP registers */
 315         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 316
 317         /* save DSP registers */
 318         DSP_SAVE(DSP_IDLECT2);
 319
 320         /* Stop all DSP domain clocks */
 321         __raw_writew(0, DSP_IDLECT2);
 322
 323         /*
 324          * Step 5: Wakeup Event Setup
 325          */
 326
 327         omap_pm_wakeup_setup();
 328
 329         /*
 330          * Step 6: ARM and Traffic controller shutdown
 331          */
 332
 333         /* disable ARM watchdog */
 334         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 335         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 336
 337         /*
 338          * Step 6b: ARM and Traffic controller shutdown
 339          *
 340          * Step 6 continues here. Prepare jump to power management
 341          * assembly code in internal SRAM.
 342          *
 343          * Since the omap_cpu_suspend routine has been copied to
 344          * SRAM, we'll do an indirect procedure call to it and pass the
 345          * contents of arm_idlect1 and arm_idlect2 so it can restore
 346          * them when it wakes up and it will return.
 347          */
 348
 349         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 350         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 351
 352         /*
 353          * Step 6c: ARM and Traffic controller shutdown
 354          *
 355          * Jump to assembly code. The processor will stay there
 356          * until wake up.
 357          */
 358         omap_sram_suspend(arg0, arg1);
 359
 360         /*
 361          * If we are here, processor is woken up!
 362          */
 363
 364         /*
 365          * Restore DSP clocks
 366          */
 367
 368         /* again temporarily enabling api_ck to access DSP registers */
 369         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 370
 371         /* Restore DSP domain clocks */
 372         DSP_RESTORE(DSP_IDLECT2);
 373
 374         /*
 375          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 376          */
 377
 378         if (!(cpu_is_omap15xx()))
 379                 ARM_RESTORE(ARM_IDLECT3);
 380         ARM_RESTORE(ARM_CKCTL);
 381         ARM_RESTORE(ARM_EWUPCT);
 382         ARM_RESTORE(ARM_RSTCT1);
 383         ARM_RESTORE(ARM_RSTCT2);
 384         ARM_RESTORE(ARM_SYSST);
 385         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 386         ULPD_RESTORE(ULPD_STATUS_REQ);
 387
 388         if (cpu_is_omap7xx()) {
 389                 MPUI7XX_RESTORE(EMIFS_CONFIG);
 390                 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
 391                 MPUI7XX_RESTORE(OMAP_IH1_MIR);
 392                 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
 393                 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
 394         } else if (cpu_is_omap15xx()) {
 395                 MPUI1510_RESTORE(MPUI_CTRL);
 396                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 397                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 398                 MPUI1510_RESTORE(EMIFS_CONFIG);
 399                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 400                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 401                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 402         } else if (cpu_is_omap16xx()) {
 403                 MPUI1610_RESTORE(MPUI_CTRL);
 404                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 405                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 406                 MPUI1610_RESTORE(EMIFS_CONFIG);
 407                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 408
 409                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 410                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 411                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 412                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 413                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 414         }
 415
 416         if (!cpu_is_omap15xx())
 417                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 418
 419         /*
 420          * Re-enable interrupts
 421          */
 422
 423         local_irq_enable();
 424         local_fiq_enable();
 425
 426         omap_serial_wake_trigger(0);
 427
 428         printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
 429                 omap_rev());
 430 }
 431
 432 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 433 static int g_read_completed;
 434
 435 /*
 436  * Read system PM registers for debugging
 437  */
 438 static int omap_pm_read_proc(
 439         char *page_buffer,
 440         char **my_first_byte,
 441         off_t virtual_start,
 442         int length,
 443         int *eof,
 444         void *data)
 445 {
 446         int my_buffer_offset = 0;
 447         char * const my_base = page_buffer;
 448
 449         ARM_SAVE(ARM_CKCTL);
 450         ARM_SAVE(ARM_IDLECT1);
 451         ARM_SAVE(ARM_IDLECT2);
 452         if (!(cpu_is_omap15xx()))
 453                 ARM_SAVE(ARM_IDLECT3);
 454         ARM_SAVE(ARM_EWUPCT);
 455         ARM_SAVE(ARM_RSTCT1);
 456         ARM_SAVE(ARM_RSTCT2);
 457         ARM_SAVE(ARM_SYSST);
 458
 459         ULPD_SAVE(ULPD_IT_STATUS);
 460         ULPD_SAVE(ULPD_CLOCK_CTRL);
 461         ULPD_SAVE(ULPD_SOFT_REQ);
 462         ULPD_SAVE(ULPD_STATUS_REQ);
 463         ULPD_SAVE(ULPD_DPLL_CTRL);
 464         ULPD_SAVE(ULPD_POWER_CTRL);
 465
 466         if (cpu_is_omap7xx()) {
 467                 MPUI7XX_SAVE(MPUI_CTRL);
 468                 MPUI7XX_SAVE(MPUI_DSP_STATUS);
 469                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 470                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 471                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 472                 MPUI7XX_SAVE(EMIFS_CONFIG);
 473         } else if (cpu_is_omap15xx()) {
 474                 MPUI1510_SAVE(MPUI_CTRL);
 475                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 476                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 477                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 478                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 479                 MPUI1510_SAVE(EMIFS_CONFIG);
 480         } else if (cpu_is_omap16xx()) {
 481                 MPUI1610_SAVE(MPUI_CTRL);
 482                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 483                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 484                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 485                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 486                 MPUI1610_SAVE(EMIFS_CONFIG);
 487         }
 488
 489         if (virtual_start == 0) {
 490                 g_read_completed = 0;
 491
 492                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 493                    "ARM_CKCTL_REG:            0x%-8x     \n"
 494                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 495                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 496                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 497                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 498                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 499                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 500                    "ARM_SYSST_REG:            0x%-8x     \n"
 501                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 502                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 503                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 504                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 505                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 506                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 507                    ARM_SHOW(ARM_CKCTL),
 508                    ARM_SHOW(ARM_IDLECT1),
 509                    ARM_SHOW(ARM_IDLECT2),
 510                    ARM_SHOW(ARM_IDLECT3),
 511                    ARM_SHOW(ARM_EWUPCT),
 512                    ARM_SHOW(ARM_RSTCT1),
 513                    ARM_SHOW(ARM_RSTCT2),
 514                    ARM_SHOW(ARM_SYSST),
 515                    ULPD_SHOW(ULPD_IT_STATUS),
 516                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 517                    ULPD_SHOW(ULPD_SOFT_REQ),
 518                    ULPD_SHOW(ULPD_DPLL_CTRL),
 519                    ULPD_SHOW(ULPD_STATUS_REQ),
 520                    ULPD_SHOW(ULPD_POWER_CTRL));
 521
 522                 if (cpu_is_omap7xx()) {
 523                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 524                            "MPUI7XX_CTRL_REG         0x%-8x \n"
 525                            "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
 526                            "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 527                            "MPUI7XX_DSP_API_CONFIG_REG:  0x%-8x \n"
 528                            "MPUI7XX_SDRAM_CONFIG_REG:    0x%-8x \n"
 529                            "MPUI7XX_EMIFS_CONFIG_REG:    0x%-8x \n",
 530                            MPUI7XX_SHOW(MPUI_CTRL),
 531                            MPUI7XX_SHOW(MPUI_DSP_STATUS),
 532                            MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
 533                            MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
 534                            MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
 535                            MPUI7XX_SHOW(EMIFS_CONFIG));
 536                 } else if (cpu_is_omap15xx()) {
 537                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 538                            "MPUI1510_CTRL_REG             0x%-8x \n"
 539                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 540                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 541                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 542                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 543                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 544                            MPUI1510_SHOW(MPUI_CTRL),
 545                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 546                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 547                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 548                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 549                            MPUI1510_SHOW(EMIFS_CONFIG));
 550                 } else if (cpu_is_omap16xx()) {
 551                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 552                            "MPUI1610_CTRL_REG             0x%-8x \n"
 553                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 554                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 555                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 556                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 557                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 558                            MPUI1610_SHOW(MPUI_CTRL),
 559                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 560                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 561                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 562                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 563                            MPUI1610_SHOW(EMIFS_CONFIG));
 564                 }
 565
 566                 g_read_completed++;
 567         } else if (g_read_completed >= 1) {
 568                  *eof = 1;
 569                  return 0;
 570         }
 571         g_read_completed++;
 572
 573         *my_first_byte = page_buffer;
 574         return  my_buffer_offset;
 575 }
 576
 577 static void omap_pm_init_proc(void)
 578 {
 579         struct proc_dir_entry *entry;
 580
 581         entry = create_proc_read_entry("driver/omap_pm",
 582                                        S_IWUSR | S_IRUGO, NULL,
 583                                        omap_pm_read_proc, NULL);
 584 }
 585
 586 #endif /* DEBUG && CONFIG_PROC_FS */
 587
 588 static void (*saved_idle)(void) = NULL;
 589
 590 /*
 591  *      omap_pm_prepare - Do preliminary suspend work.
 592  *
 593  */
 594 static int omap_pm_prepare(void)
 595 {
 596         /* We cannot sleep in idle until we have resumed */
 597         saved_idle = pm_idle;
 598         pm_idle = NULL;
 599
 600         return 0;
 601 }
 602
 603
 604 /*
 605  *      omap_pm_enter - Actually enter a sleep state.
 606  *      @state:         State we're entering.
 607  *
 608  */
 609
 610 static int omap_pm_enter(suspend_state_t state)
 611 {
 612         switch (state)
 613         {
 614         case PM_SUSPEND_STANDBY:
 615         case PM_SUSPEND_MEM:
 616                 omap1_pm_suspend();
 617                 break;
 618         default:
 619                 return -EINVAL;
 620         }
 621
 622         return 0;
 623 }
 624
 625
 626 /**
 627  *      omap_pm_finish - Finish up suspend sequence.
 628  *
 629  *      This is called after we wake back up (or if entering the sleep state
 630  *      failed).
 631  */
 632
 633 static void omap_pm_finish(void)
 634 {
 635         pm_idle = saved_idle;
 636 }
 637
 638
 639 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
 640 {
 641         return IRQ_HANDLED;
 642 }
 643
 644 static struct irqaction omap_wakeup_irq = {
 645         .name           = "peripheral wakeup",
 646         .flags          = IRQF_DISABLED,
 647         .handler        = omap_wakeup_interrupt
 648 };
 649
 650
 651
 652 static const struct platform_suspend_ops omap_pm_ops = {
 653         .prepare        = omap_pm_prepare,
 654         .enter          = omap_pm_enter,
 655         .finish         = omap_pm_finish,
 656         .valid          = suspend_valid_only_mem,
 657 };
 658
 659 static int __init omap_pm_init(void)
 660 {
 661
 662 #ifdef CONFIG_OMAP_32K_TIMER
 663         int error;
 664 #endif
 665
 666         if (!cpu_class_is_omap1())
 667                 return -ENODEV;
 668
 669         printk("Power Management for TI OMAP.\n");
 670
 671         /*
 672          * We copy the assembler sleep/wakeup routines to SRAM.
 673          * These routines need to be in SRAM as that's the only
 674          * memory the MPU can see when it wakes up.
 675          */
 676         if (cpu_is_omap7xx()) {
 677                 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
 678                                                    omap7xx_cpu_suspend_sz);
 679         } else if (cpu_is_omap15xx()) {
 680                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 681                                                    omap1510_cpu_suspend_sz);
 682         } else if (cpu_is_omap16xx()) {
 683                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 684                                                    omap1610_cpu_suspend_sz);
 685         }
 686
 687         if (omap_sram_suspend == NULL) {
 688                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 689                 return -ENODEV;
 690         }
 691
 692         pm_idle = omap1_pm_idle;
 693
 694         if (cpu_is_omap7xx())
 695                 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
 696         else if (cpu_is_omap16xx())
 697                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 698
 699         /* Program new power ramp-up time
 700          * (0 for most boards since we don't lower voltage when in deep sleep)
 701          */
 702         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 703
 704         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 705         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 706
 707         /* Configure IDLECT3 */
 708         if (cpu_is_omap7xx())
 709                 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
 710         else if (cpu_is_omap16xx())
 711                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 712
 713         suspend_set_ops(&omap_pm_ops);
 714
 715 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 716         omap_pm_init_proc();
 717 #endif
 718
 719 #ifdef CONFIG_OMAP_32K_TIMER
 720         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 721         if (error)
 722                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 723 #endif
 724
 725         if (cpu_is_omap16xx()) {
 726                 /* configure LOW_PWR pin */
 727                 omap_cfg_reg(T20_1610_LOW_PWR);
 728         }
 729
 730         return 0;
 731 }
 732 __initcall(omap_pm_init);