4 * Copyright (C) 2007-2012 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
7 * Written by Paul Walmsley
8 * Updated to COMMON clk data format by Rajendra Nayak <rnayak@ti.com>
9 * With many device clock fixes by Kevin Hilman and Jouni Högander
10 * DPLL bypass clock support added by Roman Tereshonkov
15 * Virtual clocks are introduced as convenient tools.
16 * They are sources for other clocks and not supposed
17 * to be requested from drivers directly.
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clk-private.h>
23 #include <linux/list.h>
29 #include "clock3xxx.h"
30 #include "clock34xx.h"
31 #include "clock36xx.h"
32 #include "clock3517.h"
34 #include "cm-regbits-34xx.h"
36 #include "prm-regbits-34xx.h"
43 #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR
45 /* Maximum DPLL multiplier, divider values for OMAP3 */
46 #define OMAP3_MAX_DPLL_MULT 2047
47 #define OMAP3630_MAX_JTYPE_DPLL_MULT 4095
48 #define OMAP3_MAX_DPLL_DIV 128
50 DEFINE_CLK_FIXED_RATE(dummy_apb_pclk, CLK_IS_ROOT, 0x0, 0x0);
52 DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
54 DEFINE_CLK_FIXED_RATE(omap_32k_fck, CLK_IS_ROOT, 32768, 0x0);
56 DEFINE_CLK_FIXED_RATE(pclk_ck, CLK_IS_ROOT, 27000000, 0x0);
58 DEFINE_CLK_FIXED_RATE(rmii_ck, CLK_IS_ROOT, 50000000, 0x0);
60 DEFINE_CLK_FIXED_RATE(secure_32k_fck, CLK_IS_ROOT, 32768, 0x0);
62 DEFINE_CLK_FIXED_RATE(sys_altclk, CLK_IS_ROOT, 0x0, 0x0);
64 DEFINE_CLK_FIXED_RATE(virt_12m_ck, CLK_IS_ROOT, 12000000, 0x0);
66 DEFINE_CLK_FIXED_RATE(virt_13m_ck, CLK_IS_ROOT, 13000000, 0x0);
68 DEFINE_CLK_FIXED_RATE(virt_16_8m_ck, CLK_IS_ROOT, 16800000, 0x0);
70 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
72 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
74 DEFINE_CLK_FIXED_RATE(virt_38_4m_ck, CLK_IS_ROOT, 38400000, 0x0);
76 static const char *osc_sys_ck_parent_names[] = {
77 "virt_12m_ck", "virt_13m_ck", "virt_19200000_ck", "virt_26000000_ck",
78 "virt_38_4m_ck", "virt_16_8m_ck",
81 DEFINE_CLK_MUX(osc_sys_ck, osc_sys_ck_parent_names, NULL, 0x0,
82 OMAP3430_PRM_CLKSEL, OMAP3430_SYS_CLKIN_SEL_SHIFT,
83 OMAP3430_SYS_CLKIN_SEL_WIDTH, 0x0, NULL);
85 DEFINE_CLK_DIVIDER(sys_ck, "osc_sys_ck", &osc_sys_ck, 0x0,
86 OMAP3430_PRM_CLKSRC_CTRL, OMAP_SYSCLKDIV_SHIFT,
87 OMAP_SYSCLKDIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
89 static struct dpll_data dpll3_dd = {
90 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
91 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
92 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
93 .clk_bypass = &sys_ck,
95 .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK,
96 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
97 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
98 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
99 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
100 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
101 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
102 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
103 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
104 .idlest_mask = OMAP3430_ST_CORE_CLK_MASK,
105 .max_multiplier = OMAP3_MAX_DPLL_MULT,
107 .max_divider = OMAP3_MAX_DPLL_DIV,
110 static struct clk dpll3_ck;
112 static const char *dpll3_ck_parent_names[] = {
116 static const struct clk_ops dpll3_ck_ops = {
117 .init = &omap2_init_clk_clkdm,
118 .get_parent = &omap2_init_dpll_parent,
119 .recalc_rate = &omap3_dpll_recalc,
120 .round_rate = &omap2_dpll_round_rate,
123 static struct clk_hw_omap dpll3_ck_hw = {
127 .ops = &clkhwops_omap3_dpll,
128 .dpll_data = &dpll3_dd,
129 .clkdm_name = "dpll3_clkdm",
132 DEFINE_STRUCT_CLK(dpll3_ck, dpll3_ck_parent_names, dpll3_ck_ops);
134 DEFINE_CLK_DIVIDER(dpll3_m2_ck, "dpll3_ck", &dpll3_ck, 0x0,
135 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
136 OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT,
137 OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH,
138 CLK_DIVIDER_ONE_BASED, NULL);
140 static struct clk core_ck;
142 static const char *core_ck_parent_names[] = {
146 static const struct clk_ops core_ck_ops = {};
148 DEFINE_STRUCT_CLK_HW_OMAP(core_ck, NULL);
149 DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
151 DEFINE_CLK_DIVIDER(l3_ick, "core_ck", &core_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
153 OMAP3430_CLKSEL_L3_SHIFT, OMAP3430_CLKSEL_L3_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
156 DEFINE_CLK_DIVIDER(l4_ick, "l3_ick", &l3_ick, 0x0,
157 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
158 OMAP3430_CLKSEL_L4_SHIFT, OMAP3430_CLKSEL_L4_WIDTH,
159 CLK_DIVIDER_ONE_BASED, NULL);
161 static struct clk security_l4_ick2;
163 static const char *security_l4_ick2_parent_names[] = {
167 DEFINE_STRUCT_CLK_HW_OMAP(security_l4_ick2, NULL);
168 DEFINE_STRUCT_CLK(security_l4_ick2, security_l4_ick2_parent_names, core_ck_ops);
170 static struct clk aes1_ick;
172 static const char *aes1_ick_parent_names[] = {
176 static const struct clk_ops aes1_ick_ops = {
177 .enable = &omap2_dflt_clk_enable,
178 .disable = &omap2_dflt_clk_disable,
179 .is_enabled = &omap2_dflt_clk_is_enabled,
182 static struct clk_hw_omap aes1_ick_hw = {
186 .ops = &clkhwops_iclk_wait,
187 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
188 .enable_bit = OMAP3430_EN_AES1_SHIFT,
191 DEFINE_STRUCT_CLK(aes1_ick, aes1_ick_parent_names, aes1_ick_ops);
193 static struct clk core_l4_ick;
195 static const struct clk_ops core_l4_ick_ops = {
196 .init = &omap2_init_clk_clkdm,
199 DEFINE_STRUCT_CLK_HW_OMAP(core_l4_ick, "core_l4_clkdm");
200 DEFINE_STRUCT_CLK(core_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
202 static struct clk aes2_ick;
204 static const char *aes2_ick_parent_names[] = {
208 static const struct clk_ops aes2_ick_ops = {
209 .init = &omap2_init_clk_clkdm,
210 .enable = &omap2_dflt_clk_enable,
211 .disable = &omap2_dflt_clk_disable,
212 .is_enabled = &omap2_dflt_clk_is_enabled,
215 static struct clk_hw_omap aes2_ick_hw = {
219 .ops = &clkhwops_iclk_wait,
220 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
221 .enable_bit = OMAP3430_EN_AES2_SHIFT,
222 .clkdm_name = "core_l4_clkdm",
225 DEFINE_STRUCT_CLK(aes2_ick, aes2_ick_parent_names, aes2_ick_ops);
227 static struct clk dpll1_fck;
229 static struct dpll_data dpll1_dd = {
230 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
231 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
232 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
233 .clk_bypass = &dpll1_fck,
235 .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK,
236 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
237 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
238 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
239 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
240 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
241 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
242 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
243 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
244 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
245 .idlest_mask = OMAP3430_ST_MPU_CLK_MASK,
246 .max_multiplier = OMAP3_MAX_DPLL_MULT,
248 .max_divider = OMAP3_MAX_DPLL_DIV,
251 static struct clk dpll1_ck;
253 static const struct clk_ops dpll1_ck_ops = {
254 .init = &omap2_init_clk_clkdm,
255 .enable = &omap3_noncore_dpll_enable,
256 .disable = &omap3_noncore_dpll_disable,
257 .get_parent = &omap2_init_dpll_parent,
258 .recalc_rate = &omap3_dpll_recalc,
259 .set_rate = &omap3_noncore_dpll_set_rate,
260 .round_rate = &omap2_dpll_round_rate,
263 static struct clk_hw_omap dpll1_ck_hw = {
267 .ops = &clkhwops_omap3_dpll,
268 .dpll_data = &dpll1_dd,
269 .clkdm_name = "dpll1_clkdm",
272 DEFINE_STRUCT_CLK(dpll1_ck, dpll3_ck_parent_names, dpll1_ck_ops);
274 DEFINE_CLK_FIXED_FACTOR(dpll1_x2_ck, "dpll1_ck", &dpll1_ck, 0x0, 2, 1);
276 DEFINE_CLK_DIVIDER(dpll1_x2m2_ck, "dpll1_x2_ck", &dpll1_x2_ck, 0x0,
277 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
278 OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT,
279 OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH,
280 CLK_DIVIDER_ONE_BASED, NULL);
282 static struct clk mpu_ck;
284 static const char *mpu_ck_parent_names[] = {
288 DEFINE_STRUCT_CLK_HW_OMAP(mpu_ck, "mpu_clkdm");
289 DEFINE_STRUCT_CLK(mpu_ck, mpu_ck_parent_names, core_l4_ick_ops);
291 DEFINE_CLK_DIVIDER(arm_fck, "mpu_ck", &mpu_ck, 0x0,
292 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
293 OMAP3430_ST_MPU_CLK_SHIFT, OMAP3430_ST_MPU_CLK_WIDTH,
296 static struct clk cam_ick;
298 static struct clk_hw_omap cam_ick_hw = {
302 .ops = &clkhwops_iclk,
303 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
304 .enable_bit = OMAP3430_EN_CAM_SHIFT,
305 .clkdm_name = "cam_clkdm",
308 DEFINE_STRUCT_CLK(cam_ick, security_l4_ick2_parent_names, aes2_ick_ops);
311 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
313 static struct dpll_data dpll4_dd;
315 static struct dpll_data dpll4_dd_34xx __initdata = {
316 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
317 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
318 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
319 .clk_bypass = &sys_ck,
321 .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
322 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
323 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
324 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
325 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
326 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
327 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
328 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
329 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
330 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
331 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
332 .max_multiplier = OMAP3_MAX_DPLL_MULT,
334 .max_divider = OMAP3_MAX_DPLL_DIV,
337 static struct dpll_data dpll4_dd_3630 __initdata = {
338 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
339 .mult_mask = OMAP3630_PERIPH_DPLL_MULT_MASK,
340 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
341 .clk_bypass = &sys_ck,
343 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
344 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
345 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
346 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
347 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
348 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
349 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
350 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
351 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
352 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
353 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
354 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
355 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
357 .max_divider = OMAP3_MAX_DPLL_DIV,
361 static struct clk dpll4_ck;
363 static const struct clk_ops dpll4_ck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap3_noncore_dpll_enable,
366 .disable = &omap3_noncore_dpll_disable,
367 .get_parent = &omap2_init_dpll_parent,
368 .recalc_rate = &omap3_dpll_recalc,
369 .set_rate = &omap3_dpll4_set_rate,
370 .round_rate = &omap2_dpll_round_rate,
373 static struct clk_hw_omap dpll4_ck_hw = {
377 .dpll_data = &dpll4_dd,
378 .ops = &clkhwops_omap3_dpll,
379 .clkdm_name = "dpll4_clkdm",
382 DEFINE_STRUCT_CLK(dpll4_ck, dpll3_ck_parent_names, dpll4_ck_ops);
384 DEFINE_CLK_DIVIDER(dpll4_m5_ck, "dpll4_ck", &dpll4_ck, 0x0,
385 OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
386 OMAP3430_CLKSEL_CAM_SHIFT, OMAP3630_CLKSEL_CAM_WIDTH,
387 CLK_DIVIDER_ONE_BASED, NULL);
389 static struct clk dpll4_m5x2_ck;
391 static const char *dpll4_m5x2_ck_parent_names[] = {
395 static const struct clk_ops dpll4_m5x2_ck_ops = {
396 .init = &omap2_init_clk_clkdm,
397 .enable = &omap2_dflt_clk_enable,
398 .disable = &omap2_dflt_clk_disable,
399 .is_enabled = &omap2_dflt_clk_is_enabled,
400 .recalc_rate = &omap3_clkoutx2_recalc,
403 static const struct clk_ops dpll4_m5x2_ck_3630_ops = {
404 .init = &omap2_init_clk_clkdm,
405 .enable = &omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
406 .disable = &omap2_dflt_clk_disable,
407 .recalc_rate = &omap3_clkoutx2_recalc,
410 static struct clk_hw_omap dpll4_m5x2_ck_hw = {
412 .clk = &dpll4_m5x2_ck,
414 .ops = &clkhwops_wait,
415 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
416 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
417 .flags = INVERT_ENABLE,
418 .clkdm_name = "dpll4_clkdm",
421 DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
423 static struct clk dpll4_m5x2_ck_3630 = {
424 .name = "dpll4_m5x2_ck",
425 .hw = &dpll4_m5x2_ck_hw.hw,
426 .parent_names = dpll4_m5x2_ck_parent_names,
427 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
428 .ops = &dpll4_m5x2_ck_3630_ops,
431 static struct clk cam_mclk;
433 static const char *cam_mclk_parent_names[] = {
437 static struct clk_hw_omap cam_mclk_hw = {
441 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
442 .enable_bit = OMAP3430_EN_CAM_SHIFT,
443 .clkdm_name = "cam_clkdm",
446 DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops);
448 static const struct clksel_rate clkout2_src_core_rates[] = {
449 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
453 static const struct clksel_rate clkout2_src_sys_rates[] = {
454 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
458 static const struct clksel_rate clkout2_src_96m_rates[] = {
459 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
463 DEFINE_CLK_DIVIDER(dpll4_m2_ck, "dpll4_ck", &dpll4_ck, 0x0,
464 OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
465 OMAP3430_DIV_96M_SHIFT, OMAP3630_DIV_96M_WIDTH,
466 CLK_DIVIDER_ONE_BASED, NULL);
468 static struct clk dpll4_m2x2_ck;
470 static const char *dpll4_m2x2_ck_parent_names[] = {
474 static struct clk_hw_omap dpll4_m2x2_ck_hw = {
476 .clk = &dpll4_m2x2_ck,
478 .ops = &clkhwops_wait,
479 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
480 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
481 .flags = INVERT_ENABLE,
482 .clkdm_name = "dpll4_clkdm",
485 DEFINE_STRUCT_CLK(dpll4_m2x2_ck, dpll4_m2x2_ck_parent_names, dpll4_m5x2_ck_ops);
487 static struct clk dpll4_m2x2_ck_3630 = {
488 .name = "dpll4_m2x2_ck",
489 .hw = &dpll4_m2x2_ck_hw.hw,
490 .parent_names = dpll4_m2x2_ck_parent_names,
491 .num_parents = ARRAY_SIZE(dpll4_m2x2_ck_parent_names),
492 .ops = &dpll4_m5x2_ck_3630_ops,
495 static struct clk omap_96m_alwon_fck;
497 static const char *omap_96m_alwon_fck_parent_names[] = {
501 DEFINE_STRUCT_CLK_HW_OMAP(omap_96m_alwon_fck, NULL);
502 DEFINE_STRUCT_CLK(omap_96m_alwon_fck, omap_96m_alwon_fck_parent_names,
505 static struct clk cm_96m_fck;
507 static const char *cm_96m_fck_parent_names[] = {
508 "omap_96m_alwon_fck",
511 DEFINE_STRUCT_CLK_HW_OMAP(cm_96m_fck, NULL);
512 DEFINE_STRUCT_CLK(cm_96m_fck, cm_96m_fck_parent_names, core_ck_ops);
514 static const struct clksel_rate clkout2_src_54m_rates[] = {
515 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
519 DEFINE_CLK_DIVIDER(dpll4_m3_ck, "dpll4_ck", &dpll4_ck, 0x0,
520 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
521 OMAP3430_CLKSEL_TV_SHIFT, OMAP3630_CLKSEL_TV_WIDTH,
522 CLK_DIVIDER_ONE_BASED, NULL);
524 static struct clk dpll4_m3x2_ck;
526 static const char *dpll4_m3x2_ck_parent_names[] = {
530 static struct clk_hw_omap dpll4_m3x2_ck_hw = {
532 .clk = &dpll4_m3x2_ck,
534 .ops = &clkhwops_wait,
535 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
536 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
537 .flags = INVERT_ENABLE,
538 .clkdm_name = "dpll4_clkdm",
541 DEFINE_STRUCT_CLK(dpll4_m3x2_ck, dpll4_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
543 static struct clk dpll4_m3x2_ck_3630 = {
544 .name = "dpll4_m3x2_ck",
545 .hw = &dpll4_m3x2_ck_hw.hw,
546 .parent_names = dpll4_m3x2_ck_parent_names,
547 .num_parents = ARRAY_SIZE(dpll4_m3x2_ck_parent_names),
548 .ops = &dpll4_m5x2_ck_3630_ops,
551 static const char *omap_54m_fck_parent_names[] = {
552 "dpll4_m3x2_ck", "sys_altclk",
555 DEFINE_CLK_MUX(omap_54m_fck, omap_54m_fck_parent_names, NULL, 0x0,
556 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP3430_SOURCE_54M_SHIFT,
557 OMAP3430_SOURCE_54M_WIDTH, 0x0, NULL);
559 static const struct clksel clkout2_src_clksel[] = {
560 { .parent = &core_ck, .rates = clkout2_src_core_rates },
561 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
562 { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates },
563 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
567 static const char *clkout2_src_ck_parent_names[] = {
568 "core_ck", "sys_ck", "cm_96m_fck", "omap_54m_fck",
571 static const struct clk_ops clkout2_src_ck_ops = {
572 .init = &omap2_init_clk_clkdm,
573 .enable = &omap2_dflt_clk_enable,
574 .disable = &omap2_dflt_clk_disable,
575 .is_enabled = &omap2_dflt_clk_is_enabled,
576 .recalc_rate = &omap2_clksel_recalc,
577 .get_parent = &omap2_clksel_find_parent_index,
578 .set_parent = &omap2_clksel_set_parent,
581 DEFINE_CLK_OMAP_MUX_GATE(clkout2_src_ck, "core_clkdm",
582 clkout2_src_clksel, OMAP3430_CM_CLKOUT_CTRL,
583 OMAP3430_CLKOUT2SOURCE_MASK,
584 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_EN_SHIFT,
585 NULL, clkout2_src_ck_parent_names, clkout2_src_ck_ops);
587 static const struct clksel_rate omap_48m_cm96m_rates[] = {
588 { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
592 static const struct clksel_rate omap_48m_alt_rates[] = {
593 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
597 static const struct clksel omap_48m_clksel[] = {
598 { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
599 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
603 static const char *omap_48m_fck_parent_names[] = {
604 "cm_96m_fck", "sys_altclk",
607 static struct clk omap_48m_fck;
609 static const struct clk_ops omap_48m_fck_ops = {
610 .recalc_rate = &omap2_clksel_recalc,
611 .get_parent = &omap2_clksel_find_parent_index,
612 .set_parent = &omap2_clksel_set_parent,
615 static struct clk_hw_omap omap_48m_fck_hw = {
617 .clk = &omap_48m_fck,
619 .clksel = omap_48m_clksel,
620 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
621 .clksel_mask = OMAP3430_SOURCE_48M_MASK,
624 DEFINE_STRUCT_CLK(omap_48m_fck, omap_48m_fck_parent_names, omap_48m_fck_ops);
626 DEFINE_CLK_FIXED_FACTOR(omap_12m_fck, "omap_48m_fck", &omap_48m_fck, 0x0, 1, 4);
628 static struct clk core_12m_fck;
630 static const char *core_12m_fck_parent_names[] = {
634 DEFINE_STRUCT_CLK_HW_OMAP(core_12m_fck, "core_l4_clkdm");
635 DEFINE_STRUCT_CLK(core_12m_fck, core_12m_fck_parent_names, core_l4_ick_ops);
637 static struct clk core_48m_fck;
639 static const char *core_48m_fck_parent_names[] = {
643 DEFINE_STRUCT_CLK_HW_OMAP(core_48m_fck, "core_l4_clkdm");
644 DEFINE_STRUCT_CLK(core_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
646 static const char *omap_96m_fck_parent_names[] = {
647 "cm_96m_fck", "sys_ck",
650 DEFINE_CLK_MUX(omap_96m_fck, omap_96m_fck_parent_names, NULL, 0x0,
651 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
652 OMAP3430_SOURCE_96M_SHIFT, OMAP3430_SOURCE_96M_WIDTH, 0x0, NULL);
654 static struct clk core_96m_fck;
656 static const char *core_96m_fck_parent_names[] = {
660 DEFINE_STRUCT_CLK_HW_OMAP(core_96m_fck, "core_l4_clkdm");
661 DEFINE_STRUCT_CLK(core_96m_fck, core_96m_fck_parent_names, core_l4_ick_ops);
663 static struct clk core_l3_ick;
665 static const char *core_l3_ick_parent_names[] = {
669 DEFINE_STRUCT_CLK_HW_OMAP(core_l3_ick, "core_l3_clkdm");
670 DEFINE_STRUCT_CLK(core_l3_ick, core_l3_ick_parent_names, core_l4_ick_ops);
672 DEFINE_CLK_FIXED_FACTOR(dpll3_m2x2_ck, "dpll3_m2_ck", &dpll3_m2_ck, 0x0, 2, 1);
674 static struct clk corex2_fck;
676 static const char *corex2_fck_parent_names[] = {
680 DEFINE_STRUCT_CLK_HW_OMAP(corex2_fck, NULL);
681 DEFINE_STRUCT_CLK(corex2_fck, corex2_fck_parent_names, core_ck_ops);
683 static struct clk cpefuse_fck;
685 static struct clk_hw_omap cpefuse_fck_hw = {
689 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
690 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
691 .clkdm_name = "core_l4_clkdm",
694 DEFINE_STRUCT_CLK(cpefuse_fck, dpll3_ck_parent_names, aes2_ick_ops);
696 static struct clk csi2_96m_fck;
698 static const char *csi2_96m_fck_parent_names[] = {
702 static struct clk_hw_omap csi2_96m_fck_hw = {
704 .clk = &csi2_96m_fck,
706 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
707 .enable_bit = OMAP3430_EN_CSI2_SHIFT,
708 .clkdm_name = "cam_clkdm",
711 DEFINE_STRUCT_CLK(csi2_96m_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
713 static struct clk d2d_26m_fck;
715 static struct clk_hw_omap d2d_26m_fck_hw = {
719 .ops = &clkhwops_wait,
720 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
721 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
722 .clkdm_name = "d2d_clkdm",
725 DEFINE_STRUCT_CLK(d2d_26m_fck, dpll3_ck_parent_names, aes2_ick_ops);
727 static struct clk des1_ick;
729 static struct clk_hw_omap des1_ick_hw = {
733 .ops = &clkhwops_iclk_wait,
734 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
735 .enable_bit = OMAP3430_EN_DES1_SHIFT,
738 DEFINE_STRUCT_CLK(des1_ick, aes1_ick_parent_names, aes1_ick_ops);
740 static struct clk des2_ick;
742 static struct clk_hw_omap des2_ick_hw = {
746 .ops = &clkhwops_iclk_wait,
747 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
748 .enable_bit = OMAP3430_EN_DES2_SHIFT,
749 .clkdm_name = "core_l4_clkdm",
752 DEFINE_STRUCT_CLK(des2_ick, aes2_ick_parent_names, aes2_ick_ops);
754 DEFINE_CLK_DIVIDER(dpll1_fck, "core_ck", &core_ck, 0x0,
755 OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
756 OMAP3430_MPU_CLK_SRC_SHIFT, OMAP3430_MPU_CLK_SRC_WIDTH,
757 CLK_DIVIDER_ONE_BASED, NULL);
759 static struct clk dpll2_fck;
761 static struct dpll_data dpll2_dd = {
762 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
763 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
764 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
765 .clk_bypass = &dpll2_fck,
767 .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
768 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
769 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
770 .modes = ((1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
771 (1 << DPLL_LOW_POWER_BYPASS)),
772 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
773 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
774 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
775 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
776 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
777 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
778 .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK,
779 .max_multiplier = OMAP3_MAX_DPLL_MULT,
781 .max_divider = OMAP3_MAX_DPLL_DIV,
784 static struct clk dpll2_ck;
786 static struct clk_hw_omap dpll2_ck_hw = {
790 .ops = &clkhwops_omap3_dpll,
791 .dpll_data = &dpll2_dd,
792 .clkdm_name = "dpll2_clkdm",
795 DEFINE_STRUCT_CLK(dpll2_ck, dpll3_ck_parent_names, dpll1_ck_ops);
797 DEFINE_CLK_DIVIDER(dpll2_fck, "core_ck", &core_ck, 0x0,
798 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
799 OMAP3430_IVA2_CLK_SRC_SHIFT, OMAP3430_IVA2_CLK_SRC_WIDTH,
800 CLK_DIVIDER_ONE_BASED, NULL);
802 DEFINE_CLK_DIVIDER(dpll2_m2_ck, "dpll2_ck", &dpll2_ck, 0x0,
803 OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL2_PLL),
804 OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT,
805 OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH,
806 CLK_DIVIDER_ONE_BASED, NULL);
808 DEFINE_CLK_DIVIDER(dpll3_m3_ck, "dpll3_ck", &dpll3_ck, 0x0,
809 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
810 OMAP3430_DIV_DPLL3_SHIFT, OMAP3430_DIV_DPLL3_WIDTH,
811 CLK_DIVIDER_ONE_BASED, NULL);
813 static struct clk dpll3_m3x2_ck;
815 static const char *dpll3_m3x2_ck_parent_names[] = {
819 static struct clk_hw_omap dpll3_m3x2_ck_hw = {
821 .clk = &dpll3_m3x2_ck,
823 .ops = &clkhwops_wait,
824 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
825 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
826 .flags = INVERT_ENABLE,
827 .clkdm_name = "dpll3_clkdm",
830 DEFINE_STRUCT_CLK(dpll3_m3x2_ck, dpll3_m3x2_ck_parent_names, dpll4_m5x2_ck_ops);
832 static struct clk dpll3_m3x2_ck_3630 = {
833 .name = "dpll3_m3x2_ck",
834 .hw = &dpll3_m3x2_ck_hw.hw,
835 .parent_names = dpll3_m3x2_ck_parent_names,
836 .num_parents = ARRAY_SIZE(dpll3_m3x2_ck_parent_names),
837 .ops = &dpll4_m5x2_ck_3630_ops,
840 DEFINE_CLK_FIXED_FACTOR(dpll3_x2_ck, "dpll3_ck", &dpll3_ck, 0x0, 2, 1);
842 DEFINE_CLK_DIVIDER(dpll4_m4_ck, "dpll4_ck", &dpll4_ck, 0x0,
843 OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
844 OMAP3430_CLKSEL_DSS1_SHIFT, OMAP3630_CLKSEL_DSS1_WIDTH,
845 CLK_DIVIDER_ONE_BASED, NULL);
847 static struct clk dpll4_m4x2_ck;
849 static const char *dpll4_m4x2_ck_parent_names[] = {
853 static struct clk_hw_omap dpll4_m4x2_ck_hw = {
855 .clk = &dpll4_m4x2_ck,
857 .ops = &clkhwops_wait,
858 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
859 .enable_bit = OMAP3430_PWRDN_DSS1_SHIFT,
860 .flags = INVERT_ENABLE,
861 .clkdm_name = "dpll4_clkdm",
864 DEFINE_STRUCT_CLK(dpll4_m4x2_ck, dpll4_m4x2_ck_parent_names, dpll4_m5x2_ck_ops);
866 static struct clk dpll4_m4x2_ck_3630 = {
867 .name = "dpll4_m4x2_ck",
868 .hw = &dpll4_m4x2_ck_hw.hw,
869 .parent_names = dpll4_m4x2_ck_parent_names,
870 .num_parents = ARRAY_SIZE(dpll4_m4x2_ck_parent_names),
871 .ops = &dpll4_m5x2_ck_3630_ops,
874 DEFINE_CLK_DIVIDER(dpll4_m6_ck, "dpll4_ck", &dpll4_ck, 0x0,
875 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
876 OMAP3430_DIV_DPLL4_SHIFT, OMAP3630_DIV_DPLL4_WIDTH,
877 CLK_DIVIDER_ONE_BASED, NULL);
879 static struct clk dpll4_m6x2_ck;
881 static const char *dpll4_m6x2_ck_parent_names[] = {
885 static struct clk_hw_omap dpll4_m6x2_ck_hw = {
887 .clk = &dpll4_m6x2_ck,
889 .ops = &clkhwops_wait,
890 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
891 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
892 .flags = INVERT_ENABLE,
893 .clkdm_name = "dpll4_clkdm",
896 DEFINE_STRUCT_CLK(dpll4_m6x2_ck, dpll4_m6x2_ck_parent_names, dpll4_m5x2_ck_ops);
898 static struct clk dpll4_m6x2_ck_3630 = {
899 .name = "dpll4_m6x2_ck",
900 .hw = &dpll4_m6x2_ck_hw.hw,
901 .parent_names = dpll4_m6x2_ck_parent_names,
902 .num_parents = ARRAY_SIZE(dpll4_m6x2_ck_parent_names),
903 .ops = &dpll4_m5x2_ck_3630_ops,
906 DEFINE_CLK_FIXED_FACTOR(dpll4_x2_ck, "dpll4_ck", &dpll4_ck, 0x0, 2, 1);
908 static struct dpll_data dpll5_dd = {
909 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
910 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
911 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
912 .clk_bypass = &sys_ck,
914 .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
915 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
916 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
917 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
918 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
919 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
920 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
921 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
922 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
923 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
924 .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
925 .max_multiplier = OMAP3_MAX_DPLL_MULT,
927 .max_divider = OMAP3_MAX_DPLL_DIV,
930 static struct clk dpll5_ck;
932 static struct clk_hw_omap dpll5_ck_hw = {
936 .ops = &clkhwops_omap3_dpll,
937 .dpll_data = &dpll5_dd,
938 .clkdm_name = "dpll5_clkdm",
941 DEFINE_STRUCT_CLK(dpll5_ck, dpll3_ck_parent_names, dpll1_ck_ops);
943 DEFINE_CLK_DIVIDER(dpll5_m2_ck, "dpll5_ck", &dpll5_ck, 0x0,
944 OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
945 OMAP3430ES2_DIV_120M_SHIFT, OMAP3430ES2_DIV_120M_WIDTH,
946 CLK_DIVIDER_ONE_BASED, NULL);
948 static struct clk dss1_alwon_fck_3430es1;
950 static const char *dss1_alwon_fck_3430es1_parent_names[] = {
954 static struct clk_hw_omap dss1_alwon_fck_3430es1_hw = {
956 .clk = &dss1_alwon_fck_3430es1,
958 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
959 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
960 .clkdm_name = "dss_clkdm",
963 DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es1, dss1_alwon_fck_3430es1_parent_names,
966 static struct clk dss1_alwon_fck_3430es2;
968 static struct clk_hw_omap dss1_alwon_fck_3430es2_hw = {
970 .clk = &dss1_alwon_fck_3430es2,
972 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
973 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
974 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
975 .clkdm_name = "dss_clkdm",
978 DEFINE_STRUCT_CLK(dss1_alwon_fck_3430es2, dss1_alwon_fck_3430es1_parent_names,
981 static struct clk dss2_alwon_fck;
983 static struct clk_hw_omap dss2_alwon_fck_hw = {
985 .clk = &dss2_alwon_fck,
987 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
988 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
989 .clkdm_name = "dss_clkdm",
992 DEFINE_STRUCT_CLK(dss2_alwon_fck, dpll3_ck_parent_names, aes2_ick_ops);
994 static struct clk dss_96m_fck;
996 static struct clk_hw_omap dss_96m_fck_hw = {
1000 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1001 .enable_bit = OMAP3430_EN_TV_SHIFT,
1002 .clkdm_name = "dss_clkdm",
1005 DEFINE_STRUCT_CLK(dss_96m_fck, core_96m_fck_parent_names, aes2_ick_ops);
1007 static struct clk dss_ick_3430es1;
1009 static struct clk_hw_omap dss_ick_3430es1_hw = {
1011 .clk = &dss_ick_3430es1,
1013 .ops = &clkhwops_iclk,
1014 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1015 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1016 .clkdm_name = "dss_clkdm",
1019 DEFINE_STRUCT_CLK(dss_ick_3430es1, security_l4_ick2_parent_names, aes2_ick_ops);
1021 static struct clk dss_ick_3430es2;
1023 static struct clk_hw_omap dss_ick_3430es2_hw = {
1025 .clk = &dss_ick_3430es2,
1027 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
1028 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1029 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1030 .clkdm_name = "dss_clkdm",
1033 DEFINE_STRUCT_CLK(dss_ick_3430es2, security_l4_ick2_parent_names, aes2_ick_ops);
1035 static struct clk dss_tv_fck;
1037 static const char *dss_tv_fck_parent_names[] = {
1041 static struct clk_hw_omap dss_tv_fck_hw = {
1045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1046 .enable_bit = OMAP3430_EN_TV_SHIFT,
1047 .clkdm_name = "dss_clkdm",
1050 DEFINE_STRUCT_CLK(dss_tv_fck, dss_tv_fck_parent_names, aes2_ick_ops);
1052 static struct clk emac_fck;
1054 static const char *emac_fck_parent_names[] = {
1058 static struct clk_hw_omap emac_fck_hw = {
1062 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1063 .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT,
1066 DEFINE_STRUCT_CLK(emac_fck, emac_fck_parent_names, aes1_ick_ops);
1068 static struct clk ipss_ick;
1070 static const char *ipss_ick_parent_names[] = {
1074 static struct clk_hw_omap ipss_ick_hw = {
1078 .ops = &clkhwops_am35xx_ipss_wait,
1079 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1080 .enable_bit = AM35XX_EN_IPSS_SHIFT,
1081 .clkdm_name = "core_l3_clkdm",
1084 DEFINE_STRUCT_CLK(ipss_ick, ipss_ick_parent_names, aes2_ick_ops);
1086 static struct clk emac_ick;
1088 static const char *emac_ick_parent_names[] = {
1092 static struct clk_hw_omap emac_ick_hw = {
1096 .ops = &clkhwops_am35xx_ipss_module_wait,
1097 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1098 .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
1099 .clkdm_name = "core_l3_clkdm",
1102 DEFINE_STRUCT_CLK(emac_ick, emac_ick_parent_names, aes2_ick_ops);
1104 static struct clk emu_core_alwon_ck;
1106 static const char *emu_core_alwon_ck_parent_names[] = {
1110 DEFINE_STRUCT_CLK_HW_OMAP(emu_core_alwon_ck, "dpll3_clkdm");
1111 DEFINE_STRUCT_CLK(emu_core_alwon_ck, emu_core_alwon_ck_parent_names,
1114 static struct clk emu_mpu_alwon_ck;
1116 static const char *emu_mpu_alwon_ck_parent_names[] = {
1120 DEFINE_STRUCT_CLK_HW_OMAP(emu_mpu_alwon_ck, NULL);
1121 DEFINE_STRUCT_CLK(emu_mpu_alwon_ck, emu_mpu_alwon_ck_parent_names, core_ck_ops);
1123 static struct clk emu_per_alwon_ck;
1125 static const char *emu_per_alwon_ck_parent_names[] = {
1129 DEFINE_STRUCT_CLK_HW_OMAP(emu_per_alwon_ck, "dpll4_clkdm");
1130 DEFINE_STRUCT_CLK(emu_per_alwon_ck, emu_per_alwon_ck_parent_names,
1133 static const char *emu_src_ck_parent_names[] = {
1134 "sys_ck", "emu_core_alwon_ck", "emu_per_alwon_ck", "emu_mpu_alwon_ck",
1137 static const struct clksel_rate emu_src_sys_rates[] = {
1138 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1142 static const struct clksel_rate emu_src_core_rates[] = {
1143 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1147 static const struct clksel_rate emu_src_per_rates[] = {
1148 { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
1152 static const struct clksel_rate emu_src_mpu_rates[] = {
1153 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
1157 static const struct clksel emu_src_clksel[] = {
1158 { .parent = &sys_ck, .rates = emu_src_sys_rates },
1159 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
1160 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
1161 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
1165 static const struct clk_ops emu_src_ck_ops = {
1166 .init = &omap2_init_clk_clkdm,
1167 .recalc_rate = &omap2_clksel_recalc,
1168 .get_parent = &omap2_clksel_find_parent_index,
1169 .set_parent = &omap2_clksel_set_parent,
1172 static struct clk emu_src_ck;
1174 static struct clk_hw_omap emu_src_ck_hw = {
1178 .clksel = emu_src_clksel,
1179 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1180 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
1181 .clkdm_name = "emu_clkdm",
1184 DEFINE_STRUCT_CLK(emu_src_ck, emu_src_ck_parent_names, emu_src_ck_ops);
1186 DEFINE_CLK_DIVIDER(atclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
1187 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
1188 OMAP3430_CLKSEL_ATCLK_SHIFT, OMAP3430_CLKSEL_ATCLK_WIDTH,
1189 CLK_DIVIDER_ONE_BASED, NULL);
1191 static struct clk fac_ick;
1193 static struct clk_hw_omap fac_ick_hw = {
1197 .ops = &clkhwops_iclk_wait,
1198 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1199 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1200 .clkdm_name = "core_l4_clkdm",
1203 DEFINE_STRUCT_CLK(fac_ick, aes2_ick_parent_names, aes2_ick_ops);
1205 static struct clk fshostusb_fck;
1207 static const char *fshostusb_fck_parent_names[] = {
1211 static struct clk_hw_omap fshostusb_fck_hw = {
1213 .clk = &fshostusb_fck,
1215 .ops = &clkhwops_wait,
1216 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1217 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1218 .clkdm_name = "core_l4_clkdm",
1221 DEFINE_STRUCT_CLK(fshostusb_fck, fshostusb_fck_parent_names, aes2_ick_ops);
1223 static struct clk gfx_l3_ck;
1225 static struct clk_hw_omap gfx_l3_ck_hw = {
1229 .ops = &clkhwops_wait,
1230 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1231 .enable_bit = OMAP_EN_GFX_SHIFT,
1232 .clkdm_name = "gfx_3430es1_clkdm",
1235 DEFINE_STRUCT_CLK(gfx_l3_ck, core_l3_ick_parent_names, aes1_ick_ops);
1237 DEFINE_CLK_DIVIDER(gfx_l3_fck, "l3_ick", &l3_ick, 0x0,
1238 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1239 OMAP_CLKSEL_GFX_SHIFT, OMAP_CLKSEL_GFX_WIDTH,
1240 CLK_DIVIDER_ONE_BASED, NULL);
1242 static struct clk gfx_cg1_ck;
1244 static const char *gfx_cg1_ck_parent_names[] = {
1248 static struct clk_hw_omap gfx_cg1_ck_hw = {
1252 .ops = &clkhwops_wait,
1253 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1254 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1255 .clkdm_name = "gfx_3430es1_clkdm",
1258 DEFINE_STRUCT_CLK(gfx_cg1_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1260 static struct clk gfx_cg2_ck;
1262 static struct clk_hw_omap gfx_cg2_ck_hw = {
1266 .ops = &clkhwops_wait,
1267 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1268 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1269 .clkdm_name = "gfx_3430es1_clkdm",
1272 DEFINE_STRUCT_CLK(gfx_cg2_ck, gfx_cg1_ck_parent_names, aes2_ick_ops);
1274 static struct clk gfx_l3_ick;
1276 static const char *gfx_l3_ick_parent_names[] = {
1280 DEFINE_STRUCT_CLK_HW_OMAP(gfx_l3_ick, "gfx_3430es1_clkdm");
1281 DEFINE_STRUCT_CLK(gfx_l3_ick, gfx_l3_ick_parent_names, core_l4_ick_ops);
1283 static struct clk wkup_32k_fck;
1285 static const char *wkup_32k_fck_parent_names[] = {
1289 DEFINE_STRUCT_CLK_HW_OMAP(wkup_32k_fck, "wkup_clkdm");
1290 DEFINE_STRUCT_CLK(wkup_32k_fck, wkup_32k_fck_parent_names, core_l4_ick_ops);
1292 static struct clk gpio1_dbck;
1294 static const char *gpio1_dbck_parent_names[] = {
1298 static struct clk_hw_omap gpio1_dbck_hw = {
1302 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1303 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1304 .clkdm_name = "wkup_clkdm",
1307 DEFINE_STRUCT_CLK(gpio1_dbck, gpio1_dbck_parent_names, aes2_ick_ops);
1309 static struct clk wkup_l4_ick;
1311 DEFINE_STRUCT_CLK_HW_OMAP(wkup_l4_ick, "wkup_clkdm");
1312 DEFINE_STRUCT_CLK(wkup_l4_ick, dpll3_ck_parent_names, core_l4_ick_ops);
1314 static struct clk gpio1_ick;
1316 static const char *gpio1_ick_parent_names[] = {
1320 static struct clk_hw_omap gpio1_ick_hw = {
1324 .ops = &clkhwops_iclk_wait,
1325 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1326 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
1327 .clkdm_name = "wkup_clkdm",
1330 DEFINE_STRUCT_CLK(gpio1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1332 static struct clk per_32k_alwon_fck;
1334 DEFINE_STRUCT_CLK_HW_OMAP(per_32k_alwon_fck, "per_clkdm");
1335 DEFINE_STRUCT_CLK(per_32k_alwon_fck, wkup_32k_fck_parent_names,
1338 static struct clk gpio2_dbck;
1340 static const char *gpio2_dbck_parent_names[] = {
1341 "per_32k_alwon_fck",
1344 static struct clk_hw_omap gpio2_dbck_hw = {
1348 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1349 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1350 .clkdm_name = "per_clkdm",
1353 DEFINE_STRUCT_CLK(gpio2_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1355 static struct clk per_l4_ick;
1357 DEFINE_STRUCT_CLK_HW_OMAP(per_l4_ick, "per_clkdm");
1358 DEFINE_STRUCT_CLK(per_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
1360 static struct clk gpio2_ick;
1362 static const char *gpio2_ick_parent_names[] = {
1366 static struct clk_hw_omap gpio2_ick_hw = {
1370 .ops = &clkhwops_iclk_wait,
1371 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1372 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
1373 .clkdm_name = "per_clkdm",
1376 DEFINE_STRUCT_CLK(gpio2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1378 static struct clk gpio3_dbck;
1380 static struct clk_hw_omap gpio3_dbck_hw = {
1384 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1385 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1386 .clkdm_name = "per_clkdm",
1389 DEFINE_STRUCT_CLK(gpio3_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1391 static struct clk gpio3_ick;
1393 static struct clk_hw_omap gpio3_ick_hw = {
1397 .ops = &clkhwops_iclk_wait,
1398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1399 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
1400 .clkdm_name = "per_clkdm",
1403 DEFINE_STRUCT_CLK(gpio3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1405 static struct clk gpio4_dbck;
1407 static struct clk_hw_omap gpio4_dbck_hw = {
1411 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1412 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1413 .clkdm_name = "per_clkdm",
1416 DEFINE_STRUCT_CLK(gpio4_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1418 static struct clk gpio4_ick;
1420 static struct clk_hw_omap gpio4_ick_hw = {
1424 .ops = &clkhwops_iclk_wait,
1425 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1426 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
1427 .clkdm_name = "per_clkdm",
1430 DEFINE_STRUCT_CLK(gpio4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1432 static struct clk gpio5_dbck;
1434 static struct clk_hw_omap gpio5_dbck_hw = {
1438 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1439 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1440 .clkdm_name = "per_clkdm",
1443 DEFINE_STRUCT_CLK(gpio5_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1445 static struct clk gpio5_ick;
1447 static struct clk_hw_omap gpio5_ick_hw = {
1451 .ops = &clkhwops_iclk_wait,
1452 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1453 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
1454 .clkdm_name = "per_clkdm",
1457 DEFINE_STRUCT_CLK(gpio5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1459 static struct clk gpio6_dbck;
1461 static struct clk_hw_omap gpio6_dbck_hw = {
1465 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1466 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1467 .clkdm_name = "per_clkdm",
1470 DEFINE_STRUCT_CLK(gpio6_dbck, gpio2_dbck_parent_names, aes2_ick_ops);
1472 static struct clk gpio6_ick;
1474 static struct clk_hw_omap gpio6_ick_hw = {
1478 .ops = &clkhwops_iclk_wait,
1479 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1480 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
1481 .clkdm_name = "per_clkdm",
1484 DEFINE_STRUCT_CLK(gpio6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1486 static struct clk gpmc_fck;
1488 static struct clk_hw_omap gpmc_fck_hw = {
1492 .flags = ENABLE_ON_INIT,
1493 .clkdm_name = "core_l3_clkdm",
1496 DEFINE_STRUCT_CLK(gpmc_fck, ipss_ick_parent_names, core_l4_ick_ops);
1498 static const struct clksel omap343x_gpt_clksel[] = {
1499 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1500 { .parent = &sys_ck, .rates = gpt_sys_rates },
1504 static const char *gpt10_fck_parent_names[] = {
1505 "omap_32k_fck", "sys_ck",
1508 DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1509 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1510 OMAP3430_CLKSEL_GPT10_MASK,
1511 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512 OMAP3430_EN_GPT10_SHIFT, &clkhwops_wait,
1513 gpt10_fck_parent_names, clkout2_src_ck_ops);
1515 static struct clk gpt10_ick;
1517 static struct clk_hw_omap gpt10_ick_hw = {
1521 .ops = &clkhwops_iclk_wait,
1522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1523 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1524 .clkdm_name = "core_l4_clkdm",
1527 DEFINE_STRUCT_CLK(gpt10_ick, aes2_ick_parent_names, aes2_ick_ops);
1529 DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap343x_gpt_clksel,
1530 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1531 OMAP3430_CLKSEL_GPT11_MASK,
1532 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1533 OMAP3430_EN_GPT11_SHIFT, &clkhwops_wait,
1534 gpt10_fck_parent_names, clkout2_src_ck_ops);
1536 static struct clk gpt11_ick;
1538 static struct clk_hw_omap gpt11_ick_hw = {
1542 .ops = &clkhwops_iclk_wait,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1544 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1545 .clkdm_name = "core_l4_clkdm",
1548 DEFINE_STRUCT_CLK(gpt11_ick, aes2_ick_parent_names, aes2_ick_ops);
1550 static struct clk gpt12_fck;
1552 static const char *gpt12_fck_parent_names[] = {
1556 DEFINE_STRUCT_CLK_HW_OMAP(gpt12_fck, "wkup_clkdm");
1557 DEFINE_STRUCT_CLK(gpt12_fck, gpt12_fck_parent_names, core_l4_ick_ops);
1559 static struct clk gpt12_ick;
1561 static struct clk_hw_omap gpt12_ick_hw = {
1565 .ops = &clkhwops_iclk_wait,
1566 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1567 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
1568 .clkdm_name = "wkup_clkdm",
1571 DEFINE_STRUCT_CLK(gpt12_ick, gpio1_ick_parent_names, aes2_ick_ops);
1573 DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "wkup_clkdm", omap343x_gpt_clksel,
1574 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1575 OMAP3430_CLKSEL_GPT1_MASK,
1576 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1577 OMAP3430_EN_GPT1_SHIFT, &clkhwops_wait,
1578 gpt10_fck_parent_names, clkout2_src_ck_ops);
1580 static struct clk gpt1_ick;
1582 static struct clk_hw_omap gpt1_ick_hw = {
1586 .ops = &clkhwops_iclk_wait,
1587 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1588 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
1589 .clkdm_name = "wkup_clkdm",
1592 DEFINE_STRUCT_CLK(gpt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
1594 DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "per_clkdm", omap343x_gpt_clksel,
1595 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1596 OMAP3430_CLKSEL_GPT2_MASK,
1597 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1598 OMAP3430_EN_GPT2_SHIFT, &clkhwops_wait,
1599 gpt10_fck_parent_names, clkout2_src_ck_ops);
1601 static struct clk gpt2_ick;
1603 static struct clk_hw_omap gpt2_ick_hw = {
1607 .ops = &clkhwops_iclk_wait,
1608 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1609 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
1610 .clkdm_name = "per_clkdm",
1613 DEFINE_STRUCT_CLK(gpt2_ick, gpio2_ick_parent_names, aes2_ick_ops);
1615 DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "per_clkdm", omap343x_gpt_clksel,
1616 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1617 OMAP3430_CLKSEL_GPT3_MASK,
1618 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1619 OMAP3430_EN_GPT3_SHIFT, &clkhwops_wait,
1620 gpt10_fck_parent_names, clkout2_src_ck_ops);
1622 static struct clk gpt3_ick;
1624 static struct clk_hw_omap gpt3_ick_hw = {
1628 .ops = &clkhwops_iclk_wait,
1629 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1630 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
1631 .clkdm_name = "per_clkdm",
1634 DEFINE_STRUCT_CLK(gpt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
1636 DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "per_clkdm", omap343x_gpt_clksel,
1637 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1638 OMAP3430_CLKSEL_GPT4_MASK,
1639 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1640 OMAP3430_EN_GPT4_SHIFT, &clkhwops_wait,
1641 gpt10_fck_parent_names, clkout2_src_ck_ops);
1643 static struct clk gpt4_ick;
1645 static struct clk_hw_omap gpt4_ick_hw = {
1649 .ops = &clkhwops_iclk_wait,
1650 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1651 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
1652 .clkdm_name = "per_clkdm",
1655 DEFINE_STRUCT_CLK(gpt4_ick, gpio2_ick_parent_names, aes2_ick_ops);
1657 DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "per_clkdm", omap343x_gpt_clksel,
1658 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1659 OMAP3430_CLKSEL_GPT5_MASK,
1660 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1661 OMAP3430_EN_GPT5_SHIFT, &clkhwops_wait,
1662 gpt10_fck_parent_names, clkout2_src_ck_ops);
1664 static struct clk gpt5_ick;
1666 static struct clk_hw_omap gpt5_ick_hw = {
1670 .ops = &clkhwops_iclk_wait,
1671 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1672 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
1673 .clkdm_name = "per_clkdm",
1676 DEFINE_STRUCT_CLK(gpt5_ick, gpio2_ick_parent_names, aes2_ick_ops);
1678 DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "per_clkdm", omap343x_gpt_clksel,
1679 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1680 OMAP3430_CLKSEL_GPT6_MASK,
1681 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1682 OMAP3430_EN_GPT6_SHIFT, &clkhwops_wait,
1683 gpt10_fck_parent_names, clkout2_src_ck_ops);
1685 static struct clk gpt6_ick;
1687 static struct clk_hw_omap gpt6_ick_hw = {
1691 .ops = &clkhwops_iclk_wait,
1692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1693 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
1694 .clkdm_name = "per_clkdm",
1697 DEFINE_STRUCT_CLK(gpt6_ick, gpio2_ick_parent_names, aes2_ick_ops);
1699 DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "per_clkdm", omap343x_gpt_clksel,
1700 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1701 OMAP3430_CLKSEL_GPT7_MASK,
1702 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1703 OMAP3430_EN_GPT7_SHIFT, &clkhwops_wait,
1704 gpt10_fck_parent_names, clkout2_src_ck_ops);
1706 static struct clk gpt7_ick;
1708 static struct clk_hw_omap gpt7_ick_hw = {
1712 .ops = &clkhwops_iclk_wait,
1713 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1714 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
1715 .clkdm_name = "per_clkdm",
1718 DEFINE_STRUCT_CLK(gpt7_ick, gpio2_ick_parent_names, aes2_ick_ops);
1720 DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "per_clkdm", omap343x_gpt_clksel,
1721 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1722 OMAP3430_CLKSEL_GPT8_MASK,
1723 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1724 OMAP3430_EN_GPT8_SHIFT, &clkhwops_wait,
1725 gpt10_fck_parent_names, clkout2_src_ck_ops);
1727 static struct clk gpt8_ick;
1729 static struct clk_hw_omap gpt8_ick_hw = {
1733 .ops = &clkhwops_iclk_wait,
1734 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1735 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
1736 .clkdm_name = "per_clkdm",
1739 DEFINE_STRUCT_CLK(gpt8_ick, gpio2_ick_parent_names, aes2_ick_ops);
1741 DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "per_clkdm", omap343x_gpt_clksel,
1742 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
1743 OMAP3430_CLKSEL_GPT9_MASK,
1744 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
1745 OMAP3430_EN_GPT9_SHIFT, &clkhwops_wait,
1746 gpt10_fck_parent_names, clkout2_src_ck_ops);
1748 static struct clk gpt9_ick;
1750 static struct clk_hw_omap gpt9_ick_hw = {
1754 .ops = &clkhwops_iclk_wait,
1755 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
1756 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
1757 .clkdm_name = "per_clkdm",
1760 DEFINE_STRUCT_CLK(gpt9_ick, gpio2_ick_parent_names, aes2_ick_ops);
1762 static struct clk hdq_fck;
1764 static const char *hdq_fck_parent_names[] = {
1768 static struct clk_hw_omap hdq_fck_hw = {
1772 .ops = &clkhwops_wait,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1774 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1775 .clkdm_name = "core_l4_clkdm",
1778 DEFINE_STRUCT_CLK(hdq_fck, hdq_fck_parent_names, aes2_ick_ops);
1780 static struct clk hdq_ick;
1782 static struct clk_hw_omap hdq_ick_hw = {
1786 .ops = &clkhwops_iclk_wait,
1787 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1788 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1789 .clkdm_name = "core_l4_clkdm",
1792 DEFINE_STRUCT_CLK(hdq_ick, aes2_ick_parent_names, aes2_ick_ops);
1794 static struct clk hecc_ck;
1796 static struct clk_hw_omap hecc_ck_hw = {
1800 .ops = &clkhwops_am35xx_ipss_module_wait,
1801 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1802 .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT,
1803 .clkdm_name = "core_l3_clkdm",
1806 DEFINE_STRUCT_CLK(hecc_ck, dpll3_ck_parent_names, aes2_ick_ops);
1808 static struct clk hsotgusb_fck_am35xx;
1810 static struct clk_hw_omap hsotgusb_fck_am35xx_hw = {
1812 .clk = &hsotgusb_fck_am35xx,
1814 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1815 .enable_bit = AM35XX_USBOTG_FCLK_SHIFT,
1816 .clkdm_name = "core_l3_clkdm",
1819 DEFINE_STRUCT_CLK(hsotgusb_fck_am35xx, dpll3_ck_parent_names, aes2_ick_ops);
1821 static struct clk hsotgusb_ick_3430es1;
1823 static struct clk_hw_omap hsotgusb_ick_3430es1_hw = {
1825 .clk = &hsotgusb_ick_3430es1,
1827 .ops = &clkhwops_iclk,
1828 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1830 .clkdm_name = "core_l3_clkdm",
1833 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es1, ipss_ick_parent_names, aes2_ick_ops);
1835 static struct clk hsotgusb_ick_3430es2;
1837 static struct clk_hw_omap hsotgusb_ick_3430es2_hw = {
1839 .clk = &hsotgusb_ick_3430es2,
1841 .ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1844 .clkdm_name = "core_l3_clkdm",
1847 DEFINE_STRUCT_CLK(hsotgusb_ick_3430es2, ipss_ick_parent_names, aes2_ick_ops);
1849 static struct clk hsotgusb_ick_am35xx;
1851 static struct clk_hw_omap hsotgusb_ick_am35xx_hw = {
1853 .clk = &hsotgusb_ick_am35xx,
1855 .ops = &clkhwops_am35xx_ipss_module_wait,
1856 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
1857 .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
1858 .clkdm_name = "core_l3_clkdm",
1861 DEFINE_STRUCT_CLK(hsotgusb_ick_am35xx, emac_ick_parent_names, aes2_ick_ops);
1863 static struct clk i2c1_fck;
1865 static struct clk_hw_omap i2c1_fck_hw = {
1869 .ops = &clkhwops_wait,
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1871 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1872 .clkdm_name = "core_l4_clkdm",
1875 DEFINE_STRUCT_CLK(i2c1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1877 static struct clk i2c1_ick;
1879 static struct clk_hw_omap i2c1_ick_hw = {
1883 .ops = &clkhwops_iclk_wait,
1884 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1885 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1886 .clkdm_name = "core_l4_clkdm",
1889 DEFINE_STRUCT_CLK(i2c1_ick, aes2_ick_parent_names, aes2_ick_ops);
1891 static struct clk i2c2_fck;
1893 static struct clk_hw_omap i2c2_fck_hw = {
1897 .ops = &clkhwops_wait,
1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1899 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1900 .clkdm_name = "core_l4_clkdm",
1903 DEFINE_STRUCT_CLK(i2c2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1905 static struct clk i2c2_ick;
1907 static struct clk_hw_omap i2c2_ick_hw = {
1911 .ops = &clkhwops_iclk_wait,
1912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1914 .clkdm_name = "core_l4_clkdm",
1917 DEFINE_STRUCT_CLK(i2c2_ick, aes2_ick_parent_names, aes2_ick_ops);
1919 static struct clk i2c3_fck;
1921 static struct clk_hw_omap i2c3_fck_hw = {
1925 .ops = &clkhwops_wait,
1926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1927 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1928 .clkdm_name = "core_l4_clkdm",
1931 DEFINE_STRUCT_CLK(i2c3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
1933 static struct clk i2c3_ick;
1935 static struct clk_hw_omap i2c3_ick_hw = {
1939 .ops = &clkhwops_iclk_wait,
1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1941 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1942 .clkdm_name = "core_l4_clkdm",
1945 DEFINE_STRUCT_CLK(i2c3_ick, aes2_ick_parent_names, aes2_ick_ops);
1947 static struct clk icr_ick;
1949 static struct clk_hw_omap icr_ick_hw = {
1953 .ops = &clkhwops_iclk_wait,
1954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1955 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1956 .clkdm_name = "core_l4_clkdm",
1959 DEFINE_STRUCT_CLK(icr_ick, aes2_ick_parent_names, aes2_ick_ops);
1961 static struct clk iva2_ck;
1963 static const char *iva2_ck_parent_names[] = {
1967 static struct clk_hw_omap iva2_ck_hw = {
1971 .ops = &clkhwops_wait,
1972 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1973 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1974 .clkdm_name = "iva2_clkdm",
1977 DEFINE_STRUCT_CLK(iva2_ck, iva2_ck_parent_names, aes2_ick_ops);
1979 static struct clk mad2d_ick;
1981 static struct clk_hw_omap mad2d_ick_hw = {
1985 .ops = &clkhwops_iclk_wait,
1986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1987 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
1988 .clkdm_name = "d2d_clkdm",
1991 DEFINE_STRUCT_CLK(mad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
1993 static struct clk mailboxes_ick;
1995 static struct clk_hw_omap mailboxes_ick_hw = {
1997 .clk = &mailboxes_ick,
1999 .ops = &clkhwops_iclk_wait,
2000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2001 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2002 .clkdm_name = "core_l4_clkdm",
2005 DEFINE_STRUCT_CLK(mailboxes_ick, aes2_ick_parent_names, aes2_ick_ops);
2007 static const struct clksel_rate common_mcbsp_96m_rates[] = {
2008 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2012 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
2013 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2017 static const struct clksel mcbsp_15_clksel[] = {
2018 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
2019 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2023 static const char *mcbsp1_fck_parent_names[] = {
2024 "core_96m_fck", "mcbsp_clks",
2027 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_15_clksel,
2028 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2029 OMAP2_MCBSP1_CLKS_MASK,
2030 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2031 OMAP3430_EN_MCBSP1_SHIFT, &clkhwops_wait,
2032 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2034 static struct clk mcbsp1_ick;
2036 static struct clk_hw_omap mcbsp1_ick_hw = {
2040 .ops = &clkhwops_iclk_wait,
2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2042 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
2043 .clkdm_name = "core_l4_clkdm",
2046 DEFINE_STRUCT_CLK(mcbsp1_ick, aes2_ick_parent_names, aes2_ick_ops);
2048 static struct clk per_96m_fck;
2050 DEFINE_STRUCT_CLK_HW_OMAP(per_96m_fck, "per_clkdm");
2051 DEFINE_STRUCT_CLK(per_96m_fck, cm_96m_fck_parent_names, core_l4_ick_ops);
2053 static const struct clksel mcbsp_234_clksel[] = {
2054 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2055 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2059 static const char *mcbsp2_fck_parent_names[] = {
2060 "per_96m_fck", "mcbsp_clks",
2063 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "per_clkdm", mcbsp_234_clksel,
2064 OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2065 OMAP2_MCBSP2_CLKS_MASK,
2066 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2067 OMAP3430_EN_MCBSP2_SHIFT, &clkhwops_wait,
2068 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2070 static struct clk mcbsp2_ick;
2072 static struct clk_hw_omap mcbsp2_ick_hw = {
2076 .ops = &clkhwops_iclk_wait,
2077 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2078 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2079 .clkdm_name = "per_clkdm",
2082 DEFINE_STRUCT_CLK(mcbsp2_ick, gpio2_ick_parent_names, aes2_ick_ops);
2084 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "per_clkdm", mcbsp_234_clksel,
2085 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2086 OMAP2_MCBSP3_CLKS_MASK,
2087 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2088 OMAP3430_EN_MCBSP3_SHIFT, &clkhwops_wait,
2089 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2091 static struct clk mcbsp3_ick;
2093 static struct clk_hw_omap mcbsp3_ick_hw = {
2097 .ops = &clkhwops_iclk_wait,
2098 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2099 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2100 .clkdm_name = "per_clkdm",
2103 DEFINE_STRUCT_CLK(mcbsp3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2105 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "per_clkdm", mcbsp_234_clksel,
2106 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2107 OMAP2_MCBSP4_CLKS_MASK,
2108 OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2109 OMAP3430_EN_MCBSP4_SHIFT, &clkhwops_wait,
2110 mcbsp2_fck_parent_names, clkout2_src_ck_ops);
2112 static struct clk mcbsp4_ick;
2114 static struct clk_hw_omap mcbsp4_ick_hw = {
2118 .ops = &clkhwops_iclk_wait,
2119 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2120 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2121 .clkdm_name = "per_clkdm",
2124 DEFINE_STRUCT_CLK(mcbsp4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2126 DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_15_clksel,
2127 OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2128 OMAP2_MCBSP5_CLKS_MASK,
2129 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2130 OMAP3430_EN_MCBSP5_SHIFT, &clkhwops_wait,
2131 mcbsp1_fck_parent_names, clkout2_src_ck_ops);
2133 static struct clk mcbsp5_ick;
2135 static struct clk_hw_omap mcbsp5_ick_hw = {
2139 .ops = &clkhwops_iclk_wait,
2140 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2141 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
2142 .clkdm_name = "core_l4_clkdm",
2145 DEFINE_STRUCT_CLK(mcbsp5_ick, aes2_ick_parent_names, aes2_ick_ops);
2147 static struct clk mcspi1_fck;
2149 static struct clk_hw_omap mcspi1_fck_hw = {
2153 .ops = &clkhwops_wait,
2154 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2155 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2156 .clkdm_name = "core_l4_clkdm",
2159 DEFINE_STRUCT_CLK(mcspi1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2161 static struct clk mcspi1_ick;
2163 static struct clk_hw_omap mcspi1_ick_hw = {
2167 .ops = &clkhwops_iclk_wait,
2168 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2169 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
2170 .clkdm_name = "core_l4_clkdm",
2173 DEFINE_STRUCT_CLK(mcspi1_ick, aes2_ick_parent_names, aes2_ick_ops);
2175 static struct clk mcspi2_fck;
2177 static struct clk_hw_omap mcspi2_fck_hw = {
2181 .ops = &clkhwops_wait,
2182 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2183 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2184 .clkdm_name = "core_l4_clkdm",
2187 DEFINE_STRUCT_CLK(mcspi2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2189 static struct clk mcspi2_ick;
2191 static struct clk_hw_omap mcspi2_ick_hw = {
2195 .ops = &clkhwops_iclk_wait,
2196 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2197 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
2198 .clkdm_name = "core_l4_clkdm",
2201 DEFINE_STRUCT_CLK(mcspi2_ick, aes2_ick_parent_names, aes2_ick_ops);
2203 static struct clk mcspi3_fck;
2205 static struct clk_hw_omap mcspi3_fck_hw = {
2209 .ops = &clkhwops_wait,
2210 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2211 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2212 .clkdm_name = "core_l4_clkdm",
2215 DEFINE_STRUCT_CLK(mcspi3_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2217 static struct clk mcspi3_ick;
2219 static struct clk_hw_omap mcspi3_ick_hw = {
2223 .ops = &clkhwops_iclk_wait,
2224 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2225 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
2226 .clkdm_name = "core_l4_clkdm",
2229 DEFINE_STRUCT_CLK(mcspi3_ick, aes2_ick_parent_names, aes2_ick_ops);
2231 static struct clk mcspi4_fck;
2233 static struct clk_hw_omap mcspi4_fck_hw = {
2237 .ops = &clkhwops_wait,
2238 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2239 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2240 .clkdm_name = "core_l4_clkdm",
2243 DEFINE_STRUCT_CLK(mcspi4_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2245 static struct clk mcspi4_ick;
2247 static struct clk_hw_omap mcspi4_ick_hw = {
2251 .ops = &clkhwops_iclk_wait,
2252 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2253 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
2254 .clkdm_name = "core_l4_clkdm",
2257 DEFINE_STRUCT_CLK(mcspi4_ick, aes2_ick_parent_names, aes2_ick_ops);
2259 static struct clk mmchs1_fck;
2261 static struct clk_hw_omap mmchs1_fck_hw = {
2265 .ops = &clkhwops_wait,
2266 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2267 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2268 .clkdm_name = "core_l4_clkdm",
2271 DEFINE_STRUCT_CLK(mmchs1_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2273 static struct clk mmchs1_ick;
2275 static struct clk_hw_omap mmchs1_ick_hw = {
2279 .ops = &clkhwops_iclk_wait,
2280 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2281 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
2282 .clkdm_name = "core_l4_clkdm",
2285 DEFINE_STRUCT_CLK(mmchs1_ick, aes2_ick_parent_names, aes2_ick_ops);
2287 static struct clk mmchs2_fck;
2289 static struct clk_hw_omap mmchs2_fck_hw = {
2293 .ops = &clkhwops_wait,
2294 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2295 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2296 .clkdm_name = "core_l4_clkdm",
2299 DEFINE_STRUCT_CLK(mmchs2_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2301 static struct clk mmchs2_ick;
2303 static struct clk_hw_omap mmchs2_ick_hw = {
2307 .ops = &clkhwops_iclk_wait,
2308 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2309 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
2310 .clkdm_name = "core_l4_clkdm",
2313 DEFINE_STRUCT_CLK(mmchs2_ick, aes2_ick_parent_names, aes2_ick_ops);
2315 static struct clk mmchs3_fck;
2317 static struct clk_hw_omap mmchs3_fck_hw = {
2321 .ops = &clkhwops_wait,
2322 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2323 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2324 .clkdm_name = "core_l4_clkdm",
2327 DEFINE_STRUCT_CLK(mmchs3_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2329 static struct clk mmchs3_ick;
2331 static struct clk_hw_omap mmchs3_ick_hw = {
2335 .ops = &clkhwops_iclk_wait,
2336 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2337 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
2338 .clkdm_name = "core_l4_clkdm",
2341 DEFINE_STRUCT_CLK(mmchs3_ick, aes2_ick_parent_names, aes2_ick_ops);
2343 static struct clk modem_fck;
2345 static struct clk_hw_omap modem_fck_hw = {
2349 .ops = &clkhwops_iclk_wait,
2350 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2351 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
2352 .clkdm_name = "d2d_clkdm",
2355 DEFINE_STRUCT_CLK(modem_fck, dpll3_ck_parent_names, aes2_ick_ops);
2357 static struct clk mspro_fck;
2359 static struct clk_hw_omap mspro_fck_hw = {
2363 .ops = &clkhwops_wait,
2364 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2365 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2366 .clkdm_name = "core_l4_clkdm",
2369 DEFINE_STRUCT_CLK(mspro_fck, csi2_96m_fck_parent_names, aes2_ick_ops);
2371 static struct clk mspro_ick;
2373 static struct clk_hw_omap mspro_ick_hw = {
2377 .ops = &clkhwops_iclk_wait,
2378 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2379 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
2380 .clkdm_name = "core_l4_clkdm",
2383 DEFINE_STRUCT_CLK(mspro_ick, aes2_ick_parent_names, aes2_ick_ops);
2385 static struct clk omap_192m_alwon_fck;
2387 DEFINE_STRUCT_CLK_HW_OMAP(omap_192m_alwon_fck, NULL);
2388 DEFINE_STRUCT_CLK(omap_192m_alwon_fck, omap_96m_alwon_fck_parent_names,
2391 static struct clk omap_32ksync_ick;
2393 static struct clk_hw_omap omap_32ksync_ick_hw = {
2395 .clk = &omap_32ksync_ick,
2397 .ops = &clkhwops_iclk_wait,
2398 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2399 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2400 .clkdm_name = "wkup_clkdm",
2403 DEFINE_STRUCT_CLK(omap_32ksync_ick, gpio1_ick_parent_names, aes2_ick_ops);
2405 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
2406 { .div = 1, .val = 1, .flags = RATE_IN_36XX },
2407 { .div = 2, .val = 2, .flags = RATE_IN_36XX },
2411 static const struct clksel omap_96m_alwon_fck_clksel[] = {
2412 { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
2416 static struct clk omap_96m_alwon_fck_3630;
2418 static const char *omap_96m_alwon_fck_3630_parent_names[] = {
2419 "omap_192m_alwon_fck",
2422 static const struct clk_ops omap_96m_alwon_fck_3630_ops = {
2423 .set_rate = &omap2_clksel_set_rate,
2424 .recalc_rate = &omap2_clksel_recalc,
2425 .round_rate = &omap2_clksel_round_rate,
2428 static struct clk_hw_omap omap_96m_alwon_fck_3630_hw = {
2430 .clk = &omap_96m_alwon_fck_3630,
2432 .clksel = omap_96m_alwon_fck_clksel,
2433 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2434 .clksel_mask = OMAP3630_CLKSEL_96M_MASK,
2437 static struct clk omap_96m_alwon_fck_3630 = {
2438 .name = "omap_96m_alwon_fck",
2439 .hw = &omap_96m_alwon_fck_3630_hw.hw,
2440 .parent_names = omap_96m_alwon_fck_3630_parent_names,
2441 .num_parents = ARRAY_SIZE(omap_96m_alwon_fck_3630_parent_names),
2442 .ops = &omap_96m_alwon_fck_3630_ops,
2445 static struct clk omapctrl_ick;
2447 static struct clk_hw_omap omapctrl_ick_hw = {
2449 .clk = &omapctrl_ick,
2451 .ops = &clkhwops_iclk_wait,
2452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2453 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
2454 .flags = ENABLE_ON_INIT,
2455 .clkdm_name = "core_l4_clkdm",
2458 DEFINE_STRUCT_CLK(omapctrl_ick, aes2_ick_parent_names, aes2_ick_ops);
2460 DEFINE_CLK_DIVIDER(pclk_fck, "emu_src_ck", &emu_src_ck, 0x0,
2461 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2462 OMAP3430_CLKSEL_PCLK_SHIFT, OMAP3430_CLKSEL_PCLK_WIDTH,
2463 CLK_DIVIDER_ONE_BASED, NULL);
2465 DEFINE_CLK_DIVIDER(pclkx2_fck, "emu_src_ck", &emu_src_ck, 0x0,
2466 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2467 OMAP3430_CLKSEL_PCLKX2_SHIFT, OMAP3430_CLKSEL_PCLKX2_WIDTH,
2468 CLK_DIVIDER_ONE_BASED, NULL);
2470 static struct clk per_48m_fck;
2472 DEFINE_STRUCT_CLK_HW_OMAP(per_48m_fck, "per_clkdm");
2473 DEFINE_STRUCT_CLK(per_48m_fck, core_48m_fck_parent_names, core_l4_ick_ops);
2475 static struct clk security_l3_ick;
2477 DEFINE_STRUCT_CLK_HW_OMAP(security_l3_ick, NULL);
2478 DEFINE_STRUCT_CLK(security_l3_ick, core_l3_ick_parent_names, core_ck_ops);
2480 static struct clk pka_ick;
2482 static const char *pka_ick_parent_names[] = {
2486 static struct clk_hw_omap pka_ick_hw = {
2490 .ops = &clkhwops_iclk_wait,
2491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2492 .enable_bit = OMAP3430_EN_PKA_SHIFT,
2495 DEFINE_STRUCT_CLK(pka_ick, pka_ick_parent_names, aes1_ick_ops);
2497 DEFINE_CLK_DIVIDER(rm_ick, "l4_ick", &l4_ick, 0x0,
2498 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2499 OMAP3430_CLKSEL_RM_SHIFT, OMAP3430_CLKSEL_RM_WIDTH,
2500 CLK_DIVIDER_ONE_BASED, NULL);
2502 static struct clk rng_ick;
2504 static struct clk_hw_omap rng_ick_hw = {
2508 .ops = &clkhwops_iclk_wait,
2509 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2510 .enable_bit = OMAP3430_EN_RNG_SHIFT,
2513 DEFINE_STRUCT_CLK(rng_ick, aes1_ick_parent_names, aes1_ick_ops);
2515 static struct clk sad2d_ick;
2517 static struct clk_hw_omap sad2d_ick_hw = {
2521 .ops = &clkhwops_iclk_wait,
2522 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2523 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
2524 .clkdm_name = "d2d_clkdm",
2527 DEFINE_STRUCT_CLK(sad2d_ick, core_l3_ick_parent_names, aes2_ick_ops);
2529 static struct clk sdrc_ick;
2531 static struct clk_hw_omap sdrc_ick_hw = {
2535 .ops = &clkhwops_wait,
2536 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2537 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
2538 .flags = ENABLE_ON_INIT,
2539 .clkdm_name = "core_l3_clkdm",
2542 DEFINE_STRUCT_CLK(sdrc_ick, ipss_ick_parent_names, aes2_ick_ops);
2544 static const struct clksel_rate sgx_core_rates[] = {
2545 { .div = 2, .val = 5, .flags = RATE_IN_36XX },
2546 { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
2547 { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
2548 { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
2552 static const struct clksel_rate sgx_96m_rates[] = {
2553 { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2557 static const struct clksel_rate sgx_192m_rates[] = {
2558 { .div = 1, .val = 4, .flags = RATE_IN_36XX },
2562 static const struct clksel_rate sgx_corex2_rates[] = {
2563 { .div = 3, .val = 6, .flags = RATE_IN_36XX },
2564 { .div = 5, .val = 7, .flags = RATE_IN_36XX },
2568 static const struct clksel sgx_clksel[] = {
2569 { .parent = &core_ck, .rates = sgx_core_rates },
2570 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
2571 { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
2572 { .parent = &corex2_fck, .rates = sgx_corex2_rates },
2576 static const char *sgx_fck_parent_names[] = {
2577 "core_ck", "cm_96m_fck", "omap_192m_alwon_fck", "corex2_fck",
2580 static struct clk sgx_fck;
2582 static const struct clk_ops sgx_fck_ops = {
2583 .init = &omap2_init_clk_clkdm,
2584 .enable = &omap2_dflt_clk_enable,
2585 .disable = &omap2_dflt_clk_disable,
2586 .is_enabled = &omap2_dflt_clk_is_enabled,
2587 .recalc_rate = &omap2_clksel_recalc,
2588 .set_rate = &omap2_clksel_set_rate,
2589 .round_rate = &omap2_clksel_round_rate,
2590 .get_parent = &omap2_clksel_find_parent_index,
2591 .set_parent = &omap2_clksel_set_parent,
2594 DEFINE_CLK_OMAP_MUX_GATE(sgx_fck, "sgx_clkdm", sgx_clksel,
2595 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
2596 OMAP3430ES2_CLKSEL_SGX_MASK,
2597 OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
2598 OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
2599 &clkhwops_wait, sgx_fck_parent_names, sgx_fck_ops);
2601 static struct clk sgx_ick;
2603 static struct clk_hw_omap sgx_ick_hw = {
2607 .ops = &clkhwops_wait,
2608 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
2609 .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
2610 .clkdm_name = "sgx_clkdm",
2613 DEFINE_STRUCT_CLK(sgx_ick, core_l3_ick_parent_names, aes2_ick_ops);
2615 static struct clk sha11_ick;
2617 static struct clk_hw_omap sha11_ick_hw = {
2621 .ops = &clkhwops_iclk_wait,
2622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2623 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
2626 DEFINE_STRUCT_CLK(sha11_ick, aes1_ick_parent_names, aes1_ick_ops);
2628 static struct clk sha12_ick;
2630 static struct clk_hw_omap sha12_ick_hw = {
2634 .ops = &clkhwops_iclk_wait,
2635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2636 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
2637 .clkdm_name = "core_l4_clkdm",
2640 DEFINE_STRUCT_CLK(sha12_ick, aes2_ick_parent_names, aes2_ick_ops);
2642 static struct clk sr1_fck;
2644 static struct clk_hw_omap sr1_fck_hw = {
2648 .ops = &clkhwops_wait,
2649 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2650 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2651 .clkdm_name = "wkup_clkdm",
2654 DEFINE_STRUCT_CLK(sr1_fck, dpll3_ck_parent_names, aes2_ick_ops);
2656 static struct clk sr2_fck;
2658 static struct clk_hw_omap sr2_fck_hw = {
2662 .ops = &clkhwops_wait,
2663 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2664 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2665 .clkdm_name = "wkup_clkdm",
2668 DEFINE_STRUCT_CLK(sr2_fck, dpll3_ck_parent_names, aes2_ick_ops);
2670 static struct clk sr_l4_ick;
2672 DEFINE_STRUCT_CLK_HW_OMAP(sr_l4_ick, "core_l4_clkdm");
2673 DEFINE_STRUCT_CLK(sr_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2675 static struct clk ssi_l4_ick;
2677 DEFINE_STRUCT_CLK_HW_OMAP(ssi_l4_ick, "core_l4_clkdm");
2678 DEFINE_STRUCT_CLK(ssi_l4_ick, security_l4_ick2_parent_names, core_l4_ick_ops);
2680 static struct clk ssi_ick_3430es1;
2682 static const char *ssi_ick_3430es1_parent_names[] = {
2686 static struct clk_hw_omap ssi_ick_3430es1_hw = {
2688 .clk = &ssi_ick_3430es1,
2690 .ops = &clkhwops_iclk,
2691 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2692 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2693 .clkdm_name = "core_l4_clkdm",
2696 DEFINE_STRUCT_CLK(ssi_ick_3430es1, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2698 static struct clk ssi_ick_3430es2;
2700 static struct clk_hw_omap ssi_ick_3430es2_hw = {
2702 .clk = &ssi_ick_3430es2,
2704 .ops = &clkhwops_omap3430es2_iclk_ssi_wait,
2705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2706 .enable_bit = OMAP3430_EN_SSI_SHIFT,
2707 .clkdm_name = "core_l4_clkdm",
2710 DEFINE_STRUCT_CLK(ssi_ick_3430es2, ssi_ick_3430es1_parent_names, aes2_ick_ops);
2712 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
2713 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2714 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2715 { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2716 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2717 { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2718 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
2722 static const struct clksel ssi_ssr_clksel[] = {
2723 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
2727 static const char *ssi_ssr_fck_3430es1_parent_names[] = {
2731 static const struct clk_ops ssi_ssr_fck_3430es1_ops = {
2732 .init = &omap2_init_clk_clkdm,
2733 .enable = &omap2_dflt_clk_enable,
2734 .disable = &omap2_dflt_clk_disable,
2735 .is_enabled = &omap2_dflt_clk_is_enabled,
2736 .recalc_rate = &omap2_clksel_recalc,
2737 .set_rate = &omap2_clksel_set_rate,
2738 .round_rate = &omap2_clksel_round_rate,
2741 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es1, "core_l4_clkdm",
2742 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2743 OMAP3430_CLKSEL_SSI_MASK,
2744 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2745 OMAP3430_EN_SSI_SHIFT,
2746 NULL, ssi_ssr_fck_3430es1_parent_names,
2747 ssi_ssr_fck_3430es1_ops);
2749 DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_fck_3430es2, "core_l4_clkdm",
2750 ssi_ssr_clksel, OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2751 OMAP3430_CLKSEL_SSI_MASK,
2752 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2753 OMAP3430_EN_SSI_SHIFT,
2754 NULL, ssi_ssr_fck_3430es1_parent_names,
2755 ssi_ssr_fck_3430es1_ops);
2757 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es1, "ssi_ssr_fck_3430es1",
2758 &ssi_ssr_fck_3430es1, 0x0, 1, 2);
2760 DEFINE_CLK_FIXED_FACTOR(ssi_sst_fck_3430es2, "ssi_ssr_fck_3430es2",
2761 &ssi_ssr_fck_3430es2, 0x0, 1, 2);
2763 static struct clk sys_clkout1;
2765 static const char *sys_clkout1_parent_names[] = {
2769 static struct clk_hw_omap sys_clkout1_hw = {
2771 .clk = &sys_clkout1,
2773 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
2774 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
2777 DEFINE_STRUCT_CLK(sys_clkout1, sys_clkout1_parent_names, aes1_ick_ops);
2779 DEFINE_CLK_DIVIDER(sys_clkout2, "clkout2_src_ck", &clkout2_src_ck, 0x0,
2780 OMAP3430_CM_CLKOUT_CTRL, OMAP3430_CLKOUT2_DIV_SHIFT,
2781 OMAP3430_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
2783 DEFINE_CLK_MUX(traceclk_src_fck, emu_src_ck_parent_names, NULL, 0x0,
2784 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2785 OMAP3430_TRACE_MUX_CTRL_SHIFT, OMAP3430_TRACE_MUX_CTRL_WIDTH,
2788 DEFINE_CLK_DIVIDER(traceclk_fck, "traceclk_src_fck", &traceclk_src_fck, 0x0,
2789 OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2790 OMAP3430_CLKSEL_TRACECLK_SHIFT,
2791 OMAP3430_CLKSEL_TRACECLK_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
2793 static struct clk ts_fck;
2795 static struct clk_hw_omap ts_fck_hw = {
2799 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
2800 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
2801 .clkdm_name = "core_l4_clkdm",
2804 DEFINE_STRUCT_CLK(ts_fck, wkup_32k_fck_parent_names, aes2_ick_ops);
2806 static struct clk uart1_fck;
2808 static struct clk_hw_omap uart1_fck_hw = {
2812 .ops = &clkhwops_wait,
2813 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2814 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2815 .clkdm_name = "core_l4_clkdm",
2818 DEFINE_STRUCT_CLK(uart1_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2820 static struct clk uart1_ick;
2822 static struct clk_hw_omap uart1_ick_hw = {
2826 .ops = &clkhwops_iclk_wait,
2827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2828 .enable_bit = OMAP3430_EN_UART1_SHIFT,
2829 .clkdm_name = "core_l4_clkdm",
2832 DEFINE_STRUCT_CLK(uart1_ick, aes2_ick_parent_names, aes2_ick_ops);
2834 static struct clk uart2_fck;
2836 static struct clk_hw_omap uart2_fck_hw = {
2840 .ops = &clkhwops_wait,
2841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2842 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2843 .clkdm_name = "core_l4_clkdm",
2846 DEFINE_STRUCT_CLK(uart2_fck, fshostusb_fck_parent_names, aes2_ick_ops);
2848 static struct clk uart2_ick;
2850 static struct clk_hw_omap uart2_ick_hw = {
2854 .ops = &clkhwops_iclk_wait,
2855 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2856 .enable_bit = OMAP3430_EN_UART2_SHIFT,
2857 .clkdm_name = "core_l4_clkdm",
2860 DEFINE_STRUCT_CLK(uart2_ick, aes2_ick_parent_names, aes2_ick_ops);
2862 static struct clk uart3_fck;
2864 static const char *uart3_fck_parent_names[] = {
2868 static struct clk_hw_omap uart3_fck_hw = {
2872 .ops = &clkhwops_wait,
2873 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2874 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2875 .clkdm_name = "per_clkdm",
2878 DEFINE_STRUCT_CLK(uart3_fck, uart3_fck_parent_names, aes2_ick_ops);
2880 static struct clk uart3_ick;
2882 static struct clk_hw_omap uart3_ick_hw = {
2886 .ops = &clkhwops_iclk_wait,
2887 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2888 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2889 .clkdm_name = "per_clkdm",
2892 DEFINE_STRUCT_CLK(uart3_ick, gpio2_ick_parent_names, aes2_ick_ops);
2894 static struct clk uart4_fck;
2896 static struct clk_hw_omap uart4_fck_hw = {
2900 .ops = &clkhwops_wait,
2901 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2902 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2903 .clkdm_name = "per_clkdm",
2906 DEFINE_STRUCT_CLK(uart4_fck, uart3_fck_parent_names, aes2_ick_ops);
2908 static struct clk uart4_fck_am35xx;
2910 static struct clk_hw_omap uart4_fck_am35xx_hw = {
2912 .clk = &uart4_fck_am35xx,
2914 .ops = &clkhwops_wait,
2915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2916 .enable_bit = AM35XX_EN_UART4_SHIFT,
2917 .clkdm_name = "core_l4_clkdm",
2920 DEFINE_STRUCT_CLK(uart4_fck_am35xx, fshostusb_fck_parent_names, aes2_ick_ops);
2922 static struct clk uart4_ick;
2924 static struct clk_hw_omap uart4_ick_hw = {
2928 .ops = &clkhwops_iclk_wait,
2929 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2930 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2931 .clkdm_name = "per_clkdm",
2934 DEFINE_STRUCT_CLK(uart4_ick, gpio2_ick_parent_names, aes2_ick_ops);
2936 static struct clk uart4_ick_am35xx;
2938 static struct clk_hw_omap uart4_ick_am35xx_hw = {
2940 .clk = &uart4_ick_am35xx,
2942 .ops = &clkhwops_iclk_wait,
2943 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2944 .enable_bit = AM35XX_EN_UART4_SHIFT,
2945 .clkdm_name = "core_l4_clkdm",
2948 DEFINE_STRUCT_CLK(uart4_ick_am35xx, aes2_ick_parent_names, aes2_ick_ops);
2950 static const struct clksel_rate div2_rates[] = {
2951 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2952 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2956 static const struct clksel usb_l4_clksel[] = {
2957 { .parent = &l4_ick, .rates = div2_rates },
2961 static const char *usb_l4_ick_parent_names[] = {
2965 DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_clksel,
2966 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2967 OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2968 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2969 OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2970 &clkhwops_iclk_wait, usb_l4_ick_parent_names,
2971 ssi_ssr_fck_3430es1_ops);
2973 static struct clk usbhost_120m_fck;
2975 static const char *usbhost_120m_fck_parent_names[] = {
2979 static struct clk_hw_omap usbhost_120m_fck_hw = {
2981 .clk = &usbhost_120m_fck,
2983 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2984 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2985 .clkdm_name = "usbhost_clkdm",
2988 DEFINE_STRUCT_CLK(usbhost_120m_fck, usbhost_120m_fck_parent_names,
2991 static struct clk usbhost_48m_fck;
2993 static struct clk_hw_omap usbhost_48m_fck_hw = {
2995 .clk = &usbhost_48m_fck,
2997 .ops = &clkhwops_omap3430es2_dss_usbhost_wait,
2998 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2999 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
3000 .clkdm_name = "usbhost_clkdm",
3003 DEFINE_STRUCT_CLK(usbhost_48m_fck, core_48m_fck_parent_names, aes2_ick_ops);
3005 static struct clk usbhost_ick;
3007 static struct clk_hw_omap usbhost_ick_hw = {
3009 .clk = &usbhost_ick,
3011 .ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait,
3012 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
3013 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
3014 .clkdm_name = "usbhost_clkdm",
3017 DEFINE_STRUCT_CLK(usbhost_ick, security_l4_ick2_parent_names, aes2_ick_ops);
3019 static struct clk usbtll_fck;
3021 static struct clk_hw_omap usbtll_fck_hw = {
3025 .ops = &clkhwops_wait,
3026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
3027 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3028 .clkdm_name = "core_l4_clkdm",
3031 DEFINE_STRUCT_CLK(usbtll_fck, usbhost_120m_fck_parent_names, aes2_ick_ops);
3033 static struct clk usbtll_ick;
3035 static struct clk_hw_omap usbtll_ick_hw = {
3039 .ops = &clkhwops_iclk_wait,
3040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
3041 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
3042 .clkdm_name = "core_l4_clkdm",
3045 DEFINE_STRUCT_CLK(usbtll_ick, aes2_ick_parent_names, aes2_ick_ops);
3047 static const struct clksel_rate usim_96m_rates[] = {
3048 { .div = 2, .val = 3, .flags = RATE_IN_3XXX },
3049 { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3050 { .div = 8, .val = 5, .flags = RATE_IN_3XXX },
3051 { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
3055 static const struct clksel_rate usim_120m_rates[] = {
3056 { .div = 4, .val = 7, .flags = RATE_IN_3XXX },
3057 { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
3058 { .div = 16, .val = 9, .flags = RATE_IN_3XXX },
3059 { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
3063 static const struct clksel usim_clksel[] = {
3064 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
3065 { .parent = &dpll5_m2_ck, .rates = usim_120m_rates },
3066 { .parent = &sys_ck, .rates = div2_rates },
3070 static const char *usim_fck_parent_names[] = {
3071 "omap_96m_fck", "dpll5_m2_ck", "sys_ck",
3074 static struct clk usim_fck;
3076 static const struct clk_ops usim_fck_ops = {
3077 .enable = &omap2_dflt_clk_enable,
3078 .disable = &omap2_dflt_clk_disable,
3079 .is_enabled = &omap2_dflt_clk_is_enabled,
3080 .recalc_rate = &omap2_clksel_recalc,
3081 .get_parent = &omap2_clksel_find_parent_index,
3082 .set_parent = &omap2_clksel_set_parent,
3085 DEFINE_CLK_OMAP_MUX_GATE(usim_fck, NULL, usim_clksel,
3086 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
3087 OMAP3430ES2_CLKSEL_USIMOCP_MASK,
3088 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3089 OMAP3430ES2_EN_USIMOCP_SHIFT, &clkhwops_wait,
3090 usim_fck_parent_names, usim_fck_ops);
3092 static struct clk usim_ick;
3094 static struct clk_hw_omap usim_ick_hw = {
3098 .ops = &clkhwops_iclk_wait,
3099 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3100 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
3101 .clkdm_name = "wkup_clkdm",
3104 DEFINE_STRUCT_CLK(usim_ick, gpio1_ick_parent_names, aes2_ick_ops);
3106 static struct clk vpfe_fck;
3108 static const char *vpfe_fck_parent_names[] = {
3112 static struct clk_hw_omap vpfe_fck_hw = {
3116 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3117 .enable_bit = AM35XX_VPFE_FCLK_SHIFT,
3120 DEFINE_STRUCT_CLK(vpfe_fck, vpfe_fck_parent_names, aes1_ick_ops);
3122 static struct clk vpfe_ick;
3124 static struct clk_hw_omap vpfe_ick_hw = {
3128 .ops = &clkhwops_am35xx_ipss_module_wait,
3129 .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3130 .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3131 .clkdm_name = "core_l3_clkdm",
3134 DEFINE_STRUCT_CLK(vpfe_ick, emac_ick_parent_names, aes2_ick_ops);
3136 static struct clk wdt1_fck;
3138 DEFINE_STRUCT_CLK_HW_OMAP(wdt1_fck, "wkup_clkdm");
3139 DEFINE_STRUCT_CLK(wdt1_fck, gpt12_fck_parent_names, core_l4_ick_ops);
3141 static struct clk wdt1_ick;
3143 static struct clk_hw_omap wdt1_ick_hw = {
3147 .ops = &clkhwops_iclk_wait,
3148 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3149 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
3150 .clkdm_name = "wkup_clkdm",
3153 DEFINE_STRUCT_CLK(wdt1_ick, gpio1_ick_parent_names, aes2_ick_ops);
3155 static struct clk wdt2_fck;
3157 static struct clk_hw_omap wdt2_fck_hw = {
3161 .ops = &clkhwops_wait,
3162 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3163 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3164 .clkdm_name = "wkup_clkdm",
3167 DEFINE_STRUCT_CLK(wdt2_fck, gpio1_dbck_parent_names, aes2_ick_ops);
3169 static struct clk wdt2_ick;
3171 static struct clk_hw_omap wdt2_ick_hw = {
3175 .ops = &clkhwops_iclk_wait,
3176 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
3177 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
3178 .clkdm_name = "wkup_clkdm",
3181 DEFINE_STRUCT_CLK(wdt2_ick, gpio1_ick_parent_names, aes2_ick_ops);
3183 static struct clk wdt3_fck;
3185 static struct clk_hw_omap wdt3_fck_hw = {
3189 .ops = &clkhwops_wait,
3190 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
3191 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3192 .clkdm_name = "per_clkdm",
3195 DEFINE_STRUCT_CLK(wdt3_fck, gpio2_dbck_parent_names, aes2_ick_ops);
3197 static struct clk wdt3_ick;
3199 static struct clk_hw_omap wdt3_ick_hw = {
3203 .ops = &clkhwops_iclk_wait,
3204 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
3205 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
3206 .clkdm_name = "per_clkdm",
3209 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
3214 static struct omap_clk omap3xxx_clks[] = {
3215 CLK(NULL, "apb_pclk", &dummy_apb_pclk, CK_3XXX),
3216 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3217 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3218 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3219 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3220 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
3221 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
3222 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3223 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3224 CLK("twl", "fck", &osc_sys_ck, CK_3XXX),
3225 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3226 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3227 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3228 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3229 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3230 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3231 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3232 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3233 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3234 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3235 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3236 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
3237 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_3XXX),
3238 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3239 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_3XXX),
3240 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3241 CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3242 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_3XXX),
3243 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_3XXX),
3244 CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3245 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3246 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_3XXX),
3247 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_3XXX),
3248 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_3XXX),
3249 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_3XXX),
3250 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_3XXX),
3251 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_3XXX),
3252 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3253 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_3XXX),
3254 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3255 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_3XXX),
3256 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3257 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_3XXX),
3258 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3259 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3260 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3261 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3262 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3263 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3264 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3265 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3266 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
3267 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX),
3268 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3269 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3270 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3271 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3272 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3273 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3274 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3275 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
3276 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
3277 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
3278 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3279 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3280 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3281 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3282 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3283 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3284 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3285 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3286 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3287 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3288 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3289 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3292 CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3293 CLK("usbhs_tll", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3295 CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3296 CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
3297 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3298 CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
3299 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
3300 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
3301 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
3302 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
3303 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
3304 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
3305 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
3306 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
3307 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
3308 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
3309 CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
3310 CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
3311 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3312 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3313 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3314 CLK(NULL, "hdq_fck", &hdq_fck, CK_3XXX),
3315 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3316 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3317 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3318 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3319 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3320 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3321 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3322 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3323 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3324 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3325 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3326 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3327 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3328 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3329 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3330 CLK("usbhs_omap", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3331 CLK("usbhs_tll", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3332 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3333 CLK(NULL, "mmchs3_ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3334 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3335 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3336 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3337 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3338 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3339 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3340 CLK(NULL, "mmchs2_ick", &mmchs2_ick, CK_3XXX),
3341 CLK(NULL, "mmchs1_ick", &mmchs1_ick, CK_3XXX),
3342 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3343 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3344 CLK(NULL, "hdq_ick", &hdq_ick, CK_3XXX),
3345 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3346 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3347 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3348 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3349 CLK(NULL, "mcspi4_ick", &mcspi4_ick, CK_3XXX),
3350 CLK(NULL, "mcspi3_ick", &mcspi3_ick, CK_3XXX),
3351 CLK(NULL, "mcspi2_ick", &mcspi2_ick, CK_3XXX),
3352 CLK(NULL, "mcspi1_ick", &mcspi1_ick, CK_3XXX),
3353 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3354 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3355 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3356 CLK(NULL, "i2c3_ick", &i2c3_ick, CK_3XXX),
3357 CLK(NULL, "i2c2_ick", &i2c2_ick, CK_3XXX),
3358 CLK(NULL, "i2c1_ick", &i2c1_ick, CK_3XXX),
3359 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3360 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3361 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
3362 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_3XXX),
3363 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3364 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3365 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick, CK_3XXX),
3366 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick, CK_3XXX),
3367 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3368 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3369 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3370 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3371 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3372 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3373 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3374 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3375 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3376 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3377 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3378 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3379 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3380 CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3381 CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
3382 CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
3383 CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
3384 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3385 CLK(NULL, "dss_ick", &dss_ick_3430es1, CK_3430ES1),
3386 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3387 CLK(NULL, "dss_ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3388 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3389 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3390 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3391 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3392 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3393 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3394 CLK("usbhs_omap", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3395 CLK(NULL, "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3396 CLK(NULL, "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3397 CLK(NULL, "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3398 CLK(NULL, "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3399 CLK(NULL, "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3400 CLK(NULL, "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3401 CLK("usbhs_omap", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3402 CLK("usbhs_omap", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3403 CLK("usbhs_tll", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3404 CLK("usbhs_tll", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3405 CLK(NULL, "init_60m_fclk", &dummy_ck, CK_3XXX),
3406 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3407 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3408 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3409 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3410 CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
3411 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3412 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3413 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3414 CLK(NULL, "wdt2_ick", &wdt2_ick, CK_3XXX),
3415 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3416 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3417 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3418 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3419 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3420 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3421 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3422 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3423 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3424 CLK(NULL, "uart4_fck", &uart4_fck_am35xx, CK_AM35XX),
3425 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3426 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3427 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
3428 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_3XXX),
3429 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_3XXX),
3430 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_3XXX),
3431 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_3XXX),
3432 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_3XXX),
3433 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3434 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_3XXX),
3435 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_3XXX),
3436 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_3XXX),
3437 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_3XXX),
3438 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_3XXX),
3439 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_3XXX),
3440 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_3XXX),
3441 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_3XXX),
3442 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_3XXX),
3443 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_3XXX),
3444 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_3XXX),
3445 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3446 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3447 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3448 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3449 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3450 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3451 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
3452 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_3XXX),
3453 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_3XXX),
3454 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_3XXX),
3455 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_3XXX),
3456 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_3XXX),
3457 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
3458 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
3459 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
3460 CLK(NULL, "mcbsp4_ick", &mcbsp2_ick, CK_3XXX),
3461 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick, CK_3XXX),
3462 CLK(NULL, "mcbsp2_ick", &mcbsp4_ick, CK_3XXX),
3463 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
3464 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
3465 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
3466 CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
3467 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_3XXX),
3468 CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
3469 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
3470 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3471 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3472 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3473 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3474 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3475 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3476 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3477 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3478 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
3479 CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX),
3480 CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX),
3481 CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX),
3482 CLK(NULL, "emac_ick", &emac_ick, CK_AM35XX),
3483 CLK(NULL, "emac_fck", &emac_fck, CK_AM35XX),
3484 CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX),
3485 CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX),
3486 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3487 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3488 CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3489 CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3490 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3491 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3492 CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX),
3493 CLK(NULL, "timer_sys_ck", &sys_ck, CK_3XXX),
3494 CLK(NULL, "cpufreq_ck", &dpll1_ck, CK_3XXX),
3497 static const char *enable_init_clks[] = {
3503 int __init omap3xxx_clk_init(void)
3509 * 3505 must be tested before 3517, since 3517 returns true
3510 * for both AM3517 chips and AM3517 family chips, which
3511 * includes 3505. Unfortunately there's no obvious family
3512 * test for 3517/3505 :-(
3514 if (soc_is_am35xx()) {
3515 cpu_mask = RATE_IN_34XX;
3516 cpu_clkflg = CK_AM35XX;
3517 } else if (cpu_is_omap3630()) {
3518 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3519 cpu_clkflg = CK_36XX;
3520 } else if (cpu_is_ti816x()) {
3521 cpu_mask = RATE_IN_TI816X;
3522 cpu_clkflg = CK_TI816X;
3523 } else if (soc_is_am33xx()) {
3524 cpu_mask = RATE_IN_AM33XX;
3525 } else if (cpu_is_ti814x()) {
3526 cpu_mask = RATE_IN_TI814X;
3527 } else if (cpu_is_omap34xx()) {
3528 if (omap_rev() == OMAP3430_REV_ES1_0) {
3529 cpu_mask = RATE_IN_3430ES1;
3530 cpu_clkflg = CK_3430ES1;
3533 * Assume that anything that we haven't matched yet
3534 * has 3430ES2-type clocks.
3536 cpu_mask = RATE_IN_3430ES2PLUS;
3537 cpu_clkflg = CK_3430ES2PLUS;
3540 WARN(1, "clock: could not identify OMAP3 variant\n");
3543 if (omap3_has_192mhz_clk())
3544 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3546 if (cpu_is_omap3630()) {
3547 dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
3548 dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
3549 dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
3550 dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
3551 dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
3552 dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
3556 * XXX This type of dynamic rewriting of the clock tree is
3557 * deprecated and should be revised soon.
3559 if (cpu_is_omap3630())
3560 dpll4_dd = dpll4_dd_3630;
3562 dpll4_dd = dpll4_dd_34xx;
3564 for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3566 if (c->cpu & cpu_clkflg) {
3568 if (!__clk_init(NULL, c->lk.clk))
3569 omap2_init_clk_hw_omap_clocks(c->lk.clk);
3572 omap2_clk_disable_autoidle_all();
3574 omap2_clk_enable_init_clocks(enable_init_clks,
3575 ARRAY_SIZE(enable_init_clks));
3577 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3578 (clk_get_rate(&osc_sys_ck) / 1000000),
3579 (clk_get_rate(&osc_sys_ck) / 100000) % 10,
3580 (clk_get_rate(&core_ck) / 1000000),
3581 (clk_get_rate(&arm_fck) / 1000000));
3584 * Lock DPLL5 -- here only until other device init code can
3587 if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3588 omap3_clk_lock_dpll5();
3590 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3591 sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3592 arm_fck_p = clk_get(NULL, "arm_fck");