arch/arm/mach-omap2/cm3xxx.c

   1 /*
   2  * OMAP3xxx CM module functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20
  21 #include "soc.h"
  22 #include "iomap.h"
  23 #include "common.h"
  24 #include "prm2xxx_3xxx.h"
  25 #include "cm.h"
  26 #include "cm3xxx.h"
  27 #include "cm-regbits-34xx.h"
  28 #include "clockdomain.h"
  29
  30 static const u8 omap3xxx_cm_idlest_offs[] = {
  31         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
  32 };
  33
  34 /*
  35  *
  36  */
  37
  38 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
  39 {
  40         u32 v;
  41
  42         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  43         v &= ~mask;
  44         v |= c << __ffs(mask);
  45         omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
  46 }
  47
  48 bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
  49 {
  50         u32 v;
  51
  52         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  53         v &= mask;
  54         v >>= __ffs(mask);
  55
  56         return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
  57 }
  58
  59 void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
  60 {
  61         _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
  62 }
  63
  64 void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
  65 {
  66         _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
  67 }
  68
  69 void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
  70 {
  71         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
  72 }
  73
  74 void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
  75 {
  76         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
  77 }
  78
  79 /*
  80  *
  81  */
  82
  83 /**
  84  * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
  85  * @prcm_mod: PRCM module offset
  86  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
  87  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
  88  *
  89  * Wait for the PRCM to indicate that the module identified by
  90  * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
  91  * success or -EBUSY if the module doesn't enable in time.
  92  */
  93 int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
  94 {
  95         int ena = 0, i = 0;
  96         u8 cm_idlest_reg;
  97         u32 mask;
  98
  99         if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
 100                 return -EINVAL;
 101
 102         cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
 103
 104         mask = 1 << idlest_shift;
 105         ena = 0;
 106
 107         omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
 108                             mask) == ena), MAX_MODULE_READY_TIME, i);
 109
 110         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 111 }
 112
 113 /* Clockdomain low-level operations */
 114
 115 static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
 116                                        struct clockdomain *clkdm2)
 117 {
 118         omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
 119                                   clkdm1->pwrdm.ptr->prcm_offs,
 120                                   OMAP3430_CM_SLEEPDEP);
 121         return 0;
 122 }
 123
 124 static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
 125                                        struct clockdomain *clkdm2)
 126 {
 127         omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
 128                                     clkdm1->pwrdm.ptr->prcm_offs,
 129                                     OMAP3430_CM_SLEEPDEP);
 130         return 0;
 131 }
 132
 133 static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
 134                                         struct clockdomain *clkdm2)
 135 {
 136         return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
 137                                             OMAP3430_CM_SLEEPDEP,
 138                                             (1 << clkdm2->dep_bit));
 139 }
 140
 141 static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
 142 {
 143         struct clkdm_dep *cd;
 144         u32 mask = 0;
 145
 146         for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
 147                 if (!cd->clkdm)
 148                         continue; /* only happens if data is erroneous */
 149
 150                 mask |= 1 << cd->clkdm->dep_bit;
 151                 atomic_set(&cd->sleepdep_usecount, 0);
 152         }
 153         omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
 154                                     OMAP3430_CM_SLEEPDEP);
 155         return 0;
 156 }
 157
 158 static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
 159 {
 160         omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
 161                                       clkdm->clktrctrl_mask);
 162         return 0;
 163 }
 164
 165 static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
 166 {
 167         omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
 168                                        clkdm->clktrctrl_mask);
 169         return 0;
 170 }
 171
 172 static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
 173 {
 174         if (atomic_read(&clkdm->usecount) > 0)
 175                 _clkdm_add_autodeps(clkdm);
 176
 177         omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 178                                        clkdm->clktrctrl_mask);
 179 }
 180
 181 static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
 182 {
 183         omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 184                                         clkdm->clktrctrl_mask);
 185
 186         if (atomic_read(&clkdm->usecount) > 0)
 187                 _clkdm_del_autodeps(clkdm);
 188 }
 189
 190 static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
 191 {
 192         bool hwsup = false;
 193
 194         if (!clkdm->clktrctrl_mask)
 195                 return 0;
 196
 197         /*
 198          * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
 199          * more details on the unpleasant problem this is working
 200          * around
 201          */
 202         if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
 203             (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
 204                 omap3xxx_clkdm_wakeup(clkdm);
 205                 return 0;
 206         }
 207
 208         hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 209                                               clkdm->clktrctrl_mask);
 210
 211         if (hwsup) {
 212                 /* Disable HW transitions when we are changing deps */
 213                 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 214                                                 clkdm->clktrctrl_mask);
 215                 _clkdm_add_autodeps(clkdm);
 216                 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 217                                                clkdm->clktrctrl_mask);
 218         } else {
 219                 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
 220                         omap3xxx_clkdm_wakeup(clkdm);
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
 227 {
 228         bool hwsup = false;
 229
 230         if (!clkdm->clktrctrl_mask)
 231                 return 0;
 232
 233         /*
 234          * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
 235          * more details on the unpleasant problem this is working
 236          * around
 237          */
 238         if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
 239             !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
 240                 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 241                                                clkdm->clktrctrl_mask);
 242                 return 0;
 243         }
 244
 245         hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 246                                               clkdm->clktrctrl_mask);
 247
 248         if (hwsup) {
 249                 /* Disable HW transitions when we are changing deps */
 250                 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 251                                                 clkdm->clktrctrl_mask);
 252                 _clkdm_del_autodeps(clkdm);
 253                 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 254                                                clkdm->clktrctrl_mask);
 255         } else {
 256                 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
 257                         omap3xxx_clkdm_sleep(clkdm);
 258         }
 259
 260         return 0;
 261 }
 262
 263 struct clkdm_ops omap3_clkdm_operations = {
 264         .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
 265         .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
 266         .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
 267         .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
 268         .clkdm_add_sleepdep     = omap3xxx_clkdm_add_sleepdep,
 269         .clkdm_del_sleepdep     = omap3xxx_clkdm_del_sleepdep,
 270         .clkdm_read_sleepdep    = omap3xxx_clkdm_read_sleepdep,
 271         .clkdm_clear_all_sleepdeps      = omap3xxx_clkdm_clear_all_sleepdeps,
 272         .clkdm_sleep            = omap3xxx_clkdm_sleep,
 273         .clkdm_wakeup           = omap3xxx_clkdm_wakeup,
 274         .clkdm_allow_idle       = omap3xxx_clkdm_allow_idle,
 275         .clkdm_deny_idle        = omap3xxx_clkdm_deny_idle,
 276         .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
 277         .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
 278 };
 279
 280 /*
 281  * Context save/restore code - OMAP3 only
 282  */
 283 struct omap3_cm_regs {
 284         u32 iva2_cm_clksel1;
 285         u32 iva2_cm_clksel2;
 286         u32 cm_sysconfig;
 287         u32 sgx_cm_clksel;
 288         u32 dss_cm_clksel;
 289         u32 cam_cm_clksel;
 290         u32 per_cm_clksel;
 291         u32 emu_cm_clksel;
 292         u32 emu_cm_clkstctrl;
 293         u32 pll_cm_autoidle;
 294         u32 pll_cm_autoidle2;
 295         u32 pll_cm_clksel4;
 296         u32 pll_cm_clksel5;
 297         u32 pll_cm_clken2;
 298         u32 cm_polctrl;
 299         u32 iva2_cm_fclken;
 300         u32 iva2_cm_clken_pll;
 301         u32 core_cm_fclken1;
 302         u32 core_cm_fclken3;
 303         u32 sgx_cm_fclken;
 304         u32 wkup_cm_fclken;
 305         u32 dss_cm_fclken;
 306         u32 cam_cm_fclken;
 307         u32 per_cm_fclken;
 308         u32 usbhost_cm_fclken;
 309         u32 core_cm_iclken1;
 310         u32 core_cm_iclken2;
 311         u32 core_cm_iclken3;
 312         u32 sgx_cm_iclken;
 313         u32 wkup_cm_iclken;
 314         u32 dss_cm_iclken;
 315         u32 cam_cm_iclken;
 316         u32 per_cm_iclken;
 317         u32 usbhost_cm_iclken;
 318         u32 iva2_cm_autoidle2;
 319         u32 mpu_cm_autoidle2;
 320         u32 iva2_cm_clkstctrl;
 321         u32 mpu_cm_clkstctrl;
 322         u32 core_cm_clkstctrl;
 323         u32 sgx_cm_clkstctrl;
 324         u32 dss_cm_clkstctrl;
 325         u32 cam_cm_clkstctrl;
 326         u32 per_cm_clkstctrl;
 327         u32 neon_cm_clkstctrl;
 328         u32 usbhost_cm_clkstctrl;
 329         u32 core_cm_autoidle1;
 330         u32 core_cm_autoidle2;
 331         u32 core_cm_autoidle3;
 332         u32 wkup_cm_autoidle;
 333         u32 dss_cm_autoidle;
 334         u32 cam_cm_autoidle;
 335         u32 per_cm_autoidle;
 336         u32 usbhost_cm_autoidle;
 337         u32 sgx_cm_sleepdep;
 338         u32 dss_cm_sleepdep;
 339         u32 cam_cm_sleepdep;
 340         u32 per_cm_sleepdep;
 341         u32 usbhost_cm_sleepdep;
 342         u32 cm_clkout_ctrl;
 343 };
 344
 345 static struct omap3_cm_regs cm_context;
 346
 347 void omap3_cm_save_context(void)
 348 {
 349         cm_context.iva2_cm_clksel1 =
 350                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 351         cm_context.iva2_cm_clksel2 =
 352                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 353         cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
 354         cm_context.sgx_cm_clksel =
 355                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 356         cm_context.dss_cm_clksel =
 357                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 358         cm_context.cam_cm_clksel =
 359                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 360         cm_context.per_cm_clksel =
 361                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 362         cm_context.emu_cm_clksel =
 363                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 364         cm_context.emu_cm_clkstctrl =
 365                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
 366         /*
 367          * As per erratum i671, ROM code does not respect the PER DPLL
 368          * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
 369          * In this case, even though this register has been saved in
 370          * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
 371          * by ourselves. So, we need to save it anyway.
 372          */
 373         cm_context.pll_cm_autoidle =
 374                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 375         cm_context.pll_cm_autoidle2 =
 376                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 377         cm_context.pll_cm_clksel4 =
 378                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 379         cm_context.pll_cm_clksel5 =
 380                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 381         cm_context.pll_cm_clken2 =
 382                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 383         cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
 384         cm_context.iva2_cm_fclken =
 385                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 386         cm_context.iva2_cm_clken_pll =
 387                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
 388         cm_context.core_cm_fclken1 =
 389                 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 390         cm_context.core_cm_fclken3 =
 391                 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 392         cm_context.sgx_cm_fclken =
 393                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 394         cm_context.wkup_cm_fclken =
 395                 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 396         cm_context.dss_cm_fclken =
 397                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 398         cm_context.cam_cm_fclken =
 399                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 400         cm_context.per_cm_fclken =
 401                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 402         cm_context.usbhost_cm_fclken =
 403                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 404         cm_context.core_cm_iclken1 =
 405                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 406         cm_context.core_cm_iclken2 =
 407                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 408         cm_context.core_cm_iclken3 =
 409                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 410         cm_context.sgx_cm_iclken =
 411                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 412         cm_context.wkup_cm_iclken =
 413                 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 414         cm_context.dss_cm_iclken =
 415                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 416         cm_context.cam_cm_iclken =
 417                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 418         cm_context.per_cm_iclken =
 419                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 420         cm_context.usbhost_cm_iclken =
 421                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 422         cm_context.iva2_cm_autoidle2 =
 423                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 424         cm_context.mpu_cm_autoidle2 =
 425                 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 426         cm_context.iva2_cm_clkstctrl =
 427                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 428         cm_context.mpu_cm_clkstctrl =
 429                 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
 430         cm_context.core_cm_clkstctrl =
 431                 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
 432         cm_context.sgx_cm_clkstctrl =
 433                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
 434         cm_context.dss_cm_clkstctrl =
 435                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
 436         cm_context.cam_cm_clkstctrl =
 437                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
 438         cm_context.per_cm_clkstctrl =
 439                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
 440         cm_context.neon_cm_clkstctrl =
 441                 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
 442         cm_context.usbhost_cm_clkstctrl =
 443                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 444                                       OMAP2_CM_CLKSTCTRL);
 445         cm_context.core_cm_autoidle1 =
 446                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 447         cm_context.core_cm_autoidle2 =
 448                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 449         cm_context.core_cm_autoidle3 =
 450                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 451         cm_context.wkup_cm_autoidle =
 452                 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 453         cm_context.dss_cm_autoidle =
 454                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 455         cm_context.cam_cm_autoidle =
 456                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 457         cm_context.per_cm_autoidle =
 458                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 459         cm_context.usbhost_cm_autoidle =
 460                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 461         cm_context.sgx_cm_sleepdep =
 462                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 463                                       OMAP3430_CM_SLEEPDEP);
 464         cm_context.dss_cm_sleepdep =
 465                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 466         cm_context.cam_cm_sleepdep =
 467                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 468         cm_context.per_cm_sleepdep =
 469                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 470         cm_context.usbhost_cm_sleepdep =
 471                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 472                                       OMAP3430_CM_SLEEPDEP);
 473         cm_context.cm_clkout_ctrl =
 474                 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
 475                                       OMAP3_CM_CLKOUT_CTRL_OFFSET);
 476 }
 477
 478 void omap3_cm_restore_context(void)
 479 {
 480         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 481                                CM_CLKSEL1);
 482         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 483                                CM_CLKSEL2);
 484         __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
 485         omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 486                                CM_CLKSEL);
 487         omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 488                                CM_CLKSEL);
 489         omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 490                                CM_CLKSEL);
 491         omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
 492                                CM_CLKSEL);
 493         omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 494                                CM_CLKSEL1);
 495         omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 496                                OMAP2_CM_CLKSTCTRL);
 497         /*
 498          * As per erratum i671, ROM code does not respect the PER DPLL
 499          * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
 500          * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
 501          */
 502         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
 503                                CM_AUTOIDLE);
 504         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
 505                                CM_AUTOIDLE2);
 506         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
 507                                OMAP3430ES2_CM_CLKSEL4);
 508         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
 509                                OMAP3430ES2_CM_CLKSEL5);
 510         omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
 511                                OMAP3430ES2_CM_CLKEN2);
 512         __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
 513         omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 514                                CM_FCLKEN);
 515         omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 516                                OMAP3430_CM_CLKEN_PLL);
 517         omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
 518                                CM_FCLKEN1);
 519         omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
 520                                OMAP3430ES2_CM_FCLKEN3);
 521         omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 522                                CM_FCLKEN);
 523         omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 524         omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 525                                CM_FCLKEN);
 526         omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 527                                CM_FCLKEN);
 528         omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
 529                                CM_FCLKEN);
 530         omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
 531                                OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 532         omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
 533                                CM_ICLKEN1);
 534         omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
 535                                CM_ICLKEN2);
 536         omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
 537                                CM_ICLKEN3);
 538         omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 539                                CM_ICLKEN);
 540         omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 541         omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 542                                CM_ICLKEN);
 543         omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 544                                CM_ICLKEN);
 545         omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
 546                                CM_ICLKEN);
 547         omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
 548                                OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 549         omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
 550                                CM_AUTOIDLE2);
 551         omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
 552                                CM_AUTOIDLE2);
 553         omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 554                                OMAP2_CM_CLKSTCTRL);
 555         omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
 556                                OMAP2_CM_CLKSTCTRL);
 557         omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
 558                                OMAP2_CM_CLKSTCTRL);
 559         omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 560                                OMAP2_CM_CLKSTCTRL);
 561         omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 562                                OMAP2_CM_CLKSTCTRL);
 563         omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 564                                OMAP2_CM_CLKSTCTRL);
 565         omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 566                                OMAP2_CM_CLKSTCTRL);
 567         omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 568                                OMAP2_CM_CLKSTCTRL);
 569         omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
 570                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
 571         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
 572                                CM_AUTOIDLE1);
 573         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
 574                                CM_AUTOIDLE2);
 575         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
 576                                CM_AUTOIDLE3);
 577         omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
 578                                CM_AUTOIDLE);
 579         omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 580                                CM_AUTOIDLE);
 581         omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 582                                CM_AUTOIDLE);
 583         omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 584                                CM_AUTOIDLE);
 585         omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
 586                                OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 587         omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 588                                OMAP3430_CM_SLEEPDEP);
 589         omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 590                                OMAP3430_CM_SLEEPDEP);
 591         omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 592                                OMAP3430_CM_SLEEPDEP);
 593         omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 594                                OMAP3430_CM_SLEEPDEP);
 595         omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
 596                                OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 597         omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 598                                OMAP3_CM_CLKOUT_CTRL_OFFSET);
 599 }