2 * linux/arch/arm/mach-omap2/devices.c
4 * OMAP2 platform device setup/initialization
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
19 #include <mach/hardware.h>
20 #include <mach/irqs.h>
21 #include <asm/mach-types.h>
22 #include <asm/mach/map.h>
26 #include <plat/board.h>
27 #include <plat/mcbsp.h>
28 #include <mach/gpio.h>
31 #include <plat/omap_hwmod.h>
32 #include <plat/omap_device.h>
39 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
41 static struct resource omap2cam_resources[] = {
43 .start = OMAP24XX_CAMERA_BASE,
44 .end = OMAP24XX_CAMERA_BASE + 0xfff,
45 .flags = IORESOURCE_MEM,
48 .start = INT_24XX_CAM_IRQ,
49 .flags = IORESOURCE_IRQ,
53 static struct platform_device omap2cam_device = {
54 .name = "omap24xxcam",
56 .num_resources = ARRAY_SIZE(omap2cam_resources),
57 .resource = omap2cam_resources,
61 static struct resource omap3isp_resources[] = {
63 .start = OMAP3430_ISP_BASE,
64 .end = OMAP3430_ISP_END,
65 .flags = IORESOURCE_MEM,
68 .start = OMAP3430_ISP_CCP2_BASE,
69 .end = OMAP3430_ISP_CCP2_END,
70 .flags = IORESOURCE_MEM,
73 .start = OMAP3430_ISP_CCDC_BASE,
74 .end = OMAP3430_ISP_CCDC_END,
75 .flags = IORESOURCE_MEM,
78 .start = OMAP3430_ISP_HIST_BASE,
79 .end = OMAP3430_ISP_HIST_END,
80 .flags = IORESOURCE_MEM,
83 .start = OMAP3430_ISP_H3A_BASE,
84 .end = OMAP3430_ISP_H3A_END,
85 .flags = IORESOURCE_MEM,
88 .start = OMAP3430_ISP_PREV_BASE,
89 .end = OMAP3430_ISP_PREV_END,
90 .flags = IORESOURCE_MEM,
93 .start = OMAP3430_ISP_RESZ_BASE,
94 .end = OMAP3430_ISP_RESZ_END,
95 .flags = IORESOURCE_MEM,
98 .start = OMAP3430_ISP_SBL_BASE,
99 .end = OMAP3430_ISP_SBL_END,
100 .flags = IORESOURCE_MEM,
103 .start = OMAP3430_ISP_CSI2A_REGS1_BASE,
104 .end = OMAP3430_ISP_CSI2A_REGS1_END,
105 .flags = IORESOURCE_MEM,
108 .start = OMAP3430_ISP_CSIPHY2_BASE,
109 .end = OMAP3430_ISP_CSIPHY2_END,
110 .flags = IORESOURCE_MEM,
113 .start = OMAP3630_ISP_CSI2A_REGS2_BASE,
114 .end = OMAP3630_ISP_CSI2A_REGS2_END,
115 .flags = IORESOURCE_MEM,
118 .start = OMAP3630_ISP_CSI2C_REGS1_BASE,
119 .end = OMAP3630_ISP_CSI2C_REGS1_END,
120 .flags = IORESOURCE_MEM,
123 .start = OMAP3630_ISP_CSIPHY1_BASE,
124 .end = OMAP3630_ISP_CSIPHY1_END,
125 .flags = IORESOURCE_MEM,
128 .start = OMAP3630_ISP_CSI2C_REGS2_BASE,
129 .end = OMAP3630_ISP_CSI2C_REGS2_END,
130 .flags = IORESOURCE_MEM,
133 .start = INT_34XX_CAM_IRQ,
134 .flags = IORESOURCE_IRQ,
138 static struct platform_device omap3isp_device = {
141 .num_resources = ARRAY_SIZE(omap3isp_resources),
142 .resource = omap3isp_resources,
145 int omap3_init_camera(struct isp_platform_data *pdata)
147 omap3isp_device.dev.platform_data = pdata;
148 return platform_device_register(&omap3isp_device);
151 static inline void omap_init_camera(void)
153 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
154 if (cpu_is_omap24xx())
155 platform_device_register(&omap2cam_device);
159 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
161 #define MBOX_REG_SIZE 0x120
163 #ifdef CONFIG_ARCH_OMAP2
164 static struct resource omap2_mbox_resources[] = {
166 .start = OMAP24XX_MAILBOX_BASE,
167 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
168 .flags = IORESOURCE_MEM,
171 .start = INT_24XX_MAIL_U0_MPU,
172 .flags = IORESOURCE_IRQ,
176 .start = INT_24XX_MAIL_U3_MPU,
177 .flags = IORESOURCE_IRQ,
181 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
183 #define omap2_mbox_resources NULL
184 #define omap2_mbox_resources_sz 0
187 #ifdef CONFIG_ARCH_OMAP3
188 static struct resource omap3_mbox_resources[] = {
190 .start = OMAP34XX_MAILBOX_BASE,
191 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
192 .flags = IORESOURCE_MEM,
195 .start = INT_24XX_MAIL_U0_MPU,
196 .flags = IORESOURCE_IRQ,
200 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
202 #define omap3_mbox_resources NULL
203 #define omap3_mbox_resources_sz 0
206 #ifdef CONFIG_ARCH_OMAP4
208 #define OMAP4_MBOX_REG_SIZE 0x130
209 static struct resource omap4_mbox_resources[] = {
211 .start = OMAP44XX_MAILBOX_BASE,
212 .end = OMAP44XX_MAILBOX_BASE +
213 OMAP4_MBOX_REG_SIZE - 1,
214 .flags = IORESOURCE_MEM,
217 .start = OMAP44XX_IRQ_MAIL_U0,
218 .flags = IORESOURCE_IRQ,
222 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
224 #define omap4_mbox_resources NULL
225 #define omap4_mbox_resources_sz 0
228 static struct platform_device mbox_device = {
229 .name = "omap-mailbox",
233 static inline void omap_init_mbox(void)
235 if (cpu_is_omap24xx()) {
236 mbox_device.resource = omap2_mbox_resources;
237 mbox_device.num_resources = omap2_mbox_resources_sz;
238 } else if (cpu_is_omap34xx()) {
239 mbox_device.resource = omap3_mbox_resources;
240 mbox_device.num_resources = omap3_mbox_resources_sz;
241 } else if (cpu_is_omap44xx()) {
242 mbox_device.resource = omap4_mbox_resources;
243 mbox_device.num_resources = omap4_mbox_resources_sz;
245 pr_err("%s: platform not supported\n", __func__);
248 platform_device_register(&mbox_device);
251 static inline void omap_init_mbox(void) { }
252 #endif /* CONFIG_OMAP_MBOX_FWK */
254 static inline void omap_init_sti(void) {}
256 #if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
258 static struct platform_device omap_pcm = {
259 .name = "omap-pcm-audio",
264 * OMAP2420 has 2 McBSP ports
265 * OMAP2430 has 5 McBSP ports
266 * OMAP3 has 5 McBSP ports
267 * OMAP4 has 4 McBSP ports
269 OMAP_MCBSP_PLATFORM_DEVICE(1);
270 OMAP_MCBSP_PLATFORM_DEVICE(2);
271 OMAP_MCBSP_PLATFORM_DEVICE(3);
272 OMAP_MCBSP_PLATFORM_DEVICE(4);
273 OMAP_MCBSP_PLATFORM_DEVICE(5);
275 static void omap_init_audio(void)
277 platform_device_register(&omap_mcbsp1);
278 platform_device_register(&omap_mcbsp2);
279 if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
280 platform_device_register(&omap_mcbsp3);
281 platform_device_register(&omap_mcbsp4);
283 if (cpu_is_omap243x() || cpu_is_omap34xx())
284 platform_device_register(&omap_mcbsp5);
286 platform_device_register(&omap_pcm);
290 static inline void omap_init_audio(void) {}
293 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
295 #include <plat/mcspi.h>
297 #define OMAP2_MCSPI1_BASE 0x48098000
298 #define OMAP2_MCSPI2_BASE 0x4809a000
299 #define OMAP2_MCSPI3_BASE 0x480b8000
300 #define OMAP2_MCSPI4_BASE 0x480ba000
302 #define OMAP4_MCSPI1_BASE 0x48098100
303 #define OMAP4_MCSPI2_BASE 0x4809a100
304 #define OMAP4_MCSPI3_BASE 0x480b8100
305 #define OMAP4_MCSPI4_BASE 0x480ba100
307 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
311 static struct resource omap2_mcspi1_resources[] = {
313 .start = OMAP2_MCSPI1_BASE,
314 .end = OMAP2_MCSPI1_BASE + 0xff,
315 .flags = IORESOURCE_MEM,
319 static struct platform_device omap2_mcspi1 = {
320 .name = "omap2_mcspi",
322 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
323 .resource = omap2_mcspi1_resources,
325 .platform_data = &omap2_mcspi1_config,
329 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
333 static struct resource omap2_mcspi2_resources[] = {
335 .start = OMAP2_MCSPI2_BASE,
336 .end = OMAP2_MCSPI2_BASE + 0xff,
337 .flags = IORESOURCE_MEM,
341 static struct platform_device omap2_mcspi2 = {
342 .name = "omap2_mcspi",
344 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
345 .resource = omap2_mcspi2_resources,
347 .platform_data = &omap2_mcspi2_config,
351 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
352 defined(CONFIG_ARCH_OMAP4)
353 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
357 static struct resource omap2_mcspi3_resources[] = {
359 .start = OMAP2_MCSPI3_BASE,
360 .end = OMAP2_MCSPI3_BASE + 0xff,
361 .flags = IORESOURCE_MEM,
365 static struct platform_device omap2_mcspi3 = {
366 .name = "omap2_mcspi",
368 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
369 .resource = omap2_mcspi3_resources,
371 .platform_data = &omap2_mcspi3_config,
376 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
377 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
381 static struct resource omap2_mcspi4_resources[] = {
383 .start = OMAP2_MCSPI4_BASE,
384 .end = OMAP2_MCSPI4_BASE + 0xff,
385 .flags = IORESOURCE_MEM,
389 static struct platform_device omap2_mcspi4 = {
390 .name = "omap2_mcspi",
392 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
393 .resource = omap2_mcspi4_resources,
395 .platform_data = &omap2_mcspi4_config,
400 #ifdef CONFIG_ARCH_OMAP4
401 static inline void omap4_mcspi_fixup(void)
403 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
404 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
405 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
406 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
407 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
408 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
409 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
410 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
413 static inline void omap4_mcspi_fixup(void)
418 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
419 defined(CONFIG_ARCH_OMAP4)
420 static inline void omap2_mcspi3_init(void)
422 platform_device_register(&omap2_mcspi3);
425 static inline void omap2_mcspi3_init(void)
430 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
431 static inline void omap2_mcspi4_init(void)
433 platform_device_register(&omap2_mcspi4);
436 static inline void omap2_mcspi4_init(void)
441 static void omap_init_mcspi(void)
443 if (cpu_is_omap44xx())
446 platform_device_register(&omap2_mcspi1);
447 platform_device_register(&omap2_mcspi2);
449 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
452 if (cpu_is_omap343x() || cpu_is_omap44xx())
457 static inline void omap_init_mcspi(void) {}
460 static struct resource omap2_pmu_resource = {
463 .flags = IORESOURCE_IRQ,
466 static struct resource omap3_pmu_resource = {
467 .start = INT_34XX_BENCH_MPU_EMUL,
468 .end = INT_34XX_BENCH_MPU_EMUL,
469 .flags = IORESOURCE_IRQ,
472 static struct platform_device omap_pmu_device = {
474 .id = ARM_PMU_DEVICE_CPU,
478 static void omap_init_pmu(void)
480 if (cpu_is_omap24xx())
481 omap_pmu_device.resource = &omap2_pmu_resource;
482 else if (cpu_is_omap34xx())
483 omap_pmu_device.resource = &omap3_pmu_resource;
487 platform_device_register(&omap_pmu_device);
491 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
493 #ifdef CONFIG_ARCH_OMAP2
494 static struct resource omap2_sham_resources[] = {
496 .start = OMAP24XX_SEC_SHA1MD5_BASE,
497 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
498 .flags = IORESOURCE_MEM,
501 .start = INT_24XX_SHA1MD5,
502 .flags = IORESOURCE_IRQ,
505 static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
507 #define omap2_sham_resources NULL
508 #define omap2_sham_resources_sz 0
511 #ifdef CONFIG_ARCH_OMAP3
512 static struct resource omap3_sham_resources[] = {
514 .start = OMAP34XX_SEC_SHA1MD5_BASE,
515 .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
516 .flags = IORESOURCE_MEM,
519 .start = INT_34XX_SHA1MD52_IRQ,
520 .flags = IORESOURCE_IRQ,
523 .start = OMAP34XX_DMA_SHA1MD5_RX,
524 .flags = IORESOURCE_DMA,
527 static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
529 #define omap3_sham_resources NULL
530 #define omap3_sham_resources_sz 0
533 static struct platform_device sham_device = {
538 static void omap_init_sham(void)
540 if (cpu_is_omap24xx()) {
541 sham_device.resource = omap2_sham_resources;
542 sham_device.num_resources = omap2_sham_resources_sz;
543 } else if (cpu_is_omap34xx()) {
544 sham_device.resource = omap3_sham_resources;
545 sham_device.num_resources = omap3_sham_resources_sz;
547 pr_err("%s: platform not supported\n", __func__);
550 platform_device_register(&sham_device);
553 static inline void omap_init_sham(void) { }
556 #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
558 #ifdef CONFIG_ARCH_OMAP2
559 static struct resource omap2_aes_resources[] = {
561 .start = OMAP24XX_SEC_AES_BASE,
562 .end = OMAP24XX_SEC_AES_BASE + 0x4C,
563 .flags = IORESOURCE_MEM,
566 .start = OMAP24XX_DMA_AES_TX,
567 .flags = IORESOURCE_DMA,
570 .start = OMAP24XX_DMA_AES_RX,
571 .flags = IORESOURCE_DMA,
574 static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
576 #define omap2_aes_resources NULL
577 #define omap2_aes_resources_sz 0
580 #ifdef CONFIG_ARCH_OMAP3
581 static struct resource omap3_aes_resources[] = {
583 .start = OMAP34XX_SEC_AES_BASE,
584 .end = OMAP34XX_SEC_AES_BASE + 0x4C,
585 .flags = IORESOURCE_MEM,
588 .start = OMAP34XX_DMA_AES2_TX,
589 .flags = IORESOURCE_DMA,
592 .start = OMAP34XX_DMA_AES2_RX,
593 .flags = IORESOURCE_DMA,
596 static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
598 #define omap3_aes_resources NULL
599 #define omap3_aes_resources_sz 0
602 static struct platform_device aes_device = {
607 static void omap_init_aes(void)
609 if (cpu_is_omap24xx()) {
610 aes_device.resource = omap2_aes_resources;
611 aes_device.num_resources = omap2_aes_resources_sz;
612 } else if (cpu_is_omap34xx()) {
613 aes_device.resource = omap3_aes_resources;
614 aes_device.num_resources = omap3_aes_resources_sz;
616 pr_err("%s: platform not supported\n", __func__);
619 platform_device_register(&aes_device);
623 static inline void omap_init_aes(void) { }
626 /*-------------------------------------------------------------------------*/
628 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
630 #define MMCHS_SYSCONFIG 0x0010
631 #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
632 #define MMCHS_SYSSTATUS 0x0014
633 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
635 static struct platform_device dummy_pdev = {
637 .bus = &platform_bus_type,
642 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
644 * Ensure that each MMC controller is fully reset. Controllers
645 * left in an unknown state (by bootloader) may prevent retention
646 * or OFF-mode. This is especially important in cases where the
647 * MMC driver is not enabled, _or_ built as a module.
649 * In order for reset to work, interface, functional and debounce
650 * clocks must be enabled. The debounce clock comes from func_32k_clk
651 * and is not under SW control, so we only enable i- and f-clocks.
653 static void __init omap_hsmmc_reset(void)
655 u32 i, nr_controllers;
656 struct clk *iclk, *fclk;
658 if (cpu_is_omap242x())
661 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
662 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
664 for (i = 0; i < nr_controllers; i++) {
666 struct device *dev = &dummy_pdev.dev;
670 base = OMAP2_MMC1_BASE;
673 base = OMAP2_MMC2_BASE;
676 base = OMAP3_MMC3_BASE;
679 if (!cpu_is_omap44xx())
681 base = OMAP4_MMC4_BASE;
684 if (!cpu_is_omap44xx())
686 base = OMAP4_MMC5_BASE;
690 if (cpu_is_omap44xx())
691 base += OMAP4_MMC_REG_OFFSET;
694 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
695 iclk = clk_get(dev, "ick");
698 if (clk_enable(iclk))
701 fclk = clk_get(dev, "fck");
704 if (clk_enable(fclk))
707 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
708 v = omap_readl(base + MMCHS_SYSSTATUS);
709 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
710 MMCHS_SYSSTATUS_RESETDONE))
727 printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
728 "cannot reset.\n", __func__, i);
731 static inline void omap_hsmmc_reset(void) {}
734 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
735 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
737 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
740 if ((mmc_controller->slots[0].switch_pin > 0) && \
741 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
742 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
743 OMAP_PIN_INPUT_PULLUP);
744 if ((mmc_controller->slots[0].gpio_wp > 0) && \
745 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
746 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
747 OMAP_PIN_INPUT_PULLUP);
749 if (cpu_is_omap2420() && controller_nr == 0) {
750 omap_mux_init_signal("sdmmc_cmd", 0);
751 omap_mux_init_signal("sdmmc_clki", 0);
752 omap_mux_init_signal("sdmmc_clko", 0);
753 omap_mux_init_signal("sdmmc_dat0", 0);
754 omap_mux_init_signal("sdmmc_dat_dir0", 0);
755 omap_mux_init_signal("sdmmc_cmd_dir", 0);
756 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
757 omap_mux_init_signal("sdmmc_dat1", 0);
758 omap_mux_init_signal("sdmmc_dat2", 0);
759 omap_mux_init_signal("sdmmc_dat3", 0);
760 omap_mux_init_signal("sdmmc_dat_dir1", 0);
761 omap_mux_init_signal("sdmmc_dat_dir2", 0);
762 omap_mux_init_signal("sdmmc_dat_dir3", 0);
766 * Use internal loop-back in MMC/SDIO Module Input Clock
769 if (mmc_controller->slots[0].internal_clock) {
770 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
772 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
776 if (cpu_is_omap34xx()) {
777 if (controller_nr == 0) {
778 omap_mux_init_signal("sdmmc1_clk",
779 OMAP_PIN_INPUT_PULLUP);
780 omap_mux_init_signal("sdmmc1_cmd",
781 OMAP_PIN_INPUT_PULLUP);
782 omap_mux_init_signal("sdmmc1_dat0",
783 OMAP_PIN_INPUT_PULLUP);
784 if (mmc_controller->slots[0].caps &
785 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
786 omap_mux_init_signal("sdmmc1_dat1",
787 OMAP_PIN_INPUT_PULLUP);
788 omap_mux_init_signal("sdmmc1_dat2",
789 OMAP_PIN_INPUT_PULLUP);
790 omap_mux_init_signal("sdmmc1_dat3",
791 OMAP_PIN_INPUT_PULLUP);
793 if (mmc_controller->slots[0].caps &
794 MMC_CAP_8_BIT_DATA) {
795 omap_mux_init_signal("sdmmc1_dat4",
796 OMAP_PIN_INPUT_PULLUP);
797 omap_mux_init_signal("sdmmc1_dat5",
798 OMAP_PIN_INPUT_PULLUP);
799 omap_mux_init_signal("sdmmc1_dat6",
800 OMAP_PIN_INPUT_PULLUP);
801 omap_mux_init_signal("sdmmc1_dat7",
802 OMAP_PIN_INPUT_PULLUP);
805 if (controller_nr == 1) {
807 omap_mux_init_signal("sdmmc2_clk",
808 OMAP_PIN_INPUT_PULLUP);
809 omap_mux_init_signal("sdmmc2_cmd",
810 OMAP_PIN_INPUT_PULLUP);
811 omap_mux_init_signal("sdmmc2_dat0",
812 OMAP_PIN_INPUT_PULLUP);
815 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
816 * in the board-*.c files
818 if (mmc_controller->slots[0].caps &
819 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
820 omap_mux_init_signal("sdmmc2_dat1",
821 OMAP_PIN_INPUT_PULLUP);
822 omap_mux_init_signal("sdmmc2_dat2",
823 OMAP_PIN_INPUT_PULLUP);
824 omap_mux_init_signal("sdmmc2_dat3",
825 OMAP_PIN_INPUT_PULLUP);
827 if (mmc_controller->slots[0].caps &
828 MMC_CAP_8_BIT_DATA) {
829 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
830 OMAP_PIN_INPUT_PULLUP);
831 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
832 OMAP_PIN_INPUT_PULLUP);
833 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
834 OMAP_PIN_INPUT_PULLUP);
835 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
836 OMAP_PIN_INPUT_PULLUP);
841 * For MMC3 the pins need to be muxed in the board-*.c files
846 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
852 for (i = 0; i < nr_controllers; i++) {
853 unsigned long base, size;
854 unsigned int irq = 0;
859 omap2_mmc_mux(mmc_data[i], i);
863 base = OMAP2_MMC1_BASE;
864 irq = INT_24XX_MMC_IRQ;
867 base = OMAP2_MMC2_BASE;
868 irq = INT_24XX_MMC2_IRQ;
871 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
873 base = OMAP3_MMC3_BASE;
874 irq = INT_34XX_MMC3_IRQ;
877 if (!cpu_is_omap44xx())
879 base = OMAP4_MMC4_BASE;
880 irq = OMAP44XX_IRQ_MMC4;
883 if (!cpu_is_omap44xx())
885 base = OMAP4_MMC5_BASE;
886 irq = OMAP44XX_IRQ_MMC5;
892 if (cpu_is_omap2420()) {
893 size = OMAP2420_MMC_SIZE;
895 } else if (cpu_is_omap44xx()) {
897 irq += OMAP44XX_IRQ_GIC_START;
898 size = OMAP4_HSMMC_SIZE;
899 name = "mmci-omap-hs";
901 size = OMAP3_HSMMC_SIZE;
902 name = "mmci-omap-hs";
904 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
910 /*-------------------------------------------------------------------------*/
912 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
913 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
914 #define OMAP_HDQ_BASE 0x480B2000
916 static struct resource omap_hdq_resources[] = {
918 .start = OMAP_HDQ_BASE,
919 .end = OMAP_HDQ_BASE + 0x1C,
920 .flags = IORESOURCE_MEM,
923 .start = INT_24XX_HDQ_IRQ,
924 .flags = IORESOURCE_IRQ,
927 static struct platform_device omap_hdq_dev = {
931 .platform_data = NULL,
933 .num_resources = ARRAY_SIZE(omap_hdq_resources),
934 .resource = omap_hdq_resources,
936 static inline void omap_hdq_init(void)
938 (void) platform_device_register(&omap_hdq_dev);
941 static inline void omap_hdq_init(void) {}
944 /*---------------------------------------------------------------------------*/
946 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
947 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
948 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
949 static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
952 static struct resource omap_vout_resource[2] = {
956 static struct platform_device omap_vout_device = {
958 .num_resources = ARRAY_SIZE(omap_vout_resource),
959 .resource = &omap_vout_resource[0],
962 static void omap_init_vout(void)
964 if (platform_device_register(&omap_vout_device) < 0)
965 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
968 static inline void omap_init_vout(void) {}
971 /*-------------------------------------------------------------------------*/
973 static int __init omap2_init_devices(void)
976 * please keep these calls, and their implementations above,
977 * in alphabetical order so they're easier to sort through.
993 arch_initcall(omap2_init_devices);
995 #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
996 static struct omap_device_pm_latency omap_wdt_latency[] = {
998 .deactivate_func = omap_device_idle_hwmods,
999 .activate_func = omap_device_enable_hwmods,
1000 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
1004 static int __init omap_init_wdt(void)
1007 struct omap_device *od;
1008 struct omap_hwmod *oh;
1009 char *oh_name = "wd_timer2";
1010 char *dev_name = "omap_wdt";
1012 if (!cpu_class_is_omap2())
1015 oh = omap_hwmod_lookup(oh_name);
1017 pr_err("Could not look up wd_timer%d hwmod\n", id);
1021 od = omap_device_build(dev_name, id, oh, NULL, 0,
1023 ARRAY_SIZE(omap_wdt_latency), 0);
1024 WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
1025 dev_name, oh->name);
1028 subsys_initcall(omap_init_wdt);