2 * OMAP3/4 - specific DPLL control functions
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/bitops.h>
29 #include <linux/clkdev.h>
31 #include "clockdomain.h"
34 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
35 #define DPLL_AUTOIDLE_DISABLE 0x0
36 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
38 #define MAX_DPLL_WAIT_TRIES 1000000
40 /* Private functions */
42 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
43 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
45 const struct dpll_data *dd;
50 v = omap2_clk_readl(clk, dd->control_reg);
51 v &= ~dd->enable_mask;
52 v |= clken_bits << __ffs(dd->enable_mask);
53 omap2_clk_writel(v, clk, dd->control_reg);
56 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
57 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
59 const struct dpll_data *dd;
65 clk_name = __clk_get_name(clk->hw.clk);
67 state <<= __ffs(dd->idlest_mask);
69 while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
70 != state) && i < MAX_DPLL_WAIT_TRIES) {
75 if (i == MAX_DPLL_WAIT_TRIES) {
76 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
77 clk_name, (state) ? "locked" : "bypassed");
79 pr_debug("clock: %s transition to '%s' in %d loops\n",
80 clk_name, (state) ? "locked" : "bypassed", i);
88 /* From 3430 TRM ES2 4.7.6.2 */
89 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n)
94 fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
96 pr_debug("clock: fint is %lu\n", fint);
98 if (fint >= 750000 && fint <= 1000000)
100 else if (fint > 1000000 && fint <= 1250000)
102 else if (fint > 1250000 && fint <= 1500000)
104 else if (fint > 1500000 && fint <= 1750000)
106 else if (fint > 1750000 && fint <= 2100000)
108 else if (fint > 7500000 && fint <= 10000000)
110 else if (fint > 10000000 && fint <= 12500000)
112 else if (fint > 12500000 && fint <= 15000000)
114 else if (fint > 15000000 && fint <= 17500000)
116 else if (fint > 17500000 && fint <= 21000000)
119 pr_debug("clock: unknown freqsel setting for %d\n", n);
125 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
126 * @clk: pointer to a DPLL struct clk
128 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
129 * readiness before returning. Will save and restore the DPLL's
130 * autoidle state across the enable, per the CDP code. If the DPLL
131 * locked successfully, return 0; if the DPLL did not lock in the time
132 * allotted, or DPLL3 was passed in, return -EINVAL.
134 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
136 const struct dpll_data *dd;
141 pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk->hw.clk));
144 state <<= __ffs(dd->idlest_mask);
146 /* Check if already locked */
147 if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
150 ai = omap3_dpll_autoidle_read(clk);
153 omap3_dpll_deny_idle(clk);
155 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
157 r = _omap3_wait_dpll_status(clk, 1);
160 omap3_dpll_allow_idle(clk);
167 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
168 * @clk: pointer to a DPLL struct clk
170 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
171 * bypass mode, the DPLL's rate is set equal to its parent clock's
172 * rate. Waits for the DPLL to report readiness before returning.
173 * Will save and restore the DPLL's autoidle state across the enable,
174 * per the CDP code. If the DPLL entered bypass mode successfully,
175 * return 0; if the DPLL did not enter bypass in the time allotted, or
176 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
179 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk)
184 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
187 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
188 __clk_get_name(clk->hw.clk));
190 ai = omap3_dpll_autoidle_read(clk);
192 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
194 r = _omap3_wait_dpll_status(clk, 0);
197 omap3_dpll_allow_idle(clk);
203 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
204 * @clk: pointer to a DPLL struct clk
206 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
207 * restore the DPLL's autoidle state across the stop, per the CDP
208 * code. If DPLL3 was passed in, or the DPLL does not support
209 * low-power stop, return -EINVAL; otherwise, return 0.
211 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk)
215 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
218 pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk->hw.clk));
220 ai = omap3_dpll_autoidle_read(clk);
222 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
225 omap3_dpll_allow_idle(clk);
231 * _lookup_dco - Lookup DCO used by j-type DPLL
232 * @clk: pointer to a DPLL struct clk
233 * @dco: digital control oscillator selector
234 * @m: DPLL multiplier to set
235 * @n: DPLL divider to set
237 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
239 * XXX This code is not needed for 3430/AM35xx; can it be optimized
240 * out in non-multi-OMAP builds for those chips?
242 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n)
244 unsigned long fint, clkinp; /* watch out for overflow */
246 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
247 fint = (clkinp / n) * m;
249 if (fint < 1000000000)
256 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
257 * @clk: pointer to a DPLL struct clk
258 * @sd_div: target sigma-delta divider
259 * @m: DPLL multiplier to set
260 * @n: DPLL divider to set
262 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
264 * XXX This code is not needed for 3430/AM35xx; can it be optimized
265 * out in non-multi-OMAP builds for those chips?
267 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n)
269 unsigned long clkinp, sd; /* watch out for overflow */
272 clkinp = __clk_get_rate(__clk_get_parent(clk->hw.clk));
275 * target sigma-delta to near 250MHz
276 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
278 clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
279 mod1 = (clkinp * m) % (250 * n);
280 sd = (clkinp * m) / (250 * n);
290 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
291 * @clk: struct clk * of DPLL to set
292 * @freqsel: FREQSEL value to set
294 * Program the DPLL with the last M, N values calculated, and wait for
295 * the DPLL to lock. Returns -EINVAL upon error, or 0 upon success.
297 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
299 struct dpll_data *dd = clk->dpll_data;
303 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
304 _omap3_noncore_dpll_bypass(clk);
307 * Set jitter correction. Jitter correction applicable for OMAP343X
308 * only since freqsel field is no longer present on other devices.
310 if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
311 v = omap2_clk_readl(clk, dd->control_reg);
312 v &= ~dd->freqsel_mask;
313 v |= freqsel << __ffs(dd->freqsel_mask);
314 omap2_clk_writel(v, clk, dd->control_reg);
317 /* Set DPLL multiplier, divider */
318 v = omap2_clk_readl(clk, dd->mult_div1_reg);
320 /* Handle Duty Cycle Correction */
322 if (dd->last_rounded_rate >= dd->dcc_rate)
323 v |= dd->dcc_mask; /* Enable DCC */
325 v &= ~dd->dcc_mask; /* Disable DCC */
328 v &= ~(dd->mult_mask | dd->div1_mask);
329 v |= dd->last_rounded_m << __ffs(dd->mult_mask);
330 v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
332 /* Configure dco and sd_div for dplls that have these fields */
334 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n);
335 v &= ~(dd->dco_mask);
336 v |= dco << __ffs(dd->dco_mask);
338 if (dd->sddiv_mask) {
339 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m,
341 v &= ~(dd->sddiv_mask);
342 v |= sd_div << __ffs(dd->sddiv_mask);
345 omap2_clk_writel(v, clk, dd->mult_div1_reg);
347 /* Set 4X multiplier and low-power mode */
348 if (dd->m4xen_mask || dd->lpmode_mask) {
349 v = omap2_clk_readl(clk, dd->control_reg);
351 if (dd->m4xen_mask) {
352 if (dd->last_rounded_m4xen)
355 v &= ~dd->m4xen_mask;
358 if (dd->lpmode_mask) {
359 if (dd->last_rounded_lpmode)
360 v |= dd->lpmode_mask;
362 v &= ~dd->lpmode_mask;
365 omap2_clk_writel(v, clk, dd->control_reg);
368 /* We let the clock framework set the other output dividers later */
370 /* REVISIT: Set ramp-up delay? */
372 _omap3_noncore_dpll_lock(clk);
377 /* Public functions */
380 * omap3_dpll_recalc - recalculate DPLL rate
381 * @clk: DPLL struct clk
383 * Recalculate and propagate the DPLL rate.
385 unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate)
387 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
389 return omap2_get_dpll_rate(clk);
392 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
395 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
396 * @clk: pointer to a DPLL struct clk
398 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
399 * The choice of modes depends on the DPLL's programmed rate: if it is
400 * the same as the DPLL's parent clock, it will enter bypass;
401 * otherwise, it will enter lock. This code will wait for the DPLL to
402 * indicate readiness before returning, unless the DPLL takes too long
403 * to enter the target state. Intended to be used as the struct clk's
404 * enable function. If DPLL3 was passed in, or the DPLL does not
405 * support low-power stop, or if the DPLL took too long to enter
406 * bypass or lock, return -EINVAL; otherwise, return 0.
408 int omap3_noncore_dpll_enable(struct clk_hw *hw)
410 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
412 struct dpll_data *dd;
420 r = clkdm_clk_enable(clk->clkdm, hw->clk);
423 "%s: could not enable %s's clockdomain %s: %d\n",
424 __func__, __clk_get_name(hw->clk),
425 clk->clkdm->name, r);
430 parent = __clk_get_parent(hw->clk);
432 if (__clk_get_rate(hw->clk) == __clk_get_rate(dd->clk_bypass)) {
433 WARN_ON(parent != dd->clk_bypass);
434 r = _omap3_noncore_dpll_bypass(clk);
436 WARN_ON(parent != dd->clk_ref);
437 r = _omap3_noncore_dpll_lock(clk);
444 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
445 * @clk: pointer to a DPLL struct clk
447 * Instructs a non-CORE DPLL to enter low-power stop. This function is
448 * intended for use in struct clkops. No return value.
450 void omap3_noncore_dpll_disable(struct clk_hw *hw)
452 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
454 _omap3_noncore_dpll_stop(clk);
456 clkdm_clk_disable(clk->clkdm, hw->clk);
460 /* Non-CORE DPLL rate set code */
463 * omap3_noncore_dpll_determine_rate - determine rate for a DPLL
464 * @hw: pointer to the clock to determine rate for
465 * @rate: target rate for the DPLL
466 * @best_parent_rate: pointer for returning best parent rate
467 * @best_parent_clk: pointer for returning best parent clock
469 * Determines which DPLL mode to use for reaching a desired target rate.
470 * Checks whether the DPLL shall be in bypass or locked mode, and if
471 * locked, calculates the M,N values for the DPLL via round-rate.
472 * Returns a positive clock rate with success, negative error value
475 long omap3_noncore_dpll_determine_rate(struct clk_hw *hw, unsigned long rate,
476 unsigned long *best_parent_rate,
477 struct clk_hw **best_parent_clk)
479 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
480 struct dpll_data *dd;
489 if (__clk_get_rate(dd->clk_bypass) == rate &&
490 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
491 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
493 rate = omap2_dpll_round_rate(hw, rate, best_parent_rate);
494 *best_parent_clk = __clk_get_hw(dd->clk_ref);
497 *best_parent_rate = rate;
503 * omap3_noncore_dpll_set_parent - set parent for a DPLL clock
504 * @hw: pointer to the clock to set parent for
505 * @index: parent index to select
507 * Sets parent for a DPLL clock. This sets the DPLL into bypass or
508 * locked mode. Returns 0 with success, negative error value otherwise.
510 int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index)
512 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
519 ret = _omap3_noncore_dpll_bypass(clk);
521 ret = _omap3_noncore_dpll_lock(clk);
527 * omap3_noncore_dpll_set_rate - set rate for a DPLL clock
528 * @hw: pointer to the clock to set parent for
529 * @rate: target rate for the clock
530 * @parent_rate: rate of the parent clock
532 * Sets rate for a DPLL clock. First checks if the clock parent is
533 * reference clock (in bypass mode, the rate of the clock can't be
534 * changed) and proceeds with the rate change operation. Returns 0
535 * with success, negative error value otherwise.
537 int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
538 unsigned long parent_rate)
540 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
541 struct dpll_data *dd;
552 if (__clk_get_parent(hw->clk) != dd->clk_ref)
555 if (dd->last_rounded_rate == 0)
558 /* Freqsel is available only on OMAP343X devices */
559 if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) {
560 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
564 pr_debug("%s: %s: set rate: locking rate to %lu.\n", __func__,
565 __clk_get_name(hw->clk), rate);
567 ret = omap3_noncore_dpll_program(clk, freqsel);
573 * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock
574 * @hw: pointer to the clock to set rate and parent for
575 * @rate: target rate for the DPLL
576 * @parent_rate: clock rate of the DPLL parent
577 * @index: new parent index for the DPLL, 0 - reference, 1 - bypass
579 * Sets rate and parent for a DPLL clock. If new parent is the bypass
580 * clock, only selects the parent. Otherwise proceeds with a rate
581 * change, as this will effectively also change the parent as the
582 * DPLL is put into locked mode. Returns 0 with success, negative error
585 int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
587 unsigned long parent_rate,
596 * clk-ref at index[0], in which case we only need to set rate,
597 * the parent will be changed automatically with the lock sequence.
598 * With clk-bypass case we only need to change parent.
601 ret = omap3_noncore_dpll_set_parent(hw, index);
603 ret = omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
608 /* DPLL autoidle read/set code */
611 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
612 * @clk: struct clk * of the DPLL to read
614 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
615 * -EINVAL if passed a null pointer or if the struct clk does not
616 * appear to refer to a DPLL.
618 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
620 const struct dpll_data *dd;
623 if (!clk || !clk->dpll_data)
628 if (!dd->autoidle_reg)
631 v = omap2_clk_readl(clk, dd->autoidle_reg);
632 v &= dd->autoidle_mask;
633 v >>= __ffs(dd->autoidle_mask);
639 * omap3_dpll_allow_idle - enable DPLL autoidle bits
640 * @clk: struct clk * of the DPLL to operate on
642 * Enable DPLL automatic idle control. This automatic idle mode
643 * switching takes effect only when the DPLL is locked, at least on
644 * OMAP3430. The DPLL will enter low-power stop when its downstream
645 * clocks are gated. No return value.
647 void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
649 const struct dpll_data *dd;
652 if (!clk || !clk->dpll_data)
657 if (!dd->autoidle_reg)
661 * REVISIT: CORE DPLL can optionally enter low-power bypass
662 * by writing 0x5 instead of 0x1. Add some mechanism to
663 * optionally enter this mode.
665 v = omap2_clk_readl(clk, dd->autoidle_reg);
666 v &= ~dd->autoidle_mask;
667 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
668 omap2_clk_writel(v, clk, dd->autoidle_reg);
673 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
674 * @clk: struct clk * of the DPLL to operate on
676 * Disable DPLL automatic idle control. No return value.
678 void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
680 const struct dpll_data *dd;
683 if (!clk || !clk->dpll_data)
688 if (!dd->autoidle_reg)
691 v = omap2_clk_readl(clk, dd->autoidle_reg);
692 v &= ~dd->autoidle_mask;
693 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
694 omap2_clk_writel(v, clk, dd->autoidle_reg);
698 /* Clock control for DPLL outputs */
700 /* Find the parent DPLL for the given clkoutx2 clock */
701 static struct clk_hw_omap *omap3_find_clkoutx2_dpll(struct clk_hw *hw)
703 struct clk_hw_omap *pclk = NULL;
706 /* Walk up the parents of clk, looking for a DPLL */
709 parent = __clk_get_parent(hw->clk);
710 hw = __clk_get_hw(parent);
711 } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
714 pclk = to_clk_hw_omap(hw);
715 } while (pclk && !pclk->dpll_data);
717 /* clk does not have a DPLL as a parent? error in the clock data */
727 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
728 * @clk: DPLL output struct clk
730 * Using parent clock DPLL data, look up DPLL state. If locked, set our
731 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
733 unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
734 unsigned long parent_rate)
736 const struct dpll_data *dd;
739 struct clk_hw_omap *pclk = NULL;
744 pclk = omap3_find_clkoutx2_dpll(hw);
749 dd = pclk->dpll_data;
751 WARN_ON(!dd->enable_mask);
753 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
754 v >>= __ffs(dd->enable_mask);
755 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
758 rate = parent_rate * 2;
762 int omap3_clkoutx2_set_rate(struct clk_hw *hw, unsigned long rate,
763 unsigned long parent_rate)
768 long omap3_clkoutx2_round_rate(struct clk_hw *hw, unsigned long rate,
769 unsigned long *prate)
771 const struct dpll_data *dd;
773 struct clk_hw_omap *pclk = NULL;
778 pclk = omap3_find_clkoutx2_dpll(hw);
783 dd = pclk->dpll_data;
785 /* TYPE J does not have a clkoutx2 */
786 if (dd->flags & DPLL_J_TYPE) {
787 *prate = __clk_round_rate(__clk_get_parent(pclk->hw.clk), rate);
791 WARN_ON(!dd->enable_mask);
793 v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
794 v >>= __ffs(dd->enable_mask);
796 /* If in bypass, the rate is fixed to the bypass rate*/
797 if (v != OMAP3XXX_EN_DPLL_LOCKED)
800 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
801 unsigned long best_parent;
803 best_parent = (rate / 2);
804 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
811 /* OMAP3/4 non-CORE DPLL clkops */
812 const struct clk_hw_omap_ops clkhwops_omap3_dpll = {
813 .allow_idle = omap3_dpll_allow_idle,
814 .deny_idle = omap3_dpll_deny_idle,