arch/arm/mach-omap2/gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/ioport.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/io.h>
  25 #include <linux/module.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28
  29 #include <asm/mach-types.h>
  30 #include <plat/gpmc.h>
  31
  32 #include <plat/cpu.h>
  33 #include <plat/gpmc.h>
  34 #include <plat/sdrc.h>
  35 #include <plat/omap_device.h>
  36
  37 #include "soc.h"
  38 #include "common.h"
  39
  40 #define DEVICE_NAME             "omap-gpmc"
  41
  42 /* GPMC register offsets */
  43 #define GPMC_REVISION           0x00
  44 #define GPMC_SYSCONFIG          0x10
  45 #define GPMC_SYSSTATUS          0x14
  46 #define GPMC_IRQSTATUS          0x18
  47 #define GPMC_IRQENABLE          0x1c
  48 #define GPMC_TIMEOUT_CONTROL    0x40
  49 #define GPMC_ERR_ADDRESS        0x44
  50 #define GPMC_ERR_TYPE           0x48
  51 #define GPMC_CONFIG             0x50
  52 #define GPMC_STATUS             0x54
  53 #define GPMC_PREFETCH_CONFIG1   0x1e0
  54 #define GPMC_PREFETCH_CONFIG2   0x1e4
  55 #define GPMC_PREFETCH_CONTROL   0x1ec
  56 #define GPMC_PREFETCH_STATUS    0x1f0
  57 #define GPMC_ECC_CONFIG         0x1f4
  58 #define GPMC_ECC_CONTROL        0x1f8
  59 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  60 #define GPMC_ECC1_RESULT        0x200
  61 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  62
  63 /* GPMC ECC control settings */
  64 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  65 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  66 #define GPMC_ECC_CTRL_ECCREG1           0x001
  67 #define GPMC_ECC_CTRL_ECCREG2           0x002
  68 #define GPMC_ECC_CTRL_ECCREG3           0x003
  69 #define GPMC_ECC_CTRL_ECCREG4           0x004
  70 #define GPMC_ECC_CTRL_ECCREG5           0x005
  71 #define GPMC_ECC_CTRL_ECCREG6           0x006
  72 #define GPMC_ECC_CTRL_ECCREG7           0x007
  73 #define GPMC_ECC_CTRL_ECCREG8           0x008
  74 #define GPMC_ECC_CTRL_ECCREG9           0x009
  75
  76 #define GPMC_CS0_OFFSET         0x60
  77 #define GPMC_CS_SIZE            0x30
  78
  79 #define GPMC_MEM_START          0x00000000
  80 #define GPMC_MEM_END            0x3FFFFFFF
  81 #define BOOT_ROM_SPACE          0x100000        /* 1MB */
  82
  83 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
  84 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
  85
  86 #define CS_NUM_SHIFT            24
  87 #define ENABLE_PREFETCH         (0x1 << 7)
  88 #define DMA_MPU_MODE            2
  89
  90 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
  91 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
  92
  93 #define GPMC_HAS_WR_ACCESS              0x1
  94 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
  95
  96 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  97  */
  98 #define GPMC_NR_IRQ             2
  99
 100 struct gpmc_client_irq  {
 101         unsigned                irq;
 102         u32                     bitmask;
 103 };
 104
 105 /* Structure to save gpmc cs context */
 106 struct gpmc_cs_config {
 107         u32 config1;
 108         u32 config2;
 109         u32 config3;
 110         u32 config4;
 111         u32 config5;
 112         u32 config6;
 113         u32 config7;
 114         int is_valid;
 115 };
 116
 117 /*
 118  * Structure to save/restore gpmc context
 119  * to support core off on OMAP3
 120  */
 121 struct omap3_gpmc_regs {
 122         u32 sysconfig;
 123         u32 irqenable;
 124         u32 timeout_ctrl;
 125         u32 config;
 126         u32 prefetch_config1;
 127         u32 prefetch_config2;
 128         u32 prefetch_control;
 129         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 130 };
 131
 132 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
 133 static struct irq_chip gpmc_irq_chip;
 134 static unsigned gpmc_irq_start;
 135
 136 static struct resource  gpmc_mem_root;
 137 static struct resource  gpmc_cs_mem[GPMC_CS_NUM];
 138 static DEFINE_SPINLOCK(gpmc_mem_lock);
 139 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 140 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
 141 static struct device *gpmc_dev;
 142 static int gpmc_irq;
 143 static resource_size_t phys_base, mem_size;
 144 static unsigned gpmc_capability;
 145 static void __iomem *gpmc_base;
 146
 147 static struct clk *gpmc_l3_clk;
 148
 149 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 150
 151 static void gpmc_write_reg(int idx, u32 val)
 152 {
 153         __raw_writel(val, gpmc_base + idx);
 154 }
 155
 156 static u32 gpmc_read_reg(int idx)
 157 {
 158         return __raw_readl(gpmc_base + idx);
 159 }
 160
 161 static void gpmc_cs_write_byte(int cs, int idx, u8 val)
 162 {
 163         void __iomem *reg_addr;
 164
 165         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 166         __raw_writeb(val, reg_addr);
 167 }
 168
 169 static u8 gpmc_cs_read_byte(int cs, int idx)
 170 {
 171         void __iomem *reg_addr;
 172
 173         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 174         return __raw_readb(reg_addr);
 175 }
 176
 177 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 178 {
 179         void __iomem *reg_addr;
 180
 181         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 182         __raw_writel(val, reg_addr);
 183 }
 184
 185 u32 gpmc_cs_read_reg(int cs, int idx)
 186 {
 187         void __iomem *reg_addr;
 188
 189         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 190         return __raw_readl(reg_addr);
 191 }
 192
 193 /* TODO: Add support for gpmc_fck to clock framework and use it */
 194 unsigned long gpmc_get_fclk_period(void)
 195 {
 196         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 197
 198         if (rate == 0) {
 199                 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
 200                 return 0;
 201         }
 202
 203         rate /= 1000;
 204         rate = 1000000000 / rate;       /* In picoseconds */
 205
 206         return rate;
 207 }
 208
 209 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 210 {
 211         unsigned long tick_ps;
 212
 213         /* Calculate in picosecs to yield more exact results */
 214         tick_ps = gpmc_get_fclk_period();
 215
 216         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 217 }
 218
 219 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 220 {
 221         unsigned long tick_ps;
 222
 223         /* Calculate in picosecs to yield more exact results */
 224         tick_ps = gpmc_get_fclk_period();
 225
 226         return (time_ps + tick_ps - 1) / tick_ps;
 227 }
 228
 229 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 230 {
 231         return ticks * gpmc_get_fclk_period() / 1000;
 232 }
 233
 234 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
 235 {
 236         unsigned long ticks = gpmc_ns_to_ticks(time_ns);
 237
 238         return ticks * gpmc_get_fclk_period() / 1000;
 239 }
 240
 241 #ifdef DEBUG
 242 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 243                                int time, const char *name)
 244 #else
 245 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
 246                                int time)
 247 #endif
 248 {
 249         u32 l;
 250         int ticks, mask, nr_bits;
 251
 252         if (time == 0)
 253                 ticks = 0;
 254         else
 255                 ticks = gpmc_ns_to_ticks(time);
 256         nr_bits = end_bit - st_bit + 1;
 257         if (ticks >= 1 << nr_bits) {
 258 #ifdef DEBUG
 259                 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
 260                                 cs, name, time, ticks, 1 << nr_bits);
 261 #endif
 262                 return -1;
 263         }
 264
 265         mask = (1 << nr_bits) - 1;
 266         l = gpmc_cs_read_reg(cs, reg);
 267 #ifdef DEBUG
 268         printk(KERN_INFO
 269                 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 270                cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
 271                         (l >> st_bit) & mask, time);
 272 #endif
 273         l &= ~(mask << st_bit);
 274         l |= ticks << st_bit;
 275         gpmc_cs_write_reg(cs, reg, l);
 276
 277         return 0;
 278 }
 279
 280 #ifdef DEBUG
 281 #define GPMC_SET_ONE(reg, st, end, field) \
 282         if (set_gpmc_timing_reg(cs, (reg), (st), (end),         \
 283                         t->field, #field) < 0)                  \
 284                 return -1
 285 #else
 286 #define GPMC_SET_ONE(reg, st, end, field) \
 287         if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
 288                 return -1
 289 #endif
 290
 291 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
 292 {
 293         int div;
 294         u32 l;
 295
 296         l = sync_clk + (gpmc_get_fclk_period() - 1);
 297         div = l / gpmc_get_fclk_period();
 298         if (div > 4)
 299                 return -1;
 300         if (div <= 0)
 301                 div = 1;
 302
 303         return div;
 304 }
 305
 306 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 307 {
 308         int div;
 309         u32 l;
 310
 311         div = gpmc_cs_calc_divider(cs, t->sync_clk);
 312         if (div < 0)
 313                 return div;
 314
 315         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 316         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 317         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 318
 319         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 320         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 321         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 322
 323         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 324         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 325         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 326         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 327
 328         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 329         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 330         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 331
 332         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 333
 334         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 335                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 336         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 337                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 338
 339         /* caller is expected to have initialized CONFIG1 to cover
 340          * at least sync vs async
 341          */
 342         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 343         if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
 344 #ifdef DEBUG
 345                 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
 346                                 cs, (div * gpmc_get_fclk_period()) / 1000, div);
 347 #endif
 348                 l &= ~0x03;
 349                 l |= (div - 1);
 350                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 351         }
 352
 353         return 0;
 354 }
 355
 356 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
 357 {
 358         u32 l;
 359         u32 mask;
 360
 361         mask = (1 << GPMC_SECTION_SHIFT) - size;
 362         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 363         l &= ~0x3f;
 364         l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
 365         l &= ~(0x0f << 8);
 366         l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
 367         l |= GPMC_CONFIG7_CSVALID;
 368         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 369 }
 370
 371 static void gpmc_cs_disable_mem(int cs)
 372 {
 373         u32 l;
 374
 375         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 376         l &= ~GPMC_CONFIG7_CSVALID;
 377         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 378 }
 379
 380 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 381 {
 382         u32 l;
 383         u32 mask;
 384
 385         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 386         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 387         mask = (l >> 8) & 0x0f;
 388         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 389 }
 390
 391 static int gpmc_cs_mem_enabled(int cs)
 392 {
 393         u32 l;
 394
 395         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 396         return l & GPMC_CONFIG7_CSVALID;
 397 }
 398
 399 int gpmc_cs_set_reserved(int cs, int reserved)
 400 {
 401         if (cs > GPMC_CS_NUM)
 402                 return -ENODEV;
 403
 404         gpmc_cs_map &= ~(1 << cs);
 405         gpmc_cs_map |= (reserved ? 1 : 0) << cs;
 406
 407         return 0;
 408 }
 409
 410 int gpmc_cs_reserved(int cs)
 411 {
 412         if (cs > GPMC_CS_NUM)
 413                 return -ENODEV;
 414
 415         return gpmc_cs_map & (1 << cs);
 416 }
 417
 418 static unsigned long gpmc_mem_align(unsigned long size)
 419 {
 420         int order;
 421
 422         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 423         order = GPMC_CHUNK_SHIFT - 1;
 424         do {
 425                 size >>= 1;
 426                 order++;
 427         } while (size);
 428         size = 1 << order;
 429         return size;
 430 }
 431
 432 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 433 {
 434         struct resource *res = &gpmc_cs_mem[cs];
 435         int r;
 436
 437         size = gpmc_mem_align(size);
 438         spin_lock(&gpmc_mem_lock);
 439         res->start = base;
 440         res->end = base + size - 1;
 441         r = request_resource(&gpmc_mem_root, res);
 442         spin_unlock(&gpmc_mem_lock);
 443
 444         return r;
 445 }
 446
 447 static int gpmc_cs_delete_mem(int cs)
 448 {
 449         struct resource *res = &gpmc_cs_mem[cs];
 450         int r;
 451
 452         spin_lock(&gpmc_mem_lock);
 453         r = release_resource(&gpmc_cs_mem[cs]);
 454         res->start = 0;
 455         res->end = 0;
 456         spin_unlock(&gpmc_mem_lock);
 457
 458         return r;
 459 }
 460
 461 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 462 {
 463         struct resource *res = &gpmc_cs_mem[cs];
 464         int r = -1;
 465
 466         if (cs > GPMC_CS_NUM)
 467                 return -ENODEV;
 468
 469         size = gpmc_mem_align(size);
 470         if (size > (1 << GPMC_SECTION_SHIFT))
 471                 return -ENOMEM;
 472
 473         spin_lock(&gpmc_mem_lock);
 474         if (gpmc_cs_reserved(cs)) {
 475                 r = -EBUSY;
 476                 goto out;
 477         }
 478         if (gpmc_cs_mem_enabled(cs))
 479                 r = adjust_resource(res, res->start & ~(size - 1), size);
 480         if (r < 0)
 481                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 482                                       size, NULL, NULL);
 483         if (r < 0)
 484                 goto out;
 485
 486         gpmc_cs_enable_mem(cs, res->start, resource_size(res));
 487         *base = res->start;
 488         gpmc_cs_set_reserved(cs, 1);
 489 out:
 490         spin_unlock(&gpmc_mem_lock);
 491         return r;
 492 }
 493 EXPORT_SYMBOL(gpmc_cs_request);
 494
 495 void gpmc_cs_free(int cs)
 496 {
 497         spin_lock(&gpmc_mem_lock);
 498         if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
 499                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
 500                 BUG();
 501                 spin_unlock(&gpmc_mem_lock);
 502                 return;
 503         }
 504         gpmc_cs_disable_mem(cs);
 505         release_resource(&gpmc_cs_mem[cs]);
 506         gpmc_cs_set_reserved(cs, 0);
 507         spin_unlock(&gpmc_mem_lock);
 508 }
 509 EXPORT_SYMBOL(gpmc_cs_free);
 510
 511 /**
 512  * gpmc_read_status - read access request to get the different gpmc status
 513  * @cmd: command type
 514  * @return status
 515  */
 516 int gpmc_read_status(int cmd)
 517 {
 518         int     status = -EINVAL;
 519         u32     regval = 0;
 520
 521         switch (cmd) {
 522         case GPMC_GET_IRQ_STATUS:
 523                 status = gpmc_read_reg(GPMC_IRQSTATUS);
 524                 break;
 525
 526         case GPMC_PREFETCH_FIFO_CNT:
 527                 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
 528                 status = GPMC_PREFETCH_STATUS_FIFO_CNT(regval);
 529                 break;
 530
 531         case GPMC_PREFETCH_COUNT:
 532                 regval = gpmc_read_reg(GPMC_PREFETCH_STATUS);
 533                 status = GPMC_PREFETCH_STATUS_COUNT(regval);
 534                 break;
 535
 536         case GPMC_STATUS_BUFFER:
 537                 regval = gpmc_read_reg(GPMC_STATUS);
 538                 /* 1 : buffer is available to write */
 539                 status = regval & GPMC_STATUS_BUFF_EMPTY;
 540                 break;
 541
 542         default:
 543                 printk(KERN_ERR "gpmc_read_status: Not supported\n");
 544         }
 545         return status;
 546 }
 547 EXPORT_SYMBOL(gpmc_read_status);
 548
 549 /**
 550  * gpmc_cs_configure - write request to configure gpmc
 551  * @cs: chip select number
 552  * @cmd: command type
 553  * @wval: value to write
 554  * @return status of the operation
 555  */
 556 int gpmc_cs_configure(int cs, int cmd, int wval)
 557 {
 558         int err = 0;
 559         u32 regval = 0;
 560
 561         switch (cmd) {
 562         case GPMC_ENABLE_IRQ:
 563                 gpmc_write_reg(GPMC_IRQENABLE, wval);
 564                 break;
 565
 566         case GPMC_SET_IRQ_STATUS:
 567                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
 568                 break;
 569
 570         case GPMC_CONFIG_WP:
 571                 regval = gpmc_read_reg(GPMC_CONFIG);
 572                 if (wval)
 573                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
 574                 else
 575                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
 576                 gpmc_write_reg(GPMC_CONFIG, regval);
 577                 break;
 578
 579         case GPMC_CONFIG_RDY_BSY:
 580                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 581                 if (wval)
 582                         regval |= WR_RD_PIN_MONITORING;
 583                 else
 584                         regval &= ~WR_RD_PIN_MONITORING;
 585                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 586                 break;
 587
 588         case GPMC_CONFIG_DEV_SIZE:
 589                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 590
 591                 /* clear 2 target bits */
 592                 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
 593
 594                 /* set the proper value */
 595                 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
 596
 597                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 598                 break;
 599
 600         case GPMC_CONFIG_DEV_TYPE:
 601                 regval  = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 602                 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
 603                 if (wval == GPMC_DEVICETYPE_NOR)
 604                         regval |= GPMC_CONFIG1_MUXADDDATA;
 605                 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
 606                 break;
 607
 608         default:
 609                 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
 610                 err = -EINVAL;
 611         }
 612
 613         return err;
 614 }
 615 EXPORT_SYMBOL(gpmc_cs_configure);
 616
 617 /**
 618  * gpmc_nand_read - nand specific read access request
 619  * @cs: chip select number
 620  * @cmd: command type
 621  */
 622 int gpmc_nand_read(int cs, int cmd)
 623 {
 624         int rval = -EINVAL;
 625
 626         switch (cmd) {
 627         case GPMC_NAND_DATA:
 628                 rval = gpmc_cs_read_byte(cs, GPMC_CS_NAND_DATA);
 629                 break;
 630
 631         default:
 632                 printk(KERN_ERR "gpmc_read_nand_ctrl: Not supported\n");
 633         }
 634         return rval;
 635 }
 636 EXPORT_SYMBOL(gpmc_nand_read);
 637
 638 /**
 639  * gpmc_nand_write - nand specific write request
 640  * @cs: chip select number
 641  * @cmd: command type
 642  * @wval: value to write
 643  */
 644 int gpmc_nand_write(int cs, int cmd, int wval)
 645 {
 646         int err = 0;
 647
 648         switch (cmd) {
 649         case GPMC_NAND_COMMAND:
 650                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_COMMAND, wval);
 651                 break;
 652
 653         case GPMC_NAND_ADDRESS:
 654                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_ADDRESS, wval);
 655                 break;
 656
 657         case GPMC_NAND_DATA:
 658                 gpmc_cs_write_byte(cs, GPMC_CS_NAND_DATA, wval);
 659
 660         default:
 661                 printk(KERN_ERR "gpmc_write_nand_ctrl: Not supported\n");
 662                 err = -EINVAL;
 663         }
 664         return err;
 665 }
 666 EXPORT_SYMBOL(gpmc_nand_write);
 667
 668
 669
 670 /**
 671  * gpmc_prefetch_enable - configures and starts prefetch transfer
 672  * @cs: cs (chip select) number
 673  * @fifo_th: fifo threshold to be used for read/ write
 674  * @dma_mode: dma mode enable (1) or disable (0)
 675  * @u32_count: number of bytes to be transferred
 676  * @is_write: prefetch read(0) or write post(1) mode
 677  */
 678 int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
 679                                 unsigned int u32_count, int is_write)
 680 {
 681
 682         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
 683                 pr_err("gpmc: fifo threshold is not supported\n");
 684                 return -1;
 685         } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
 686                 /* Set the amount of bytes to be prefetched */
 687                 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 688
 689                 /* Set dma/mpu mode, the prefetch read / post write and
 690                  * enable the engine. Set which cs is has requested for.
 691                  */
 692                 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
 693                                         PREFETCH_FIFOTHRESHOLD(fifo_th) |
 694                                         ENABLE_PREFETCH |
 695                                         (dma_mode << DMA_MPU_MODE) |
 696                                         (0x1 & is_write)));
 697
 698                 /*  Start the prefetch engine */
 699                 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
 700         } else {
 701                 return -EBUSY;
 702         }
 703
 704         return 0;
 705 }
 706 EXPORT_SYMBOL(gpmc_prefetch_enable);
 707
 708 /**
 709  * gpmc_prefetch_reset - disables and stops the prefetch engine
 710  */
 711 int gpmc_prefetch_reset(int cs)
 712 {
 713         u32 config1;
 714
 715         /* check if the same module/cs is trying to reset */
 716         config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
 717         if (((config1 >> CS_NUM_SHIFT) & 0x7) != cs)
 718                 return -EINVAL;
 719
 720         /* Stop the PFPW engine */
 721         gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
 722
 723         /* Reset/disable the PFPW engine */
 724         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
 725
 726         return 0;
 727 }
 728 EXPORT_SYMBOL(gpmc_prefetch_reset);
 729
 730 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
 731 {
 732         reg->gpmc_status = gpmc_base + GPMC_STATUS;
 733         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
 734                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
 735         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
 736                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
 737         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
 738                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
 739         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
 740         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
 741         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
 742         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
 743         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
 744         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
 745         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
 746         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
 747         reg->gpmc_bch_result0 = gpmc_base + GPMC_ECC_BCH_RESULT_0;
 748 }
 749
 750 int gpmc_get_client_irq(unsigned irq_config)
 751 {
 752         int i;
 753
 754         if (hweight32(irq_config) > 1)
 755                 return 0;
 756
 757         for (i = 0; i < GPMC_NR_IRQ; i++)
 758                 if (gpmc_client_irq[i].bitmask & irq_config)
 759                         return gpmc_client_irq[i].irq;
 760
 761         return 0;
 762 }
 763
 764 static int gpmc_irq_endis(unsigned irq, bool endis)
 765 {
 766         int i;
 767         u32 regval;
 768
 769         for (i = 0; i < GPMC_NR_IRQ; i++)
 770                 if (irq == gpmc_client_irq[i].irq) {
 771                         regval = gpmc_read_reg(GPMC_IRQENABLE);
 772                         if (endis)
 773                                 regval |= gpmc_client_irq[i].bitmask;
 774                         else
 775                                 regval &= ~gpmc_client_irq[i].bitmask;
 776                         gpmc_write_reg(GPMC_IRQENABLE, regval);
 777                         break;
 778                 }
 779
 780         return 0;
 781 }
 782
 783 static void gpmc_irq_disable(struct irq_data *p)
 784 {
 785         gpmc_irq_endis(p->irq, false);
 786 }
 787
 788 static void gpmc_irq_enable(struct irq_data *p)
 789 {
 790         gpmc_irq_endis(p->irq, true);
 791 }
 792
 793 static void gpmc_irq_noop(struct irq_data *data) { }
 794
 795 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 796
 797 static int gpmc_setup_irq(void)
 798 {
 799         int i;
 800         u32 regval;
 801
 802         if (!gpmc_irq)
 803                 return -EINVAL;
 804
 805         gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
 806         if (IS_ERR_VALUE(gpmc_irq_start)) {
 807                 pr_err("irq_alloc_descs failed\n");
 808                 return gpmc_irq_start;
 809         }
 810
 811         gpmc_irq_chip.name = "gpmc";
 812         gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
 813         gpmc_irq_chip.irq_enable = gpmc_irq_enable;
 814         gpmc_irq_chip.irq_disable = gpmc_irq_disable;
 815         gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
 816         gpmc_irq_chip.irq_ack = gpmc_irq_noop;
 817         gpmc_irq_chip.irq_mask = gpmc_irq_noop;
 818         gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
 819
 820         gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
 821         gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
 822
 823         for (i = 0; i < GPMC_NR_IRQ; i++) {
 824                 gpmc_client_irq[i].irq = gpmc_irq_start + i;
 825                 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
 826                                         &gpmc_irq_chip, handle_simple_irq);
 827                 set_irq_flags(gpmc_client_irq[i].irq,
 828                                 IRQF_VALID | IRQF_NOAUTOEN);
 829         }
 830
 831         /* Disable interrupts */
 832         gpmc_write_reg(GPMC_IRQENABLE, 0);
 833
 834         /* clear interrupts */
 835         regval = gpmc_read_reg(GPMC_IRQSTATUS);
 836         gpmc_write_reg(GPMC_IRQSTATUS, regval);
 837
 838         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 839 }
 840
 841 static __devexit int gpmc_free_irq(void)
 842 {
 843         int i;
 844
 845         if (gpmc_irq)
 846                 free_irq(gpmc_irq, NULL);
 847
 848         for (i = 0; i < GPMC_NR_IRQ; i++) {
 849                 irq_set_handler(gpmc_client_irq[i].irq, NULL);
 850                 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
 851                 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
 852         }
 853
 854         irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
 855
 856         return 0;
 857 }
 858
 859 static void __devexit gpmc_mem_exit(void)
 860 {
 861         int cs;
 862
 863         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 864                 if (!gpmc_cs_mem_enabled(cs))
 865                         continue;
 866                 gpmc_cs_delete_mem(cs);
 867         }
 868
 869 }
 870
 871 static int __devinit gpmc_mem_init(void)
 872 {
 873         int cs, rc;
 874         unsigned long boot_rom_space = 0;
 875
 876         /* never allocate the first page, to facilitate bug detection;
 877          * even if we didn't boot from ROM.
 878          */
 879         boot_rom_space = BOOT_ROM_SPACE;
 880         /* In apollon the CS0 is mapped as 0x0000 0000 */
 881         if (machine_is_omap_apollon())
 882                 boot_rom_space = 0;
 883         gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
 884         gpmc_mem_root.end = GPMC_MEM_END;
 885
 886         /* Reserve all regions that has been set up by bootloader */
 887         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
 888                 u32 base, size;
 889
 890                 if (!gpmc_cs_mem_enabled(cs))
 891                         continue;
 892                 gpmc_cs_get_memconf(cs, &base, &size);
 893                 rc = gpmc_cs_insert_mem(cs, base, size);
 894                 if (IS_ERR_VALUE(rc)) {
 895                         while (--cs >= 0)
 896                                 if (gpmc_cs_mem_enabled(cs))
 897                                         gpmc_cs_delete_mem(cs);
 898                         return rc;
 899                 }
 900         }
 901
 902         return 0;
 903 }
 904
 905 static __devinit int gpmc_probe(struct platform_device *pdev)
 906 {
 907         int rc;
 908         u32 l;
 909         struct resource *res;
 910
 911         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 912         if (res == NULL)
 913                 return -ENOENT;
 914
 915         phys_base = res->start;
 916         mem_size = resource_size(res);
 917
 918         gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
 919         if (!gpmc_base) {
 920                 dev_err(&pdev->dev, "error: request memory / ioremap\n");
 921                 return -EADDRNOTAVAIL;
 922         }
 923
 924         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 925         if (res == NULL)
 926                 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
 927         else
 928                 gpmc_irq = res->start;
 929
 930         gpmc_l3_clk = clk_get(&pdev->dev, "fck");
 931         if (IS_ERR(gpmc_l3_clk)) {
 932                 dev_err(&pdev->dev, "error: clk_get\n");
 933                 gpmc_irq = 0;
 934                 return PTR_ERR(gpmc_l3_clk);
 935         }
 936
 937         clk_prepare_enable(gpmc_l3_clk);
 938
 939         gpmc_dev = &pdev->dev;
 940
 941         l = gpmc_read_reg(GPMC_REVISION);
 942         if (GPMC_REVISION_MAJOR(l) > 0x4)
 943                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
 944         dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
 945                  GPMC_REVISION_MINOR(l));
 946
 947         rc = gpmc_mem_init();
 948         if (IS_ERR_VALUE(rc)) {
 949                 clk_disable_unprepare(gpmc_l3_clk);
 950                 clk_put(gpmc_l3_clk);
 951                 dev_err(gpmc_dev, "failed to reserve memory\n");
 952                 return rc;
 953         }
 954
 955         if (IS_ERR_VALUE(gpmc_setup_irq()))
 956                 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
 957
 958         return 0;
 959 }
 960
 961 static __devexit int gpmc_remove(struct platform_device *pdev)
 962 {
 963         gpmc_free_irq();
 964         gpmc_mem_exit();
 965         gpmc_dev = NULL;
 966         return 0;
 967 }
 968
 969 static struct platform_driver gpmc_driver = {
 970         .probe          = gpmc_probe,
 971         .remove         = __devexit_p(gpmc_remove),
 972         .driver         = {
 973                 .name   = DEVICE_NAME,
 974                 .owner  = THIS_MODULE,
 975         },
 976 };
 977
 978 static __init int gpmc_init(void)
 979 {
 980         return platform_driver_register(&gpmc_driver);
 981 }
 982
 983 static __exit void gpmc_exit(void)
 984 {
 985         platform_driver_unregister(&gpmc_driver);
 986
 987 }
 988
 989 postcore_initcall(gpmc_init);
 990 module_exit(gpmc_exit);
 991
 992 static int __init omap_gpmc_init(void)
 993 {
 994         struct omap_hwmod *oh;
 995         struct platform_device *pdev;
 996         char *oh_name = "gpmc";
 997
 998         oh = omap_hwmod_lookup(oh_name);
 999         if (!oh) {
1000                 pr_err("Could not look up %s\n", oh_name);
1001                 return -ENODEV;
1002         }
1003
1004         pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
1005         WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1006
1007         return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1008 }
1009 postcore_initcall(omap_gpmc_init);
1010
1011 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1012 {
1013         int i;
1014         u32 regval;
1015
1016         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1017
1018         if (!regval)
1019                 return IRQ_NONE;
1020
1021         for (i = 0; i < GPMC_NR_IRQ; i++)
1022                 if (regval & gpmc_client_irq[i].bitmask)
1023                         generic_handle_irq(gpmc_client_irq[i].irq);
1024
1025         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1026
1027         return IRQ_HANDLED;
1028 }
1029
1030 #ifdef CONFIG_ARCH_OMAP3
1031 static struct omap3_gpmc_regs gpmc_context;
1032
1033 void omap3_gpmc_save_context(void)
1034 {
1035         int i;
1036
1037         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1038         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1039         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1040         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1041         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1042         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1043         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1044         for (i = 0; i < GPMC_CS_NUM; i++) {
1045                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1046                 if (gpmc_context.cs_context[i].is_valid) {
1047                         gpmc_context.cs_context[i].config1 =
1048                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1049                         gpmc_context.cs_context[i].config2 =
1050                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1051                         gpmc_context.cs_context[i].config3 =
1052                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1053                         gpmc_context.cs_context[i].config4 =
1054                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1055                         gpmc_context.cs_context[i].config5 =
1056                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1057                         gpmc_context.cs_context[i].config6 =
1058                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1059                         gpmc_context.cs_context[i].config7 =
1060                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1061                 }
1062         }
1063 }
1064
1065 void omap3_gpmc_restore_context(void)
1066 {
1067         int i;
1068
1069         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1070         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1071         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1072         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1073         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1074         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1075         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1076         for (i = 0; i < GPMC_CS_NUM; i++) {
1077                 if (gpmc_context.cs_context[i].is_valid) {
1078                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1079                                 gpmc_context.cs_context[i].config1);
1080                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1081                                 gpmc_context.cs_context[i].config2);
1082                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1083                                 gpmc_context.cs_context[i].config3);
1084                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1085                                 gpmc_context.cs_context[i].config4);
1086                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1087                                 gpmc_context.cs_context[i].config5);
1088                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1089                                 gpmc_context.cs_context[i].config6);
1090                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1091                                 gpmc_context.cs_context[i].config7);
1092                 }
1093         }
1094 }
1095 #endif /* CONFIG_ARCH_OMAP3 */
1096
1097 /**
1098  * gpmc_enable_hwecc - enable hardware ecc functionality
1099  * @cs: chip select number
1100  * @mode: read/write mode
1101  * @dev_width: device bus width(1 for x16, 0 for x8)
1102  * @ecc_size: bytes for which ECC will be generated
1103  */
1104 int gpmc_enable_hwecc(int cs, int mode, int dev_width, int ecc_size)
1105 {
1106         unsigned int val;
1107
1108         /* check if ecc module is in used */
1109         if (gpmc_ecc_used != -EINVAL)
1110                 return -EINVAL;
1111
1112         gpmc_ecc_used = cs;
1113
1114         /* clear ecc and enable bits */
1115         gpmc_write_reg(GPMC_ECC_CONTROL,
1116                         GPMC_ECC_CTRL_ECCCLEAR |
1117                         GPMC_ECC_CTRL_ECCREG1);
1118
1119         /* program ecc and result sizes */
1120         val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
1121         gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
1122
1123         switch (mode) {
1124         case GPMC_ECC_READ:
1125         case GPMC_ECC_WRITE:
1126                 gpmc_write_reg(GPMC_ECC_CONTROL,
1127                                 GPMC_ECC_CTRL_ECCCLEAR |
1128                                 GPMC_ECC_CTRL_ECCREG1);
1129                 break;
1130         case GPMC_ECC_READSYN:
1131                 gpmc_write_reg(GPMC_ECC_CONTROL,
1132                                 GPMC_ECC_CTRL_ECCCLEAR |
1133                                 GPMC_ECC_CTRL_ECCDISABLE);
1134                 break;
1135         default:
1136                 printk(KERN_INFO "Error: Unrecognized Mode[%d]!\n", mode);
1137                 break;
1138         }
1139
1140         /* (ECC 16 or 8 bit col) | ( CS  )  | ECC Enable */
1141         val = (dev_width << 7) | (cs << 1) | (0x1);
1142         gpmc_write_reg(GPMC_ECC_CONFIG, val);
1143         return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc);
1146
1147 /**
1148  * gpmc_calculate_ecc - generate non-inverted ecc bytes
1149  * @cs: chip select number
1150  * @dat: data pointer over which ecc is computed
1151  * @ecc_code: ecc code buffer
1152  *
1153  * Using non-inverted ECC is considered ugly since writing a blank
1154  * page (padding) will clear the ECC bytes. This is not a problem as long
1155  * no one is trying to write data on the seemingly unused page. Reading
1156  * an erased page will produce an ECC mismatch between generated and read
1157  * ECC bytes that has to be dealt with separately.
1158  */
1159 int gpmc_calculate_ecc(int cs, const u_char *dat, u_char *ecc_code)
1160 {
1161         unsigned int val = 0x0;
1162
1163         if (gpmc_ecc_used != cs)
1164                 return -EINVAL;
1165
1166         /* read ecc result */
1167         val = gpmc_read_reg(GPMC_ECC1_RESULT);
1168         *ecc_code++ = val;          /* P128e, ..., P1e */
1169         *ecc_code++ = val >> 16;    /* P128o, ..., P1o */
1170         /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
1171         *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
1172
1173         gpmc_ecc_used = -EINVAL;
1174         return 0;
1175 }
1176 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc);
1177
1178 #ifdef CONFIG_ARCH_OMAP3
1179
1180 /**
1181  * gpmc_init_hwecc_bch - initialize hardware BCH ecc functionality
1182  * @cs: chip select number
1183  * @nsectors: how many 512-byte sectors to process
1184  * @nerrors: how many errors to correct per sector (4 or 8)
1185  *
1186  * This function must be executed before any call to gpmc_enable_hwecc_bch.
1187  */
1188 int gpmc_init_hwecc_bch(int cs, int nsectors, int nerrors)
1189 {
1190         /* check if ecc module is in use */
1191         if (gpmc_ecc_used != -EINVAL)
1192                 return -EINVAL;
1193
1194         /* support only OMAP3 class */
1195         if (!cpu_is_omap34xx()) {
1196                 printk(KERN_ERR "BCH ecc is not supported on this CPU\n");
1197                 return -EINVAL;
1198         }
1199
1200         /*
1201          * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
1202          * Other chips may be added if confirmed to work.
1203          */
1204         if ((nerrors == 4) &&
1205             (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
1206                 printk(KERN_ERR "BCH 4-bit mode is not supported on this CPU\n");
1207                 return -EINVAL;
1208         }
1209
1210         /* sanity check */
1211         if (nsectors > 8) {
1212                 printk(KERN_ERR "BCH cannot process %d sectors (max is 8)\n",
1213                        nsectors);
1214                 return -EINVAL;
1215         }
1216
1217         return 0;
1218 }
1219 EXPORT_SYMBOL_GPL(gpmc_init_hwecc_bch);
1220
1221 /**
1222  * gpmc_enable_hwecc_bch - enable hardware BCH ecc functionality
1223  * @cs: chip select number
1224  * @mode: read/write mode
1225  * @dev_width: device bus width(1 for x16, 0 for x8)
1226  * @nsectors: how many 512-byte sectors to process
1227  * @nerrors: how many errors to correct per sector (4 or 8)
1228  */
1229 int gpmc_enable_hwecc_bch(int cs, int mode, int dev_width, int nsectors,
1230                           int nerrors)
1231 {
1232         unsigned int val;
1233
1234         /* check if ecc module is in use */
1235         if (gpmc_ecc_used != -EINVAL)
1236                 return -EINVAL;
1237
1238         gpmc_ecc_used = cs;
1239
1240         /* clear ecc and enable bits */
1241         gpmc_write_reg(GPMC_ECC_CONTROL, 0x1);
1242
1243         /*
1244          * When using BCH, sector size is hardcoded to 512 bytes.
1245          * Here we are using wrapping mode 6 both for reading and writing, with:
1246          *  size0 = 0  (no additional protected byte in spare area)
1247          *  size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
1248          */
1249         gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, (32 << 22) | (0 << 12));
1250
1251         /* BCH configuration */
1252         val = ((1                        << 16) | /* enable BCH */
1253                (((nerrors == 8) ? 1 : 0) << 12) | /* 8 or 4 bits */
1254                (0x06                     <<  8) | /* wrap mode = 6 */
1255                (dev_width                <<  7) | /* bus width */
1256                (((nsectors-1) & 0x7)     <<  4) | /* number of sectors */
1257                (cs                       <<  1) | /* ECC CS */
1258                (0x1));                            /* enable ECC */
1259
1260         gpmc_write_reg(GPMC_ECC_CONFIG, val);
1261         gpmc_write_reg(GPMC_ECC_CONTROL, 0x101);
1262         return 0;
1263 }
1264 EXPORT_SYMBOL_GPL(gpmc_enable_hwecc_bch);
1265
1266 /**
1267  * gpmc_calculate_ecc_bch4 - Generate 7 ecc bytes per sector of 512 data bytes
1268  * @cs:  chip select number
1269  * @dat: The pointer to data on which ecc is computed
1270  * @ecc: The ecc output buffer
1271  */
1272 int gpmc_calculate_ecc_bch4(int cs, const u_char *dat, u_char *ecc)
1273 {
1274         int i;
1275         unsigned long nsectors, reg, val1, val2;
1276
1277         if (gpmc_ecc_used != cs)
1278                 return -EINVAL;
1279
1280         nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1281
1282         for (i = 0; i < nsectors; i++) {
1283
1284                 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1285
1286                 /* Read hw-computed remainder */
1287                 val1 = gpmc_read_reg(reg + 0);
1288                 val2 = gpmc_read_reg(reg + 4);
1289
1290                 /*
1291                  * Add constant polynomial to remainder, in order to get an ecc
1292                  * sequence of 0xFFs for a buffer filled with 0xFFs; and
1293                  * left-justify the resulting polynomial.
1294                  */
1295                 *ecc++ = 0x28 ^ ((val2 >> 12) & 0xFF);
1296                 *ecc++ = 0x13 ^ ((val2 >>  4) & 0xFF);
1297                 *ecc++ = 0xcc ^ (((val2 & 0xF) << 4)|((val1 >> 28) & 0xF));
1298                 *ecc++ = 0x39 ^ ((val1 >> 20) & 0xFF);
1299                 *ecc++ = 0x96 ^ ((val1 >> 12) & 0xFF);
1300                 *ecc++ = 0xac ^ ((val1 >> 4) & 0xFF);
1301                 *ecc++ = 0x7f ^ ((val1 & 0xF) << 4);
1302         }
1303
1304         gpmc_ecc_used = -EINVAL;
1305         return 0;
1306 }
1307 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch4);
1308
1309 /**
1310  * gpmc_calculate_ecc_bch8 - Generate 13 ecc bytes per block of 512 data bytes
1311  * @cs:  chip select number
1312  * @dat: The pointer to data on which ecc is computed
1313  * @ecc: The ecc output buffer
1314  */
1315 int gpmc_calculate_ecc_bch8(int cs, const u_char *dat, u_char *ecc)
1316 {
1317         int i;
1318         unsigned long nsectors, reg, val1, val2, val3, val4;
1319
1320         if (gpmc_ecc_used != cs)
1321                 return -EINVAL;
1322
1323         nsectors = ((gpmc_read_reg(GPMC_ECC_CONFIG) >> 4) & 0x7) + 1;
1324
1325         for (i = 0; i < nsectors; i++) {
1326
1327                 reg = GPMC_ECC_BCH_RESULT_0 + 16*i;
1328
1329                 /* Read hw-computed remainder */
1330                 val1 = gpmc_read_reg(reg + 0);
1331                 val2 = gpmc_read_reg(reg + 4);
1332                 val3 = gpmc_read_reg(reg + 8);
1333                 val4 = gpmc_read_reg(reg + 12);
1334
1335                 /*
1336                  * Add constant polynomial to remainder, in order to get an ecc
1337                  * sequence of 0xFFs for a buffer filled with 0xFFs.
1338                  */
1339                 *ecc++ = 0xef ^ (val4 & 0xFF);
1340                 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
1341                 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
1342                 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
1343                 *ecc++ = 0xed ^ (val3 & 0xFF);
1344                 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
1345                 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
1346                 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
1347                 *ecc++ = 0x97 ^ (val2 & 0xFF);
1348                 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
1349                 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
1350                 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
1351                 *ecc++ = 0xb5 ^ (val1 & 0xFF);
1352         }
1353
1354         gpmc_ecc_used = -EINVAL;
1355         return 0;
1356 }
1357 EXPORT_SYMBOL_GPL(gpmc_calculate_ecc_bch8);
1358
1359 #endif /* CONFIG_ARCH_OMAP3 */