2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/platform_data/gpio-omap.h>
13 #include <linux/omap-dma.h>
14 #include <plat/dmtimer.h>
15 #include <linux/platform_data/spi-omap2-mcspi.h>
17 #include "omap_hwmod.h"
18 #include "omap_hwmod_common_data.h"
19 #include "cm-regbits-24xx.h"
20 #include "prm-regbits-24xx.h"
23 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24 { .irq = 48 + OMAP_INTC_START, },
28 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29 { .name = "dispc", .dma_req = 5 },
38 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
42 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
43 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
44 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
45 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
46 .sysc_fields = &omap_hwmod_sysc_type1,
49 struct omap_hwmod_class omap2_dispc_hwmod_class = {
51 .sysc = &omap2_dispc_sysc,
54 /* OMAP2xxx Timer Common */
55 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
59 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
60 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
61 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
62 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
63 .clockact = CLOCKACT_TEST_ICLK,
64 .sysc_fields = &omap_hwmod_sysc_type1,
67 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
69 .sysc = &omap2xxx_timer_sysc,
74 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
78 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
82 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
83 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
84 .sysc_fields = &omap_hwmod_sysc_type1,
87 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
89 .sysc = &omap2xxx_wd_timer_sysc,
90 .pre_shutdown = &omap2_wd_timer_disable,
91 .reset = &omap2_wd_timer_reset,
96 * general purpose io module
98 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
102 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
103 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
104 SYSS_HAS_RESET_STATUS),
105 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
106 .sysc_fields = &omap_hwmod_sysc_type1,
109 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
111 .sysc = &omap2xxx_gpio_sysc,
116 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
120 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
121 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
122 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
123 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
124 .sysc_fields = &omap_hwmod_sysc_type1,
127 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
129 .sysc = &omap2xxx_dma_sysc,
134 * mailbox module allowing communication between the on-chip processors
135 * using a queued mailbox-interrupt mechanism.
138 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
142 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
143 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
144 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
145 .sysc_fields = &omap_hwmod_sysc_type1,
148 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
150 .sysc = &omap2xxx_mailbox_sysc,
155 * multichannel serial port interface (mcspi) / master/slave synchronous serial
159 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
163 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
164 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
165 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
166 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
167 .sysc_fields = &omap_hwmod_sysc_type1,
170 struct omap_hwmod_class omap2xxx_mcspi_class = {
172 .sysc = &omap2xxx_mcspi_sysc,
173 .rev = OMAP2_MCSPI_REV,
178 * general purpose memory controller
181 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
185 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
186 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
187 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
188 .sysc_fields = &omap_hwmod_sysc_type1,
191 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
193 .sysc = &omap2xxx_gpmc_sysc,
201 struct omap_hwmod omap2xxx_l3_main_hwmod = {
203 .class = &l3_hwmod_class,
204 .flags = HWMOD_NO_IDLEST,
208 struct omap_hwmod omap2xxx_l4_core_hwmod = {
210 .class = &l4_hwmod_class,
211 .flags = HWMOD_NO_IDLEST,
215 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
217 .class = &l4_hwmod_class,
218 .flags = HWMOD_NO_IDLEST,
222 static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
223 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
227 struct omap_hwmod omap2xxx_mpu_hwmod = {
229 .mpu_irqs = omap2xxx_mpu_irqs,
230 .class = &mpu_hwmod_class,
231 .main_clk = "mpu_ck",
235 struct omap_hwmod omap2xxx_iva_hwmod = {
237 .class = &iva_hwmod_class,
240 /* always-on timers dev attribute */
241 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
242 .timer_capability = OMAP_TIMER_ALWON,
245 /* pwm timers dev attribute */
246 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
247 .timer_capability = OMAP_TIMER_HAS_PWM,
250 /* timers with DSP interrupt dev attribute */
251 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
252 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
257 struct omap_hwmod omap2xxx_timer1_hwmod = {
259 .mpu_irqs = omap2_timer1_mpu_irqs,
260 .main_clk = "gpt1_fck",
264 .module_bit = OMAP24XX_EN_GPT1_SHIFT,
265 .module_offs = WKUP_MOD,
267 .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
270 .dev_attr = &capability_alwon_dev_attr,
271 .class = &omap2xxx_timer_hwmod_class,
272 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
277 struct omap_hwmod omap2xxx_timer2_hwmod = {
279 .mpu_irqs = omap2_timer2_mpu_irqs,
280 .main_clk = "gpt2_fck",
284 .module_bit = OMAP24XX_EN_GPT2_SHIFT,
285 .module_offs = CORE_MOD,
287 .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
290 .class = &omap2xxx_timer_hwmod_class,
291 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
296 struct omap_hwmod omap2xxx_timer3_hwmod = {
298 .mpu_irqs = omap2_timer3_mpu_irqs,
299 .main_clk = "gpt3_fck",
303 .module_bit = OMAP24XX_EN_GPT3_SHIFT,
304 .module_offs = CORE_MOD,
306 .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
309 .class = &omap2xxx_timer_hwmod_class,
310 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
315 struct omap_hwmod omap2xxx_timer4_hwmod = {
317 .mpu_irqs = omap2_timer4_mpu_irqs,
318 .main_clk = "gpt4_fck",
322 .module_bit = OMAP24XX_EN_GPT4_SHIFT,
323 .module_offs = CORE_MOD,
325 .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
328 .class = &omap2xxx_timer_hwmod_class,
329 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
334 struct omap_hwmod omap2xxx_timer5_hwmod = {
336 .mpu_irqs = omap2_timer5_mpu_irqs,
337 .main_clk = "gpt5_fck",
341 .module_bit = OMAP24XX_EN_GPT5_SHIFT,
342 .module_offs = CORE_MOD,
344 .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
347 .dev_attr = &capability_dsp_dev_attr,
348 .class = &omap2xxx_timer_hwmod_class,
349 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
354 struct omap_hwmod omap2xxx_timer6_hwmod = {
356 .mpu_irqs = omap2_timer6_mpu_irqs,
357 .main_clk = "gpt6_fck",
361 .module_bit = OMAP24XX_EN_GPT6_SHIFT,
362 .module_offs = CORE_MOD,
364 .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
367 .dev_attr = &capability_dsp_dev_attr,
368 .class = &omap2xxx_timer_hwmod_class,
369 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
374 struct omap_hwmod omap2xxx_timer7_hwmod = {
376 .mpu_irqs = omap2_timer7_mpu_irqs,
377 .main_clk = "gpt7_fck",
381 .module_bit = OMAP24XX_EN_GPT7_SHIFT,
382 .module_offs = CORE_MOD,
384 .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
387 .dev_attr = &capability_dsp_dev_attr,
388 .class = &omap2xxx_timer_hwmod_class,
389 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
394 struct omap_hwmod omap2xxx_timer8_hwmod = {
396 .mpu_irqs = omap2_timer8_mpu_irqs,
397 .main_clk = "gpt8_fck",
401 .module_bit = OMAP24XX_EN_GPT8_SHIFT,
402 .module_offs = CORE_MOD,
404 .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
407 .dev_attr = &capability_dsp_dev_attr,
408 .class = &omap2xxx_timer_hwmod_class,
409 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
414 struct omap_hwmod omap2xxx_timer9_hwmod = {
416 .mpu_irqs = omap2_timer9_mpu_irqs,
417 .main_clk = "gpt9_fck",
421 .module_bit = OMAP24XX_EN_GPT9_SHIFT,
422 .module_offs = CORE_MOD,
424 .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
427 .dev_attr = &capability_pwm_dev_attr,
428 .class = &omap2xxx_timer_hwmod_class,
429 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
434 struct omap_hwmod omap2xxx_timer10_hwmod = {
436 .mpu_irqs = omap2_timer10_mpu_irqs,
437 .main_clk = "gpt10_fck",
441 .module_bit = OMAP24XX_EN_GPT10_SHIFT,
442 .module_offs = CORE_MOD,
444 .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
447 .dev_attr = &capability_pwm_dev_attr,
448 .class = &omap2xxx_timer_hwmod_class,
449 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
454 struct omap_hwmod omap2xxx_timer11_hwmod = {
456 .mpu_irqs = omap2_timer11_mpu_irqs,
457 .main_clk = "gpt11_fck",
461 .module_bit = OMAP24XX_EN_GPT11_SHIFT,
462 .module_offs = CORE_MOD,
464 .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
467 .dev_attr = &capability_pwm_dev_attr,
468 .class = &omap2xxx_timer_hwmod_class,
469 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
474 struct omap_hwmod omap2xxx_timer12_hwmod = {
476 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
477 .main_clk = "gpt12_fck",
481 .module_bit = OMAP24XX_EN_GPT12_SHIFT,
482 .module_offs = CORE_MOD,
484 .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
487 .dev_attr = &capability_pwm_dev_attr,
488 .class = &omap2xxx_timer_hwmod_class,
489 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
493 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
495 .class = &omap2xxx_wd_timer_hwmod_class,
496 .main_clk = "mpu_wdt_fck",
500 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
501 .module_offs = WKUP_MOD,
503 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
510 struct omap_hwmod omap2xxx_uart1_hwmod = {
512 .mpu_irqs = omap2_uart1_mpu_irqs,
513 .sdma_reqs = omap2_uart1_sdma_reqs,
514 .main_clk = "uart1_fck",
517 .module_offs = CORE_MOD,
519 .module_bit = OMAP24XX_EN_UART1_SHIFT,
521 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
524 .class = &omap2_uart_class,
529 struct omap_hwmod omap2xxx_uart2_hwmod = {
531 .mpu_irqs = omap2_uart2_mpu_irqs,
532 .sdma_reqs = omap2_uart2_sdma_reqs,
533 .main_clk = "uart2_fck",
536 .module_offs = CORE_MOD,
538 .module_bit = OMAP24XX_EN_UART2_SHIFT,
540 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
543 .class = &omap2_uart_class,
548 struct omap_hwmod omap2xxx_uart3_hwmod = {
550 .mpu_irqs = omap2_uart3_mpu_irqs,
551 .sdma_reqs = omap2_uart3_sdma_reqs,
552 .main_clk = "uart3_fck",
555 .module_offs = CORE_MOD,
557 .module_bit = OMAP24XX_EN_UART3_SHIFT,
559 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
562 .class = &omap2_uart_class,
567 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
569 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
570 * driver does not use these clocks.
572 { .role = "tv_clk", .clk = "dss_54m_fck" },
573 { .role = "sys_clk", .clk = "dss2_fck" },
576 struct omap_hwmod omap2xxx_dss_core_hwmod = {
578 .class = &omap2_dss_hwmod_class,
579 .main_clk = "dss1_fck", /* instead of dss_fck */
580 .sdma_reqs = omap2xxx_dss_sdma_chs,
584 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
585 .module_offs = CORE_MOD,
587 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
590 .opt_clks = dss_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
592 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
595 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
597 .class = &omap2_dispc_hwmod_class,
598 .mpu_irqs = omap2_dispc_irqs,
599 .main_clk = "dss1_fck",
603 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
604 .module_offs = CORE_MOD,
606 .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
609 .flags = HWMOD_NO_IDLEST,
610 .dev_attr = &omap2_3_dss_dispc_dev_attr
613 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
614 { .role = "ick", .clk = "dss_ick" },
617 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
619 .class = &omap2_rfbi_hwmod_class,
620 .main_clk = "dss1_fck",
624 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
625 .module_offs = CORE_MOD,
628 .opt_clks = dss_rfbi_opt_clks,
629 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
630 .flags = HWMOD_NO_IDLEST,
633 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
635 .class = &omap2_venc_hwmod_class,
636 .main_clk = "dss_54m_fck",
640 .module_bit = OMAP24XX_EN_DSS1_SHIFT,
641 .module_offs = CORE_MOD,
644 .flags = HWMOD_NO_IDLEST,
648 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
654 struct omap_hwmod omap2xxx_gpio1_hwmod = {
656 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657 .mpu_irqs = omap2_gpio1_irqs,
658 .main_clk = "gpios_fck",
662 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
663 .module_offs = WKUP_MOD,
665 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
668 .class = &omap2xxx_gpio_hwmod_class,
669 .dev_attr = &omap2xxx_gpio_dev_attr,
673 struct omap_hwmod omap2xxx_gpio2_hwmod = {
675 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
676 .mpu_irqs = omap2_gpio2_irqs,
677 .main_clk = "gpios_fck",
681 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682 .module_offs = WKUP_MOD,
684 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
687 .class = &omap2xxx_gpio_hwmod_class,
688 .dev_attr = &omap2xxx_gpio_dev_attr,
692 struct omap_hwmod omap2xxx_gpio3_hwmod = {
694 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
695 .mpu_irqs = omap2_gpio3_irqs,
696 .main_clk = "gpios_fck",
700 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
701 .module_offs = WKUP_MOD,
703 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
706 .class = &omap2xxx_gpio_hwmod_class,
707 .dev_attr = &omap2xxx_gpio_dev_attr,
711 struct omap_hwmod omap2xxx_gpio4_hwmod = {
713 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714 .mpu_irqs = omap2_gpio4_irqs,
715 .main_clk = "gpios_fck",
719 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
720 .module_offs = WKUP_MOD,
722 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
725 .class = &omap2xxx_gpio_hwmod_class,
726 .dev_attr = &omap2xxx_gpio_dev_attr,
730 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
734 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
736 .mpu_irqs = omap2_mcspi1_mpu_irqs,
737 .sdma_reqs = omap2_mcspi1_sdma_reqs,
738 .main_clk = "mcspi1_fck",
741 .module_offs = CORE_MOD,
743 .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
745 .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
748 .class = &omap2xxx_mcspi_class,
749 .dev_attr = &omap_mcspi1_dev_attr,
753 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
757 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
759 .mpu_irqs = omap2_mcspi2_mpu_irqs,
760 .sdma_reqs = omap2_mcspi2_sdma_reqs,
761 .main_clk = "mcspi2_fck",
764 .module_offs = CORE_MOD,
766 .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
768 .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
771 .class = &omap2xxx_mcspi_class,
772 .dev_attr = &omap_mcspi2_dev_attr,
775 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
779 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
780 .name = "counter_32k",
781 .main_clk = "func_32k_ck",
784 .module_offs = WKUP_MOD,
786 .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
788 .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
791 .class = &omap2xxx_counter_hwmod_class,
795 static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
800 struct omap_hwmod omap2xxx_gpmc_hwmod = {
802 .class = &omap2xxx_gpmc_hwmod_class,
803 .mpu_irqs = omap2xxx_gpmc_irqs,
804 .main_clk = "gpmc_fck",
806 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
807 * block. It is not being added due to any known bugs with
808 * resetting the GPMC IP block, but rather because any timings
809 * set by the bootloader are not being correctly programmed by
810 * the kernel from the board file or DT data.
811 * HWMOD_INIT_NO_RESET should be removed ASAP.
813 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
818 .module_bit = OMAP24XX_EN_GPMC_MASK,
819 .module_offs = CORE_MOD,
826 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
830 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
831 SYSS_HAS_RESET_STATUS),
832 .sysc_fields = &omap_hwmod_sysc_type1,
835 static struct omap_hwmod_class omap2_rng_hwmod_class = {
837 .sysc = &omap2_rng_sysc,
840 static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
845 struct omap_hwmod omap2xxx_rng_hwmod = {
847 .mpu_irqs = omap2_rng_mpu_irqs,
851 .module_offs = CORE_MOD,
853 .module_bit = OMAP24XX_EN_RNG_SHIFT,
855 .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
859 * XXX The first read from the SYSSTATUS register of the RNG
860 * after the SYSCONFIG SOFTRESET bit is set triggers an
861 * imprecise external abort. It's unclear why this happens.
862 * Until this is analyzed, skip the IP block reset.
864 .flags = HWMOD_INIT_NO_RESET,
865 .class = &omap2_rng_hwmod_class,