3 * Copyright (C) 2013 Texas Instruments Incorporated
5 * Hwmod common for AM335x and AM43x
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/hsmmc-omap.h>
19 #include <linux/platform_data/spi-omap2-mcspi.h>
20 #include "omap_hwmod.h"
25 #include "omap_hwmod_33xx_43xx_common_data.h"
29 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
30 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
31 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
35 * instance(s): l3_main, l3_s, l3_instr
37 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
41 struct omap_hwmod am33xx_l3_main_hwmod = {
43 .class = &am33xx_l3_hwmod_class,
44 .clkdm_name = "l3_clkdm",
45 .flags = HWMOD_INIT_NO_IDLE,
46 .main_clk = "l3_gclk",
49 .modulemode = MODULEMODE_SWCTRL,
55 struct omap_hwmod am33xx_l3_s_hwmod = {
57 .class = &am33xx_l3_hwmod_class,
58 .clkdm_name = "l3s_clkdm",
62 struct omap_hwmod am33xx_l3_instr_hwmod = {
64 .class = &am33xx_l3_hwmod_class,
65 .clkdm_name = "l3_clkdm",
66 .flags = HWMOD_INIT_NO_IDLE,
67 .main_clk = "l3_gclk",
70 .modulemode = MODULEMODE_SWCTRL,
77 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
79 struct omap_hwmod_class am33xx_l4_hwmod_class = {
84 struct omap_hwmod am33xx_l4_ls_hwmod = {
86 .class = &am33xx_l4_hwmod_class,
87 .clkdm_name = "l4ls_clkdm",
88 .flags = HWMOD_INIT_NO_IDLE,
89 .main_clk = "l4ls_gclk",
92 .modulemode = MODULEMODE_SWCTRL,
98 struct omap_hwmod am33xx_l4_wkup_hwmod = {
100 .class = &am33xx_l4_hwmod_class,
101 .clkdm_name = "l4_wkup_clkdm",
102 .flags = HWMOD_INIT_NO_IDLE,
105 .modulemode = MODULEMODE_SWCTRL,
113 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
117 struct omap_hwmod am33xx_mpu_hwmod = {
119 .class = &am33xx_mpu_hwmod_class,
120 .clkdm_name = "mpu_clkdm",
121 .flags = HWMOD_INIT_NO_IDLE,
122 .main_clk = "dpll_mpu_m2_ck",
125 .modulemode = MODULEMODE_SWCTRL,
132 * Wakeup controller sub-system under wakeup domain
134 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
140 * Programmable Real-Time Unit and Industrial Communication Subsystem
142 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
146 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
147 { .name = "pruss", .rst_shift = 1 },
151 /* Pseudo hwmod for reset control purpose only */
152 struct omap_hwmod am33xx_pruss_hwmod = {
154 .class = &am33xx_pruss_hwmod_class,
155 .clkdm_name = "pruss_ocp_clkdm",
156 .main_clk = "pruss_ocp_gclk",
159 .modulemode = MODULEMODE_SWCTRL,
162 .rst_lines = am33xx_pruss_resets,
163 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
167 /* Pseudo hwmod for reset control purpose only */
168 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
172 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
173 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
176 struct omap_hwmod am33xx_gfx_hwmod = {
178 .class = &am33xx_gfx_hwmod_class,
179 .clkdm_name = "gfx_l3_clkdm",
180 .main_clk = "gfx_fck_div_ck",
183 .modulemode = MODULEMODE_SWCTRL,
186 .rst_lines = am33xx_gfx_resets,
187 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
192 * power and reset manager (whole prcm infrastructure)
194 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
199 struct omap_hwmod am33xx_prcm_hwmod = {
201 .class = &am33xx_prcm_hwmod_class,
202 .clkdm_name = "l4_wkup_clkdm",
208 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
212 .sysc_flags = SYSS_HAS_RESET_STATUS,
215 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
217 .sysc = &am33xx_aes0_sysc,
220 struct omap_hwmod am33xx_aes0_hwmod = {
222 .class = &am33xx_aes0_hwmod_class,
223 .clkdm_name = "l3_clkdm",
224 .main_clk = "aes0_fck",
227 .modulemode = MODULEMODE_SWCTRL,
232 /* sha0 HIB2 (the 'P' (public) device) */
233 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
237 .sysc_flags = SYSS_HAS_RESET_STATUS,
240 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
242 .sysc = &am33xx_sha0_sysc,
245 struct omap_hwmod am33xx_sha0_hwmod = {
247 .class = &am33xx_sha0_hwmod_class,
248 .clkdm_name = "l3_clkdm",
249 .main_clk = "l3_gclk",
252 .modulemode = MODULEMODE_SWCTRL,
258 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
262 struct omap_hwmod am33xx_ocmcram_hwmod = {
264 .class = &am33xx_ocmcram_hwmod_class,
265 .clkdm_name = "l3_clkdm",
266 .flags = HWMOD_INIT_NO_IDLE,
267 .main_clk = "l3_gclk",
270 .modulemode = MODULEMODE_SWCTRL,
275 /* 'smartreflex' class */
276 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
277 .name = "smartreflex",
281 struct omap_hwmod am33xx_smartreflex0_hwmod = {
282 .name = "smartreflex0",
283 .class = &am33xx_smartreflex_hwmod_class,
284 .clkdm_name = "l4_wkup_clkdm",
285 .main_clk = "smartreflex0_fck",
288 .modulemode = MODULEMODE_SWCTRL,
294 struct omap_hwmod am33xx_smartreflex1_hwmod = {
295 .name = "smartreflex1",
296 .class = &am33xx_smartreflex_hwmod_class,
297 .clkdm_name = "l4_wkup_clkdm",
298 .main_clk = "smartreflex1_fck",
301 .modulemode = MODULEMODE_SWCTRL,
307 * 'control' module class
309 struct omap_hwmod_class am33xx_control_hwmod_class = {
315 * cpsw/cpgmac sub system
317 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
321 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
322 SYSS_HAS_RESET_STATUS),
323 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
325 .sysc_fields = &omap_hwmod_sysc_type3,
328 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
330 .sysc = &am33xx_cpgmac_sysc,
333 struct omap_hwmod am33xx_cpgmac0_hwmod = {
335 .class = &am33xx_cpgmac0_hwmod_class,
336 .clkdm_name = "cpsw_125mhz_clkdm",
337 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
338 .main_clk = "cpsw_125mhz_gclk",
342 .modulemode = MODULEMODE_SWCTRL,
350 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
351 .name = "davinci_mdio",
354 struct omap_hwmod am33xx_mdio_hwmod = {
355 .name = "davinci_mdio",
356 .class = &am33xx_mdio_hwmod_class,
357 .clkdm_name = "cpsw_125mhz_clkdm",
358 .main_clk = "cpsw_125mhz_gclk",
364 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
369 struct omap_hwmod am33xx_dcan0_hwmod = {
371 .class = &am33xx_dcan_hwmod_class,
372 .clkdm_name = "l4ls_clkdm",
373 .main_clk = "dcan0_fck",
376 .modulemode = MODULEMODE_SWCTRL,
382 struct omap_hwmod am33xx_dcan1_hwmod = {
384 .class = &am33xx_dcan_hwmod_class,
385 .clkdm_name = "l4ls_clkdm",
386 .main_clk = "dcan1_fck",
389 .modulemode = MODULEMODE_SWCTRL,
395 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
399 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
400 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
401 SYSS_HAS_RESET_STATUS),
402 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
403 .sysc_fields = &omap_hwmod_sysc_type1,
406 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
408 .sysc = &am33xx_elm_sysc,
411 struct omap_hwmod am33xx_elm_hwmod = {
413 .class = &am33xx_elm_hwmod_class,
414 .clkdm_name = "l4ls_clkdm",
415 .main_clk = "l4ls_gclk",
418 .modulemode = MODULEMODE_SWCTRL,
424 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
427 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
428 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
429 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
430 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
431 .sysc_fields = &omap_hwmod_sysc_type2,
434 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
436 .sysc = &am33xx_epwmss_sysc,
439 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
443 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
447 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
452 struct omap_hwmod am33xx_epwmss0_hwmod = {
454 .class = &am33xx_epwmss_hwmod_class,
455 .clkdm_name = "l4ls_clkdm",
456 .main_clk = "l4ls_gclk",
459 .modulemode = MODULEMODE_SWCTRL,
465 struct omap_hwmod am33xx_ecap0_hwmod = {
467 .class = &am33xx_ecap_hwmod_class,
468 .clkdm_name = "l4ls_clkdm",
469 .main_clk = "l4ls_gclk",
473 struct omap_hwmod am33xx_eqep0_hwmod = {
475 .class = &am33xx_eqep_hwmod_class,
476 .clkdm_name = "l4ls_clkdm",
477 .main_clk = "l4ls_gclk",
481 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
483 .class = &am33xx_ehrpwm_hwmod_class,
484 .clkdm_name = "l4ls_clkdm",
485 .main_clk = "l4ls_gclk",
489 struct omap_hwmod am33xx_epwmss1_hwmod = {
491 .class = &am33xx_epwmss_hwmod_class,
492 .clkdm_name = "l4ls_clkdm",
493 .main_clk = "l4ls_gclk",
496 .modulemode = MODULEMODE_SWCTRL,
502 struct omap_hwmod am33xx_ecap1_hwmod = {
504 .class = &am33xx_ecap_hwmod_class,
505 .clkdm_name = "l4ls_clkdm",
506 .main_clk = "l4ls_gclk",
510 struct omap_hwmod am33xx_eqep1_hwmod = {
512 .class = &am33xx_eqep_hwmod_class,
513 .clkdm_name = "l4ls_clkdm",
514 .main_clk = "l4ls_gclk",
518 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
520 .class = &am33xx_ehrpwm_hwmod_class,
521 .clkdm_name = "l4ls_clkdm",
522 .main_clk = "l4ls_gclk",
526 struct omap_hwmod am33xx_epwmss2_hwmod = {
528 .class = &am33xx_epwmss_hwmod_class,
529 .clkdm_name = "l4ls_clkdm",
530 .main_clk = "l4ls_gclk",
533 .modulemode = MODULEMODE_SWCTRL,
539 struct omap_hwmod am33xx_ecap2_hwmod = {
541 .class = &am33xx_ecap_hwmod_class,
542 .clkdm_name = "l4ls_clkdm",
543 .main_clk = "l4ls_gclk",
547 struct omap_hwmod am33xx_eqep2_hwmod = {
549 .class = &am33xx_eqep_hwmod_class,
550 .clkdm_name = "l4ls_clkdm",
551 .main_clk = "l4ls_gclk",
555 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
557 .class = &am33xx_ehrpwm_hwmod_class,
558 .clkdm_name = "l4ls_clkdm",
559 .main_clk = "l4ls_gclk",
563 * 'gpio' class: for gpio 0,1,2,3
565 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
569 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
570 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
571 SYSS_HAS_RESET_STATUS),
572 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
574 .sysc_fields = &omap_hwmod_sysc_type1,
577 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
579 .sysc = &am33xx_gpio_sysc,
583 struct omap_gpio_dev_attr gpio_dev_attr = {
589 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
590 { .role = "dbclk", .clk = "gpio1_dbclk" },
593 struct omap_hwmod am33xx_gpio1_hwmod = {
595 .class = &am33xx_gpio_hwmod_class,
596 .clkdm_name = "l4ls_clkdm",
597 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
598 .main_clk = "l4ls_gclk",
601 .modulemode = MODULEMODE_SWCTRL,
604 .opt_clks = gpio1_opt_clks,
605 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
606 .dev_attr = &gpio_dev_attr,
610 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
611 { .role = "dbclk", .clk = "gpio2_dbclk" },
614 struct omap_hwmod am33xx_gpio2_hwmod = {
616 .class = &am33xx_gpio_hwmod_class,
617 .clkdm_name = "l4ls_clkdm",
618 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
619 .main_clk = "l4ls_gclk",
622 .modulemode = MODULEMODE_SWCTRL,
625 .opt_clks = gpio2_opt_clks,
626 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
627 .dev_attr = &gpio_dev_attr,
631 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
632 { .role = "dbclk", .clk = "gpio3_dbclk" },
635 struct omap_hwmod am33xx_gpio3_hwmod = {
637 .class = &am33xx_gpio_hwmod_class,
638 .clkdm_name = "l4ls_clkdm",
639 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
640 .main_clk = "l4ls_gclk",
643 .modulemode = MODULEMODE_SWCTRL,
646 .opt_clks = gpio3_opt_clks,
647 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
648 .dev_attr = &gpio_dev_attr,
652 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
656 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
657 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
659 .sysc_fields = &omap_hwmod_sysc_type1,
662 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
667 struct omap_hwmod am33xx_gpmc_hwmod = {
669 .class = &am33xx_gpmc_hwmod_class,
670 .clkdm_name = "l3s_clkdm",
671 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
672 .main_clk = "l3s_gclk",
675 .modulemode = MODULEMODE_SWCTRL,
681 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
684 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
685 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
686 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
687 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
689 .sysc_fields = &omap_hwmod_sysc_type1,
692 static struct omap_hwmod_class i2c_class = {
694 .sysc = &am33xx_i2c_sysc,
695 .rev = OMAP_I2C_IP_VERSION_2,
696 .reset = &omap_i2c_reset,
699 static struct omap_i2c_dev_attr i2c_dev_attr = {
700 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
704 struct omap_hwmod am33xx_i2c1_hwmod = {
707 .clkdm_name = "l4_wkup_clkdm",
708 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
709 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
712 .modulemode = MODULEMODE_SWCTRL,
715 .dev_attr = &i2c_dev_attr,
719 struct omap_hwmod am33xx_i2c2_hwmod = {
722 .clkdm_name = "l4ls_clkdm",
723 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
724 .main_clk = "dpll_per_m2_div4_ck",
727 .modulemode = MODULEMODE_SWCTRL,
730 .dev_attr = &i2c_dev_attr,
734 struct omap_hwmod am33xx_i2c3_hwmod = {
737 .clkdm_name = "l4ls_clkdm",
738 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
739 .main_clk = "dpll_per_m2_div4_ck",
742 .modulemode = MODULEMODE_SWCTRL,
745 .dev_attr = &i2c_dev_attr,
750 * mailbox module allowing communication between the on-chip processors using a
751 * queued mailbox-interrupt mechanism.
753 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
756 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
759 .sysc_fields = &omap_hwmod_sysc_type2,
762 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
764 .sysc = &am33xx_mailbox_sysc,
767 struct omap_hwmod am33xx_mailbox_hwmod = {
769 .class = &am33xx_mailbox_hwmod_class,
770 .clkdm_name = "l4ls_clkdm",
771 .main_clk = "l4ls_gclk",
774 .modulemode = MODULEMODE_SWCTRL,
782 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
785 .sysc_flags = SYSC_HAS_SIDLEMODE,
786 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
787 .sysc_fields = &omap_hwmod_sysc_type3,
790 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
792 .sysc = &am33xx_mcasp_sysc,
796 struct omap_hwmod am33xx_mcasp0_hwmod = {
798 .class = &am33xx_mcasp_hwmod_class,
799 .clkdm_name = "l3s_clkdm",
800 .main_clk = "mcasp0_fck",
803 .modulemode = MODULEMODE_SWCTRL,
809 struct omap_hwmod am33xx_mcasp1_hwmod = {
811 .class = &am33xx_mcasp_hwmod_class,
812 .clkdm_name = "l3s_clkdm",
813 .main_clk = "mcasp1_fck",
816 .modulemode = MODULEMODE_SWCTRL,
822 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
826 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
827 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
828 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
829 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
830 .sysc_fields = &omap_hwmod_sysc_type1,
833 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
835 .sysc = &am33xx_mmc_sysc,
839 static struct omap_hsmmc_dev_attr am33xx_mmc0_dev_attr = {
840 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
843 struct omap_hwmod am33xx_mmc0_hwmod = {
845 .class = &am33xx_mmc_hwmod_class,
846 .clkdm_name = "l4ls_clkdm",
847 .main_clk = "mmc_clk",
850 .modulemode = MODULEMODE_SWCTRL,
853 .dev_attr = &am33xx_mmc0_dev_attr,
857 static struct omap_hsmmc_dev_attr am33xx_mmc1_dev_attr = {
858 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
861 struct omap_hwmod am33xx_mmc1_hwmod = {
863 .class = &am33xx_mmc_hwmod_class,
864 .clkdm_name = "l4ls_clkdm",
865 .main_clk = "mmc_clk",
868 .modulemode = MODULEMODE_SWCTRL,
871 .dev_attr = &am33xx_mmc1_dev_attr,
875 static struct omap_hsmmc_dev_attr am33xx_mmc2_dev_attr = {
876 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
878 struct omap_hwmod am33xx_mmc2_hwmod = {
880 .class = &am33xx_mmc_hwmod_class,
881 .clkdm_name = "l3s_clkdm",
882 .main_clk = "mmc_clk",
885 .modulemode = MODULEMODE_SWCTRL,
888 .dev_attr = &am33xx_mmc2_dev_attr,
895 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
898 .sysc_flags = SYSC_HAS_SIDLEMODE,
899 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
900 SIDLE_SMART | SIDLE_SMART_WKUP),
901 .sysc_fields = &omap_hwmod_sysc_type3,
904 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
906 .sysc = &am33xx_rtc_sysc,
909 struct omap_hwmod am33xx_rtc_hwmod = {
911 .class = &am33xx_rtc_hwmod_class,
912 .clkdm_name = "l4_rtc_clkdm",
913 .main_clk = "clk_32768_ck",
916 .modulemode = MODULEMODE_SWCTRL,
922 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
926 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
927 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
928 SYSS_HAS_RESET_STATUS),
929 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
930 .sysc_fields = &omap_hwmod_sysc_type1,
933 struct omap_hwmod_class am33xx_spi_hwmod_class = {
935 .sysc = &am33xx_mcspi_sysc,
936 .rev = OMAP4_MCSPI_REV,
940 struct omap2_mcspi_dev_attr mcspi_attrib = {
943 struct omap_hwmod am33xx_spi0_hwmod = {
945 .class = &am33xx_spi_hwmod_class,
946 .clkdm_name = "l4ls_clkdm",
947 .main_clk = "dpll_per_m2_div4_ck",
950 .modulemode = MODULEMODE_SWCTRL,
953 .dev_attr = &mcspi_attrib,
957 struct omap_hwmod am33xx_spi1_hwmod = {
959 .class = &am33xx_spi_hwmod_class,
960 .clkdm_name = "l4ls_clkdm",
961 .main_clk = "dpll_per_m2_div4_ck",
964 .modulemode = MODULEMODE_SWCTRL,
967 .dev_attr = &mcspi_attrib,
972 * spinlock provides hardware assistance for synchronizing the
973 * processes running on multiple processors
976 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
980 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
981 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
982 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
984 .sysc_fields = &omap_hwmod_sysc_type1,
987 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
989 .sysc = &am33xx_spinlock_sysc,
992 struct omap_hwmod am33xx_spinlock_hwmod = {
994 .class = &am33xx_spinlock_hwmod_class,
995 .clkdm_name = "l4ls_clkdm",
996 .main_clk = "l4ls_gclk",
999 .modulemode = MODULEMODE_SWCTRL,
1004 /* 'timer 2-7' class */
1005 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1007 .sysc_offs = 0x0010,
1008 .syss_offs = 0x0014,
1009 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1012 .sysc_fields = &omap_hwmod_sysc_type2,
1015 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1017 .sysc = &am33xx_timer_sysc,
1021 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1023 .sysc_offs = 0x0010,
1024 .syss_offs = 0x0014,
1025 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1026 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1027 SYSS_HAS_RESET_STATUS),
1028 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1029 .sysc_fields = &omap_hwmod_sysc_type1,
1032 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1034 .sysc = &am33xx_timer1ms_sysc,
1037 struct omap_hwmod am33xx_timer1_hwmod = {
1039 .class = &am33xx_timer1ms_hwmod_class,
1040 .clkdm_name = "l4_wkup_clkdm",
1041 .main_clk = "timer1_fck",
1044 .modulemode = MODULEMODE_SWCTRL,
1049 struct omap_hwmod am33xx_timer2_hwmod = {
1051 .class = &am33xx_timer_hwmod_class,
1052 .clkdm_name = "l4ls_clkdm",
1053 .main_clk = "timer2_fck",
1056 .modulemode = MODULEMODE_SWCTRL,
1061 struct omap_hwmod am33xx_timer3_hwmod = {
1063 .class = &am33xx_timer_hwmod_class,
1064 .clkdm_name = "l4ls_clkdm",
1065 .main_clk = "timer3_fck",
1068 .modulemode = MODULEMODE_SWCTRL,
1073 struct omap_hwmod am33xx_timer4_hwmod = {
1075 .class = &am33xx_timer_hwmod_class,
1076 .clkdm_name = "l4ls_clkdm",
1077 .main_clk = "timer4_fck",
1080 .modulemode = MODULEMODE_SWCTRL,
1085 struct omap_hwmod am33xx_timer5_hwmod = {
1087 .class = &am33xx_timer_hwmod_class,
1088 .clkdm_name = "l4ls_clkdm",
1089 .main_clk = "timer5_fck",
1092 .modulemode = MODULEMODE_SWCTRL,
1097 struct omap_hwmod am33xx_timer6_hwmod = {
1099 .class = &am33xx_timer_hwmod_class,
1100 .clkdm_name = "l4ls_clkdm",
1101 .main_clk = "timer6_fck",
1104 .modulemode = MODULEMODE_SWCTRL,
1109 struct omap_hwmod am33xx_timer7_hwmod = {
1111 .class = &am33xx_timer_hwmod_class,
1112 .clkdm_name = "l4ls_clkdm",
1113 .main_clk = "timer7_fck",
1116 .modulemode = MODULEMODE_SWCTRL,
1122 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1126 struct omap_hwmod am33xx_tpcc_hwmod = {
1128 .class = &am33xx_tpcc_hwmod_class,
1129 .clkdm_name = "l3_clkdm",
1130 .main_clk = "l3_gclk",
1133 .modulemode = MODULEMODE_SWCTRL,
1138 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1141 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1142 SYSC_HAS_MIDLEMODE),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1144 .sysc_fields = &omap_hwmod_sysc_type2,
1148 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1150 .sysc = &am33xx_tptc_sysc,
1154 struct omap_hwmod am33xx_tptc0_hwmod = {
1156 .class = &am33xx_tptc_hwmod_class,
1157 .clkdm_name = "l3_clkdm",
1158 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1159 .main_clk = "l3_gclk",
1162 .modulemode = MODULEMODE_SWCTRL,
1168 struct omap_hwmod am33xx_tptc1_hwmod = {
1170 .class = &am33xx_tptc_hwmod_class,
1171 .clkdm_name = "l3_clkdm",
1172 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1173 .main_clk = "l3_gclk",
1176 .modulemode = MODULEMODE_SWCTRL,
1182 struct omap_hwmod am33xx_tptc2_hwmod = {
1184 .class = &am33xx_tptc_hwmod_class,
1185 .clkdm_name = "l3_clkdm",
1186 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1187 .main_clk = "l3_gclk",
1190 .modulemode = MODULEMODE_SWCTRL,
1196 static struct omap_hwmod_class_sysconfig uart_sysc = {
1200 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1201 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1202 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1204 .sysc_fields = &omap_hwmod_sysc_type1,
1207 static struct omap_hwmod_class uart_class = {
1212 struct omap_hwmod am33xx_uart1_hwmod = {
1214 .class = &uart_class,
1215 .clkdm_name = "l4_wkup_clkdm",
1216 .flags = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1217 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1220 .modulemode = MODULEMODE_SWCTRL,
1225 struct omap_hwmod am33xx_uart2_hwmod = {
1227 .class = &uart_class,
1228 .clkdm_name = "l4ls_clkdm",
1229 .flags = HWMOD_SWSUP_SIDLE_ACT,
1230 .main_clk = "dpll_per_m2_div4_ck",
1233 .modulemode = MODULEMODE_SWCTRL,
1239 struct omap_hwmod am33xx_uart3_hwmod = {
1241 .class = &uart_class,
1242 .clkdm_name = "l4ls_clkdm",
1243 .flags = HWMOD_SWSUP_SIDLE_ACT,
1244 .main_clk = "dpll_per_m2_div4_ck",
1247 .modulemode = MODULEMODE_SWCTRL,
1252 struct omap_hwmod am33xx_uart4_hwmod = {
1254 .class = &uart_class,
1255 .clkdm_name = "l4ls_clkdm",
1256 .flags = HWMOD_SWSUP_SIDLE_ACT,
1257 .main_clk = "dpll_per_m2_div4_ck",
1260 .modulemode = MODULEMODE_SWCTRL,
1265 struct omap_hwmod am33xx_uart5_hwmod = {
1267 .class = &uart_class,
1268 .clkdm_name = "l4ls_clkdm",
1269 .flags = HWMOD_SWSUP_SIDLE_ACT,
1270 .main_clk = "dpll_per_m2_div4_ck",
1273 .modulemode = MODULEMODE_SWCTRL,
1278 struct omap_hwmod am33xx_uart6_hwmod = {
1280 .class = &uart_class,
1281 .clkdm_name = "l4ls_clkdm",
1282 .flags = HWMOD_SWSUP_SIDLE_ACT,
1283 .main_clk = "dpll_per_m2_div4_ck",
1286 .modulemode = MODULEMODE_SWCTRL,
1291 /* 'wd_timer' class */
1292 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1296 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1297 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1298 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1300 .sysc_fields = &omap_hwmod_sysc_type1,
1303 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1306 .pre_shutdown = &omap2_wd_timer_disable,
1310 * XXX: device.c file uses hardcoded name for watchdog timer
1311 * driver "wd_timer2, so we are also using same name as of now...
1313 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1314 .name = "wd_timer2",
1315 .class = &am33xx_wd_timer_hwmod_class,
1316 .clkdm_name = "l4_wkup_clkdm",
1317 .flags = HWMOD_SWSUP_SIDLE,
1318 .main_clk = "wdt1_fck",
1321 .modulemode = MODULEMODE_SWCTRL,
1326 static void omap_hwmod_am33xx_clkctrl(void)
1328 CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1329 CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1330 CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1331 CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1332 CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1333 CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1334 CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1335 CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1336 CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1337 CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1338 CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1339 CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1340 CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1341 CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1342 CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1343 CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1344 CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1345 CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1346 CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1347 CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1348 CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1349 CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1350 CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1351 CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1352 CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1353 CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1354 CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1355 CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1356 CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1357 CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1358 CLKCTRL(am33xx_smartreflex0_hwmod,
1359 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1360 CLKCTRL(am33xx_smartreflex1_hwmod,
1361 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1362 CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1363 CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1364 CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1365 CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1366 CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1367 CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1368 CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1369 CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1370 CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1371 CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1372 CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1373 CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1374 CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1375 CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1376 CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1377 CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1378 CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1379 CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1380 CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1381 CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1382 CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1383 CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1386 static void omap_hwmod_am33xx_rst(void)
1388 RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1389 RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1390 RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1393 void omap_hwmod_am33xx_reg(void)
1395 omap_hwmod_am33xx_clkctrl();
1396 omap_hwmod_am33xx_rst();
1399 static void omap_hwmod_am43xx_clkctrl(void)
1401 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1402 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1403 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1404 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1405 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1406 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1407 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1408 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1409 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1410 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1411 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1412 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1413 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1414 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1415 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1416 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1417 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1418 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1419 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1420 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1421 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1422 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1423 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1424 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1425 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1426 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1427 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1428 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1429 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1430 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1431 CLKCTRL(am33xx_smartreflex0_hwmod,
1432 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1433 CLKCTRL(am33xx_smartreflex1_hwmod,
1434 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1435 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1436 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1437 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1438 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1439 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1440 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1441 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1442 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1443 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1444 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1445 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1446 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1447 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1448 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1449 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1450 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1451 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1452 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1453 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1454 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1455 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1456 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1459 static void omap_hwmod_am43xx_rst(void)
1461 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1462 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1463 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1466 void omap_hwmod_am43xx_reg(void)
1468 omap_hwmod_am43xx_clkctrl();
1469 omap_hwmod_am43xx_rst();