2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * The data in this file should be completely autogeneratable from
13 * the TI hardware database or other technical documentation.
15 * XXX these should be marked initdata for multi-OMAP kernels
18 #include <linux/i2c-omap.h>
19 #include <linux/power/smartreflex.h>
20 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/omap-dma.h>
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/iommu-omap.h>
28 #include <plat/dmtimer.h>
33 #include "omap_hwmod.h"
34 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-34xx.h"
36 #include "cm-regbits-34xx.h"
45 * OMAP3xxx hardware module integration data
47 * All of the data in this section should be autogeneratable from the
48 * TI hardware database or other technical documentation. Data that
49 * is driver-specific or driver-kernel integration-specific belongs
58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
59 { .irq = 9 + OMAP_INTC_START, },
60 { .irq = 10 + OMAP_INTC_START, },
64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
66 .class = &l3_hwmod_class,
67 .mpu_irqs = omap3xxx_l3_main_irqs,
68 .flags = HWMOD_NO_IDLEST,
72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
74 .class = &l4_hwmod_class,
75 .flags = HWMOD_NO_IDLEST,
79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
81 .class = &l4_hwmod_class,
82 .flags = HWMOD_NO_IDLEST,
86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
88 .class = &l4_hwmod_class,
89 .flags = HWMOD_NO_IDLEST,
93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
95 .class = &l4_hwmod_class,
96 .flags = HWMOD_NO_IDLEST,
100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
101 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
107 .mpu_irqs = omap3xxx_mpu_irqs,
108 .class = &mpu_hwmod_class,
109 .main_clk = "arm_fck",
113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
114 { .name = "logic", .rst_shift = 0, .st_shift = 8 },
115 { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
116 { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
119 static struct omap_hwmod omap3xxx_iva_hwmod = {
121 .class = &iva_hwmod_class,
122 .clkdm_name = "iva2_clkdm",
123 .rst_lines = omap3xxx_iva_resets,
124 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_iva_resets),
125 .main_clk = "iva2_ck",
128 .module_offs = OMAP3430_IVA2_MOD,
130 .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
132 .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
139 * debug and emulation sub system
142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
149 .class = &omap3xxx_debugss_hwmod_class,
150 .clkdm_name = "emu_clkdm",
151 .main_clk = "emu_src_ck",
152 .flags = HWMOD_NO_IDLEST,
156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
166 .sysc_fields = &omap_hwmod_sysc_type1,
169 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
171 .sysc = &omap3xxx_timer_sysc,
174 /* secure timers dev attribute */
175 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
176 .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
179 /* always-on timers dev attribute */
180 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
181 .timer_capability = OMAP_TIMER_ALWON,
184 /* pwm timers dev attribute */
185 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
186 .timer_capability = OMAP_TIMER_HAS_PWM,
189 /* timers with DSP interrupt dev attribute */
190 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
191 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
194 /* pwm timers with DSP interrupt dev attribute */
195 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
196 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
200 static struct omap_hwmod omap3xxx_timer1_hwmod = {
202 .mpu_irqs = omap2_timer1_mpu_irqs,
203 .main_clk = "gpt1_fck",
207 .module_bit = OMAP3430_EN_GPT1_SHIFT,
208 .module_offs = WKUP_MOD,
210 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
213 .dev_attr = &capability_alwon_dev_attr,
214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
219 static struct omap_hwmod omap3xxx_timer2_hwmod = {
221 .mpu_irqs = omap2_timer2_mpu_irqs,
222 .main_clk = "gpt2_fck",
226 .module_bit = OMAP3430_EN_GPT2_SHIFT,
227 .module_offs = OMAP3430_PER_MOD,
229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
237 static struct omap_hwmod omap3xxx_timer3_hwmod = {
239 .mpu_irqs = omap2_timer3_mpu_irqs,
240 .main_clk = "gpt3_fck",
244 .module_bit = OMAP3430_EN_GPT3_SHIFT,
245 .module_offs = OMAP3430_PER_MOD,
247 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
255 static struct omap_hwmod omap3xxx_timer4_hwmod = {
257 .mpu_irqs = omap2_timer4_mpu_irqs,
258 .main_clk = "gpt4_fck",
262 .module_bit = OMAP3430_EN_GPT4_SHIFT,
263 .module_offs = OMAP3430_PER_MOD,
265 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
273 static struct omap_hwmod omap3xxx_timer5_hwmod = {
275 .mpu_irqs = omap2_timer5_mpu_irqs,
276 .main_clk = "gpt5_fck",
280 .module_bit = OMAP3430_EN_GPT5_SHIFT,
281 .module_offs = OMAP3430_PER_MOD,
283 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
286 .dev_attr = &capability_dsp_dev_attr,
287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
292 static struct omap_hwmod omap3xxx_timer6_hwmod = {
294 .mpu_irqs = omap2_timer6_mpu_irqs,
295 .main_clk = "gpt6_fck",
299 .module_bit = OMAP3430_EN_GPT6_SHIFT,
300 .module_offs = OMAP3430_PER_MOD,
302 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
305 .dev_attr = &capability_dsp_dev_attr,
306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
311 static struct omap_hwmod omap3xxx_timer7_hwmod = {
313 .mpu_irqs = omap2_timer7_mpu_irqs,
314 .main_clk = "gpt7_fck",
318 .module_bit = OMAP3430_EN_GPT7_SHIFT,
319 .module_offs = OMAP3430_PER_MOD,
321 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
324 .dev_attr = &capability_dsp_dev_attr,
325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
330 static struct omap_hwmod omap3xxx_timer8_hwmod = {
332 .mpu_irqs = omap2_timer8_mpu_irqs,
333 .main_clk = "gpt8_fck",
337 .module_bit = OMAP3430_EN_GPT8_SHIFT,
338 .module_offs = OMAP3430_PER_MOD,
340 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
343 .dev_attr = &capability_dsp_pwm_dev_attr,
344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
349 static struct omap_hwmod omap3xxx_timer9_hwmod = {
351 .mpu_irqs = omap2_timer9_mpu_irqs,
352 .main_clk = "gpt9_fck",
356 .module_bit = OMAP3430_EN_GPT9_SHIFT,
357 .module_offs = OMAP3430_PER_MOD,
359 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
362 .dev_attr = &capability_pwm_dev_attr,
363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
370 .mpu_irqs = omap2_timer10_mpu_irqs,
371 .main_clk = "gpt10_fck",
375 .module_bit = OMAP3430_EN_GPT10_SHIFT,
376 .module_offs = CORE_MOD,
378 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
381 .dev_attr = &capability_pwm_dev_attr,
382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
387 static struct omap_hwmod omap3xxx_timer11_hwmod = {
389 .mpu_irqs = omap2_timer11_mpu_irqs,
390 .main_clk = "gpt11_fck",
394 .module_bit = OMAP3430_EN_GPT11_SHIFT,
395 .module_offs = CORE_MOD,
397 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
400 .dev_attr = &capability_pwm_dev_attr,
401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
406 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
407 { .irq = 95 + OMAP_INTC_START, },
411 static struct omap_hwmod omap3xxx_timer12_hwmod = {
413 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
414 .main_clk = "gpt12_fck",
418 .module_bit = OMAP3430_EN_GPT12_SHIFT,
419 .module_offs = WKUP_MOD,
421 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
424 .dev_attr = &capability_secure_dev_attr,
425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
431 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
435 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
439 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
440 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
441 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442 SYSS_HAS_RESET_STATUS),
443 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
444 .sysc_fields = &omap_hwmod_sysc_type1,
448 static struct omap_hwmod_class_sysconfig i2c_sysc = {
452 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
453 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
454 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
455 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
456 .clockact = CLOCKACT_TEST_ICLK,
457 .sysc_fields = &omap_hwmod_sysc_type1,
460 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
462 .sysc = &omap3xxx_wd_timer_sysc,
463 .pre_shutdown = &omap2_wd_timer_disable,
464 .reset = &omap2_wd_timer_reset,
467 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
469 .class = &omap3xxx_wd_timer_hwmod_class,
470 .main_clk = "wdt2_fck",
474 .module_bit = OMAP3430_EN_WDT2_SHIFT,
475 .module_offs = WKUP_MOD,
477 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
481 * XXX: Use software supervised mode, HW supervised smartidle seems to
482 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
484 .flags = HWMOD_SWSUP_SIDLE,
488 static struct omap_hwmod omap3xxx_uart1_hwmod = {
490 .mpu_irqs = omap2_uart1_mpu_irqs,
491 .sdma_reqs = omap2_uart1_sdma_reqs,
492 .main_clk = "uart1_fck",
495 .module_offs = CORE_MOD,
497 .module_bit = OMAP3430_EN_UART1_SHIFT,
499 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
502 .class = &omap2_uart_class,
506 static struct omap_hwmod omap3xxx_uart2_hwmod = {
508 .mpu_irqs = omap2_uart2_mpu_irqs,
509 .sdma_reqs = omap2_uart2_sdma_reqs,
510 .main_clk = "uart2_fck",
513 .module_offs = CORE_MOD,
515 .module_bit = OMAP3430_EN_UART2_SHIFT,
517 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
520 .class = &omap2_uart_class,
524 static struct omap_hwmod omap3xxx_uart3_hwmod = {
526 .mpu_irqs = omap2_uart3_mpu_irqs,
527 .sdma_reqs = omap2_uart3_sdma_reqs,
528 .main_clk = "uart3_fck",
531 .module_offs = OMAP3430_PER_MOD,
533 .module_bit = OMAP3430_EN_UART3_SHIFT,
535 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
538 .class = &omap2_uart_class,
542 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
543 { .irq = 80 + OMAP_INTC_START, },
547 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
548 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
549 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
553 static struct omap_hwmod omap36xx_uart4_hwmod = {
555 .mpu_irqs = uart4_mpu_irqs,
556 .sdma_reqs = uart4_sdma_reqs,
557 .main_clk = "uart4_fck",
560 .module_offs = OMAP3430_PER_MOD,
562 .module_bit = OMAP3630_EN_UART4_SHIFT,
564 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
567 .class = &omap2_uart_class,
570 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
571 { .irq = 84 + OMAP_INTC_START, },
575 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
576 { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
577 { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
582 * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
583 * uart2_fck being enabled. So we add uart1_fck as an optional clock,
584 * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really
585 * should not be needed. The functional clock structure of the AM35xx
586 * UART4 is extremely unclear and opaque; it is unclear what the role
587 * of uart1/2_fck is for the UART4. Any clarification from either
588 * empirical testing or the AM3505/3517 hardware designers would be
591 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
592 { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
595 static struct omap_hwmod am35xx_uart4_hwmod = {
597 .mpu_irqs = am35xx_uart4_mpu_irqs,
598 .sdma_reqs = am35xx_uart4_sdma_reqs,
599 .main_clk = "uart4_fck",
602 .module_offs = CORE_MOD,
604 .module_bit = AM35XX_EN_UART4_SHIFT,
606 .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
609 .opt_clks = am35xx_uart4_opt_clks,
610 .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks),
611 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
612 .class = &omap2_uart_class,
615 static struct omap_hwmod_class i2c_class = {
618 .rev = OMAP_I2C_IP_VERSION_1,
619 .reset = &omap_i2c_reset,
622 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
623 { .name = "dispc", .dma_req = 5 },
624 { .name = "dsi1", .dma_req = 74 },
629 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
631 * The DSS HW needs all DSS clocks enabled during reset. The dss_core
632 * driver does not use these clocks.
634 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
635 { .role = "tv_clk", .clk = "dss_tv_fck" },
636 /* required only on OMAP3430 */
637 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
640 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
642 .class = &omap2_dss_hwmod_class,
643 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
644 .sdma_reqs = omap3xxx_dss_sdma_chs,
648 .module_bit = OMAP3430_EN_DSS1_SHIFT,
649 .module_offs = OMAP3430_DSS_MOD,
651 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
654 .opt_clks = dss_opt_clks,
655 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
656 .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
659 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
661 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
662 .class = &omap2_dss_hwmod_class,
663 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
664 .sdma_reqs = omap3xxx_dss_sdma_chs,
668 .module_bit = OMAP3430_EN_DSS1_SHIFT,
669 .module_offs = OMAP3430_DSS_MOD,
671 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
672 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
675 .opt_clks = dss_opt_clks,
676 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
684 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
688 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
689 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
691 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
692 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
693 .sysc_fields = &omap_hwmod_sysc_type1,
696 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
698 .sysc = &omap3_dispc_sysc,
701 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
703 .class = &omap3_dispc_hwmod_class,
704 .mpu_irqs = omap2_dispc_irqs,
705 .main_clk = "dss1_alwon_fck",
709 .module_bit = OMAP3430_EN_DSS1_SHIFT,
710 .module_offs = OMAP3430_DSS_MOD,
713 .flags = HWMOD_NO_IDLEST,
714 .dev_attr = &omap2_3_dss_dispc_dev_attr
719 * display serial interface controller
722 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
726 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
727 { .irq = 25 + OMAP_INTC_START, },
732 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
733 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
736 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
738 .class = &omap3xxx_dsi_hwmod_class,
739 .mpu_irqs = omap3xxx_dsi1_irqs,
740 .main_clk = "dss1_alwon_fck",
744 .module_bit = OMAP3430_EN_DSS1_SHIFT,
745 .module_offs = OMAP3430_DSS_MOD,
748 .opt_clks = dss_dsi1_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
750 .flags = HWMOD_NO_IDLEST,
753 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
754 { .role = "ick", .clk = "dss_ick" },
757 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
759 .class = &omap2_rfbi_hwmod_class,
760 .main_clk = "dss1_alwon_fck",
764 .module_bit = OMAP3430_EN_DSS1_SHIFT,
765 .module_offs = OMAP3430_DSS_MOD,
768 .opt_clks = dss_rfbi_opt_clks,
769 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
770 .flags = HWMOD_NO_IDLEST,
773 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
774 /* required only on OMAP3430 */
775 { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
778 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
780 .class = &omap2_venc_hwmod_class,
781 .main_clk = "dss_tv_fck",
785 .module_bit = OMAP3430_EN_DSS1_SHIFT,
786 .module_offs = OMAP3430_DSS_MOD,
789 .opt_clks = dss_venc_opt_clks,
790 .opt_clks_cnt = ARRAY_SIZE(dss_venc_opt_clks),
791 .flags = HWMOD_NO_IDLEST,
795 static struct omap_i2c_dev_attr i2c1_dev_attr = {
796 .fifo_depth = 8, /* bytes */
797 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
798 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
799 OMAP_I2C_FLAG_BUS_SHIFT_2,
802 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
804 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
805 .mpu_irqs = omap2_i2c1_mpu_irqs,
806 .sdma_reqs = omap2_i2c1_sdma_reqs,
807 .main_clk = "i2c1_fck",
810 .module_offs = CORE_MOD,
812 .module_bit = OMAP3430_EN_I2C1_SHIFT,
814 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
818 .dev_attr = &i2c1_dev_attr,
822 static struct omap_i2c_dev_attr i2c2_dev_attr = {
823 .fifo_depth = 8, /* bytes */
824 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
825 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
826 OMAP_I2C_FLAG_BUS_SHIFT_2,
829 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
831 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
832 .mpu_irqs = omap2_i2c2_mpu_irqs,
833 .sdma_reqs = omap2_i2c2_sdma_reqs,
834 .main_clk = "i2c2_fck",
837 .module_offs = CORE_MOD,
839 .module_bit = OMAP3430_EN_I2C2_SHIFT,
841 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
845 .dev_attr = &i2c2_dev_attr,
849 static struct omap_i2c_dev_attr i2c3_dev_attr = {
850 .fifo_depth = 64, /* bytes */
851 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
852 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
853 OMAP_I2C_FLAG_BUS_SHIFT_2,
856 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
857 { .irq = 61 + OMAP_INTC_START, },
861 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
862 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
863 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
867 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
869 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
870 .mpu_irqs = i2c3_mpu_irqs,
871 .sdma_reqs = i2c3_sdma_reqs,
872 .main_clk = "i2c3_fck",
875 .module_offs = CORE_MOD,
877 .module_bit = OMAP3430_EN_I2C3_SHIFT,
879 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
883 .dev_attr = &i2c3_dev_attr,
888 * general purpose io module
891 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
895 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
896 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
897 SYSS_HAS_RESET_STATUS),
898 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
899 .sysc_fields = &omap_hwmod_sysc_type1,
902 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
904 .sysc = &omap3xxx_gpio_sysc,
909 static struct omap_gpio_dev_attr gpio_dev_attr = {
915 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
916 { .role = "dbclk", .clk = "gpio1_dbck", },
919 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
921 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
922 .mpu_irqs = omap2_gpio1_irqs,
923 .main_clk = "gpio1_ick",
924 .opt_clks = gpio1_opt_clks,
925 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
929 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
930 .module_offs = WKUP_MOD,
932 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
935 .class = &omap3xxx_gpio_hwmod_class,
936 .dev_attr = &gpio_dev_attr,
940 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
941 { .role = "dbclk", .clk = "gpio2_dbck", },
944 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
946 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
947 .mpu_irqs = omap2_gpio2_irqs,
948 .main_clk = "gpio2_ick",
949 .opt_clks = gpio2_opt_clks,
950 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
954 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
955 .module_offs = OMAP3430_PER_MOD,
957 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
960 .class = &omap3xxx_gpio_hwmod_class,
961 .dev_attr = &gpio_dev_attr,
965 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
966 { .role = "dbclk", .clk = "gpio3_dbck", },
969 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
971 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
972 .mpu_irqs = omap2_gpio3_irqs,
973 .main_clk = "gpio3_ick",
974 .opt_clks = gpio3_opt_clks,
975 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
979 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
980 .module_offs = OMAP3430_PER_MOD,
982 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
985 .class = &omap3xxx_gpio_hwmod_class,
986 .dev_attr = &gpio_dev_attr,
990 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
991 { .role = "dbclk", .clk = "gpio4_dbck", },
994 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
996 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
997 .mpu_irqs = omap2_gpio4_irqs,
998 .main_clk = "gpio4_ick",
999 .opt_clks = gpio4_opt_clks,
1000 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1004 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1005 .module_offs = OMAP3430_PER_MOD,
1007 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1010 .class = &omap3xxx_gpio_hwmod_class,
1011 .dev_attr = &gpio_dev_attr,
1015 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1016 { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1020 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1021 { .role = "dbclk", .clk = "gpio5_dbck", },
1024 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1026 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1027 .mpu_irqs = omap3xxx_gpio5_irqs,
1028 .main_clk = "gpio5_ick",
1029 .opt_clks = gpio5_opt_clks,
1030 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1034 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1035 .module_offs = OMAP3430_PER_MOD,
1037 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1040 .class = &omap3xxx_gpio_hwmod_class,
1041 .dev_attr = &gpio_dev_attr,
1045 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1046 { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1050 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1051 { .role = "dbclk", .clk = "gpio6_dbck", },
1054 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1056 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1057 .mpu_irqs = omap3xxx_gpio6_irqs,
1058 .main_clk = "gpio6_ick",
1059 .opt_clks = gpio6_opt_clks,
1060 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1064 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1065 .module_offs = OMAP3430_PER_MOD,
1067 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1070 .class = &omap3xxx_gpio_hwmod_class,
1071 .dev_attr = &gpio_dev_attr,
1074 /* dma attributes */
1075 static struct omap_dma_dev_attr dma_dev_attr = {
1076 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1077 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1081 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1083 .sysc_offs = 0x002c,
1084 .syss_offs = 0x0028,
1085 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1086 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1087 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1088 SYSS_HAS_RESET_STATUS),
1089 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091 .sysc_fields = &omap_hwmod_sysc_type1,
1094 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1096 .sysc = &omap3xxx_dma_sysc,
1100 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1102 .class = &omap3xxx_dma_hwmod_class,
1103 .mpu_irqs = omap2_dma_system_irqs,
1104 .main_clk = "core_l3_ick",
1107 .module_offs = CORE_MOD,
1109 .module_bit = OMAP3430_ST_SDMA_SHIFT,
1111 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
1114 .dev_attr = &dma_dev_attr,
1115 .flags = HWMOD_NO_IDLEST,
1120 * multi channel buffered serial port controller
1123 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1124 .sysc_offs = 0x008c,
1125 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1126 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1127 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1128 .sysc_fields = &omap_hwmod_sysc_type1,
1132 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1134 .sysc = &omap3xxx_mcbsp_sysc,
1135 .rev = MCBSP_CONFIG_TYPE3,
1138 /* McBSP functional clock mapping */
1139 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1140 { .role = "pad_fck", .clk = "mcbsp_clks" },
1141 { .role = "prcm_fck", .clk = "core_96m_fck" },
1144 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1145 { .role = "pad_fck", .clk = "mcbsp_clks" },
1146 { .role = "prcm_fck", .clk = "per_96m_fck" },
1150 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1151 { .name = "common", .irq = 16 + OMAP_INTC_START, },
1152 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1153 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1157 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1159 .class = &omap3xxx_mcbsp_hwmod_class,
1160 .mpu_irqs = omap3xxx_mcbsp1_irqs,
1161 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
1162 .main_clk = "mcbsp1_fck",
1166 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1167 .module_offs = CORE_MOD,
1169 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1172 .opt_clks = mcbsp15_opt_clks,
1173 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1177 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1178 { .name = "common", .irq = 17 + OMAP_INTC_START, },
1179 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1180 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1184 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1185 .sidetone = "mcbsp2_sidetone",
1188 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1190 .class = &omap3xxx_mcbsp_hwmod_class,
1191 .mpu_irqs = omap3xxx_mcbsp2_irqs,
1192 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
1193 .main_clk = "mcbsp2_fck",
1197 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1198 .module_offs = OMAP3430_PER_MOD,
1200 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1203 .opt_clks = mcbsp234_opt_clks,
1204 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1205 .dev_attr = &omap34xx_mcbsp2_dev_attr,
1209 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1210 { .name = "common", .irq = 22 + OMAP_INTC_START, },
1211 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1212 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1216 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1217 .sidetone = "mcbsp3_sidetone",
1220 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1222 .class = &omap3xxx_mcbsp_hwmod_class,
1223 .mpu_irqs = omap3xxx_mcbsp3_irqs,
1224 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
1225 .main_clk = "mcbsp3_fck",
1229 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1230 .module_offs = OMAP3430_PER_MOD,
1232 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1235 .opt_clks = mcbsp234_opt_clks,
1236 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1237 .dev_attr = &omap34xx_mcbsp3_dev_attr,
1241 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1242 { .name = "common", .irq = 23 + OMAP_INTC_START, },
1243 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1244 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1248 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1249 { .name = "rx", .dma_req = 20 },
1250 { .name = "tx", .dma_req = 19 },
1254 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1256 .class = &omap3xxx_mcbsp_hwmod_class,
1257 .mpu_irqs = omap3xxx_mcbsp4_irqs,
1258 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
1259 .main_clk = "mcbsp4_fck",
1263 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1264 .module_offs = OMAP3430_PER_MOD,
1266 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1269 .opt_clks = mcbsp234_opt_clks,
1270 .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks),
1274 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1275 { .name = "common", .irq = 27 + OMAP_INTC_START, },
1276 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1277 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1281 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1282 { .name = "rx", .dma_req = 22 },
1283 { .name = "tx", .dma_req = 21 },
1287 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1289 .class = &omap3xxx_mcbsp_hwmod_class,
1290 .mpu_irqs = omap3xxx_mcbsp5_irqs,
1291 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
1292 .main_clk = "mcbsp5_fck",
1296 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1297 .module_offs = CORE_MOD,
1299 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1302 .opt_clks = mcbsp15_opt_clks,
1303 .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks),
1306 /* 'mcbsp sidetone' class */
1307 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1308 .sysc_offs = 0x0010,
1309 .sysc_flags = SYSC_HAS_AUTOIDLE,
1310 .sysc_fields = &omap_hwmod_sysc_type1,
1313 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1314 .name = "mcbsp_sidetone",
1315 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1318 /* mcbsp2_sidetone */
1319 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1320 { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1324 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1325 .name = "mcbsp2_sidetone",
1326 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1327 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
1328 .main_clk = "mcbsp2_fck",
1332 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1333 .module_offs = OMAP3430_PER_MOD,
1335 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1340 /* mcbsp3_sidetone */
1341 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1342 { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1346 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1347 .name = "mcbsp3_sidetone",
1348 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
1349 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
1350 .main_clk = "mcbsp3_fck",
1354 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1355 .module_offs = OMAP3430_PER_MOD,
1357 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1363 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1367 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1369 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1370 .clockact = CLOCKACT_TEST_ICLK,
1371 .sysc_fields = &omap34xx_sr_sysc_fields,
1374 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1375 .name = "smartreflex",
1376 .sysc = &omap34xx_sr_sysc,
1380 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1385 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1387 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1388 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1390 .sysc_fields = &omap36xx_sr_sysc_fields,
1393 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1394 .name = "smartreflex",
1395 .sysc = &omap36xx_sr_sysc,
1400 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1401 .sensor_voltdm_name = "mpu_iva",
1404 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1405 { .irq = 18 + OMAP_INTC_START, },
1409 static struct omap_hwmod omap34xx_sr1_hwmod = {
1410 .name = "smartreflex_mpu_iva",
1411 .class = &omap34xx_smartreflex_hwmod_class,
1412 .main_clk = "sr1_fck",
1416 .module_bit = OMAP3430_EN_SR1_SHIFT,
1417 .module_offs = WKUP_MOD,
1419 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1422 .dev_attr = &sr1_dev_attr,
1423 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1424 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1427 static struct omap_hwmod omap36xx_sr1_hwmod = {
1428 .name = "smartreflex_mpu_iva",
1429 .class = &omap36xx_smartreflex_hwmod_class,
1430 .main_clk = "sr1_fck",
1434 .module_bit = OMAP3430_EN_SR1_SHIFT,
1435 .module_offs = WKUP_MOD,
1437 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1440 .dev_attr = &sr1_dev_attr,
1441 .mpu_irqs = omap3_smartreflex_mpu_irqs,
1445 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1446 .sensor_voltdm_name = "core",
1449 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1450 { .irq = 19 + OMAP_INTC_START, },
1454 static struct omap_hwmod omap34xx_sr2_hwmod = {
1455 .name = "smartreflex_core",
1456 .class = &omap34xx_smartreflex_hwmod_class,
1457 .main_clk = "sr2_fck",
1461 .module_bit = OMAP3430_EN_SR2_SHIFT,
1462 .module_offs = WKUP_MOD,
1464 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1467 .dev_attr = &sr2_dev_attr,
1468 .mpu_irqs = omap3_smartreflex_core_irqs,
1469 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1472 static struct omap_hwmod omap36xx_sr2_hwmod = {
1473 .name = "smartreflex_core",
1474 .class = &omap36xx_smartreflex_hwmod_class,
1475 .main_clk = "sr2_fck",
1479 .module_bit = OMAP3430_EN_SR2_SHIFT,
1480 .module_offs = WKUP_MOD,
1482 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1485 .dev_attr = &sr2_dev_attr,
1486 .mpu_irqs = omap3_smartreflex_core_irqs,
1491 * mailbox module allowing communication between the on-chip processors
1492 * using a queued mailbox-interrupt mechanism.
1495 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1499 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1500 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1501 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1502 .sysc_fields = &omap_hwmod_sysc_type1,
1505 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1507 .sysc = &omap3xxx_mailbox_sysc,
1510 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1511 { .irq = 26 + OMAP_INTC_START, },
1515 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1517 .class = &omap3xxx_mailbox_hwmod_class,
1518 .mpu_irqs = omap3xxx_mailbox_irqs,
1519 .main_clk = "mailboxes_ick",
1523 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1524 .module_offs = CORE_MOD,
1526 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1533 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1537 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1539 .sysc_offs = 0x0010,
1540 .syss_offs = 0x0014,
1541 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1542 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1543 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1545 .sysc_fields = &omap_hwmod_sysc_type1,
1548 static struct omap_hwmod_class omap34xx_mcspi_class = {
1550 .sysc = &omap34xx_mcspi_sysc,
1551 .rev = OMAP3_MCSPI_REV,
1555 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1556 .num_chipselect = 4,
1559 static struct omap_hwmod omap34xx_mcspi1 = {
1561 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1562 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1563 .main_clk = "mcspi1_fck",
1566 .module_offs = CORE_MOD,
1568 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1570 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1573 .class = &omap34xx_mcspi_class,
1574 .dev_attr = &omap_mcspi1_dev_attr,
1578 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1579 .num_chipselect = 2,
1582 static struct omap_hwmod omap34xx_mcspi2 = {
1584 .mpu_irqs = omap2_mcspi2_mpu_irqs,
1585 .sdma_reqs = omap2_mcspi2_sdma_reqs,
1586 .main_clk = "mcspi2_fck",
1589 .module_offs = CORE_MOD,
1591 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1593 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1596 .class = &omap34xx_mcspi_class,
1597 .dev_attr = &omap_mcspi2_dev_attr,
1601 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1602 { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1606 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1607 { .name = "tx0", .dma_req = 15 },
1608 { .name = "rx0", .dma_req = 16 },
1609 { .name = "tx1", .dma_req = 23 },
1610 { .name = "rx1", .dma_req = 24 },
1614 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1615 .num_chipselect = 2,
1618 static struct omap_hwmod omap34xx_mcspi3 = {
1620 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
1621 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
1622 .main_clk = "mcspi3_fck",
1625 .module_offs = CORE_MOD,
1627 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1629 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1632 .class = &omap34xx_mcspi_class,
1633 .dev_attr = &omap_mcspi3_dev_attr,
1637 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1638 { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1642 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1643 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1644 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1648 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1649 .num_chipselect = 1,
1652 static struct omap_hwmod omap34xx_mcspi4 = {
1654 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
1655 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
1656 .main_clk = "mcspi4_fck",
1659 .module_offs = CORE_MOD,
1661 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1663 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1666 .class = &omap34xx_mcspi_class,
1667 .dev_attr = &omap_mcspi4_dev_attr,
1671 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1673 .sysc_offs = 0x0404,
1674 .syss_offs = 0x0408,
1675 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1676 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1678 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1679 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1680 .sysc_fields = &omap_hwmod_sysc_type1,
1683 static struct omap_hwmod_class usbotg_class = {
1685 .sysc = &omap3xxx_usbhsotg_sysc,
1689 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1691 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1692 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1696 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1697 .name = "usb_otg_hs",
1698 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
1699 .main_clk = "hsotgusb_ick",
1703 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1704 .module_offs = CORE_MOD,
1706 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1707 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1710 .class = &usbotg_class,
1713 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
1714 * broken when autoidle is enabled
1715 * workaround is to disable the autoidle bit at module level.
1717 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1718 | HWMOD_SWSUP_MSTANDBY,
1722 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1723 { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1727 static struct omap_hwmod_class am35xx_usbotg_class = {
1728 .name = "am35xx_usbotg",
1731 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1732 .name = "am35x_otg_hs",
1733 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
1734 .main_clk = "hsotgusb_fck",
1735 .class = &am35xx_usbotg_class,
1736 .flags = HWMOD_NO_IDLEST,
1739 /* MMC/SD/SDIO common */
1740 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1744 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1745 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1746 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1747 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1748 .sysc_fields = &omap_hwmod_sysc_type1,
1751 static struct omap_hwmod_class omap34xx_mmc_class = {
1753 .sysc = &omap34xx_mmc_sysc,
1758 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1759 { .irq = 83 + OMAP_INTC_START, },
1763 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1764 { .name = "tx", .dma_req = 61, },
1765 { .name = "rx", .dma_req = 62, },
1769 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1770 { .role = "dbck", .clk = "omap_32k_fck", },
1773 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1774 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1777 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1778 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1779 .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1780 OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1783 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1785 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1786 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1787 .opt_clks = omap34xx_mmc1_opt_clks,
1788 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1789 .main_clk = "mmchs1_fck",
1792 .module_offs = CORE_MOD,
1794 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1796 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1799 .dev_attr = &mmc1_pre_es3_dev_attr,
1800 .class = &omap34xx_mmc_class,
1803 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1805 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
1806 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
1807 .opt_clks = omap34xx_mmc1_opt_clks,
1808 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1809 .main_clk = "mmchs1_fck",
1812 .module_offs = CORE_MOD,
1814 .module_bit = OMAP3430_EN_MMC1_SHIFT,
1816 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1819 .dev_attr = &mmc1_dev_attr,
1820 .class = &omap34xx_mmc_class,
1825 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1826 { .irq = 86 + OMAP_INTC_START, },
1830 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1831 { .name = "tx", .dma_req = 47, },
1832 { .name = "rx", .dma_req = 48, },
1836 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1837 { .role = "dbck", .clk = "omap_32k_fck", },
1840 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1841 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1842 .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1845 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1847 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1848 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1849 .opt_clks = omap34xx_mmc2_opt_clks,
1850 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1851 .main_clk = "mmchs2_fck",
1854 .module_offs = CORE_MOD,
1856 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1858 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1861 .dev_attr = &mmc2_pre_es3_dev_attr,
1862 .class = &omap34xx_mmc_class,
1865 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1867 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
1868 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
1869 .opt_clks = omap34xx_mmc2_opt_clks,
1870 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1871 .main_clk = "mmchs2_fck",
1874 .module_offs = CORE_MOD,
1876 .module_bit = OMAP3430_EN_MMC2_SHIFT,
1878 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1881 .class = &omap34xx_mmc_class,
1886 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1887 { .irq = 94 + OMAP_INTC_START, },
1891 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1892 { .name = "tx", .dma_req = 77, },
1893 { .name = "rx", .dma_req = 78, },
1897 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1898 { .role = "dbck", .clk = "omap_32k_fck", },
1901 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1903 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
1904 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
1905 .opt_clks = omap34xx_mmc3_opt_clks,
1906 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1907 .main_clk = "mmchs3_fck",
1911 .module_bit = OMAP3430_EN_MMC3_SHIFT,
1913 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1916 .class = &omap34xx_mmc_class,
1920 * 'usb_host_hs' class
1921 * high-speed multi-port usb host controller
1924 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1926 .sysc_offs = 0x0010,
1927 .syss_offs = 0x0014,
1928 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1929 SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1930 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1931 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1932 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1933 .sysc_fields = &omap_hwmod_sysc_type1,
1936 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1937 .name = "usb_host_hs",
1938 .sysc = &omap3xxx_usb_host_hs_sysc,
1941 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1942 { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1945 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1946 { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1947 { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1951 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1952 .name = "usb_host_hs",
1953 .class = &omap3xxx_usb_host_hs_hwmod_class,
1954 .clkdm_name = "l3_init_clkdm",
1955 .mpu_irqs = omap3xxx_usb_host_hs_irqs,
1956 .main_clk = "usbhost_48m_fck",
1959 .module_offs = OMAP3430ES2_USBHOST_MOD,
1961 .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1963 .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1964 .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1967 .opt_clks = omap3xxx_usb_host_hs_opt_clks,
1968 .opt_clks_cnt = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1971 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1975 * In the following configuration :
1976 * - USBHOST module is set to smart-idle mode
1977 * - PRCM asserts idle_req to the USBHOST module ( This typically
1978 * happens when the system is going to a low power mode : all ports
1979 * have been suspended, the master part of the USBHOST module has
1980 * entered the standby state, and SW has cut the functional clocks)
1981 * - an USBHOST interrupt occurs before the module is able to answer
1982 * idle_ack, typically a remote wakeup IRQ.
1983 * Then the USB HOST module will enter a deadlock situation where it
1984 * is no more accessible nor functional.
1987 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1991 * Errata: USB host EHCI may stall when entering smart-standby mode
1995 * When the USBHOST module is set to smart-standby mode, and when it is
1996 * ready to enter the standby state (i.e. all ports are suspended and
1997 * all attached devices are in suspend mode), then it can wrongly assert
1998 * the Mstandby signal too early while there are still some residual OCP
1999 * transactions ongoing. If this condition occurs, the internal state
2000 * machine may go to an undefined state and the USB link may be stuck
2001 * upon the next resume.
2004 * Don't use smart standby; use only force standby,
2005 * hence HWMOD_SWSUP_MSTANDBY
2009 * During system boot; If the hwmod framework resets the module
2010 * the module will have smart idle settings; which can lead to deadlock
2011 * (above Errata Id:i660); so, dont reset the module during boot;
2012 * Use HWMOD_INIT_NO_RESET.
2015 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2016 HWMOD_INIT_NO_RESET,
2020 * 'usb_tll_hs' class
2021 * usb_tll_hs module is the adapter on the usb_host_hs ports
2023 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2025 .sysc_offs = 0x0010,
2026 .syss_offs = 0x0014,
2027 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2028 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2030 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2031 .sysc_fields = &omap_hwmod_sysc_type1,
2034 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2035 .name = "usb_tll_hs",
2036 .sysc = &omap3xxx_usb_tll_hs_sysc,
2039 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2040 { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2044 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2045 .name = "usb_tll_hs",
2046 .class = &omap3xxx_usb_tll_hs_hwmod_class,
2047 .clkdm_name = "l3_init_clkdm",
2048 .mpu_irqs = omap3xxx_usb_tll_hs_irqs,
2049 .main_clk = "usbtll_fck",
2052 .module_offs = CORE_MOD,
2054 .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2056 .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2061 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2063 .mpu_irqs = omap2_hdq1w_mpu_irqs,
2064 .main_clk = "hdq_fck",
2067 .module_offs = CORE_MOD,
2069 .module_bit = OMAP3430_EN_HDQ_SHIFT,
2071 .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2074 .class = &omap2_hdq1w_class,
2078 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2079 { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2080 { .name = "rst_modem_sw", .rst_shift = 1 },
2083 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2087 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2089 .rst_lines = omap3xxx_sad2d_resets,
2090 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_sad2d_resets),
2091 .main_clk = "sad2d_ick",
2094 .module_offs = CORE_MOD,
2096 .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2098 .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2101 .class = &omap3xxx_sad2d_class,
2105 * '32K sync counter' class
2106 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2108 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2110 .sysc_offs = 0x0004,
2111 .sysc_flags = SYSC_HAS_SIDLEMODE,
2112 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
2113 .sysc_fields = &omap_hwmod_sysc_type1,
2116 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2118 .sysc = &omap3xxx_counter_sysc,
2121 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2122 .name = "counter_32k",
2123 .class = &omap3xxx_counter_hwmod_class,
2124 .clkdm_name = "wkup_clkdm",
2125 .flags = HWMOD_SWSUP_SIDLE,
2126 .main_clk = "wkup_32k_fck",
2129 .module_offs = WKUP_MOD,
2131 .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2133 .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2140 * general purpose memory controller
2143 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2145 .sysc_offs = 0x0010,
2146 .syss_offs = 0x0014,
2147 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2148 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2149 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2150 .sysc_fields = &omap_hwmod_sysc_type1,
2153 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2155 .sysc = &omap3xxx_gpmc_sysc,
2158 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2163 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2165 .class = &omap3xxx_gpmc_hwmod_class,
2166 .clkdm_name = "core_l3_clkdm",
2167 .mpu_irqs = omap3xxx_gpmc_irqs,
2168 .main_clk = "gpmc_fck",
2170 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2171 * block. It is not being added due to any known bugs with
2172 * resetting the GPMC IP block, but rather because any timings
2173 * set by the bootloader are not being correctly programmed by
2174 * the kernel from the board file or DT data.
2175 * HWMOD_INIT_NO_RESET should be removed ASAP.
2177 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2185 /* L3 -> L4_CORE interface */
2186 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2187 .master = &omap3xxx_l3_main_hwmod,
2188 .slave = &omap3xxx_l4_core_hwmod,
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2192 /* L3 -> L4_PER interface */
2193 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2194 .master = &omap3xxx_l3_main_hwmod,
2195 .slave = &omap3xxx_l4_per_hwmod,
2196 .user = OCP_USER_MPU | OCP_USER_SDMA,
2199 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2201 .pa_start = 0x68000000,
2202 .pa_end = 0x6800ffff,
2203 .flags = ADDR_TYPE_RT,
2208 /* MPU -> L3 interface */
2209 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2210 .master = &omap3xxx_mpu_hwmod,
2211 .slave = &omap3xxx_l3_main_hwmod,
2212 .addr = omap3xxx_l3_main_addrs,
2213 .user = OCP_USER_MPU,
2216 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2218 .pa_start = 0x54000000,
2219 .pa_end = 0x547fffff,
2220 .flags = ADDR_TYPE_RT,
2226 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2227 .master = &omap3xxx_l3_main_hwmod,
2228 .slave = &omap3xxx_debugss_hwmod,
2229 .addr = omap3xxx_l4_emu_addrs,
2230 .user = OCP_USER_MPU,
2234 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2235 .master = &omap3430es1_dss_core_hwmod,
2236 .slave = &omap3xxx_l3_main_hwmod,
2237 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2241 .master = &omap3xxx_dss_core_hwmod,
2242 .slave = &omap3xxx_l3_main_hwmod,
2245 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2246 .flags = OMAP_FIREWALL_L3,
2249 .user = OCP_USER_MPU | OCP_USER_SDMA,
2252 /* l3_core -> usbhsotg interface */
2253 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2254 .master = &omap3xxx_usbhsotg_hwmod,
2255 .slave = &omap3xxx_l3_main_hwmod,
2256 .clk = "core_l3_ick",
2257 .user = OCP_USER_MPU,
2260 /* l3_core -> am35xx_usbhsotg interface */
2261 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2262 .master = &am35xx_usbhsotg_hwmod,
2263 .slave = &omap3xxx_l3_main_hwmod,
2264 .clk = "hsotgusb_ick",
2265 .user = OCP_USER_MPU,
2268 /* l3_core -> sad2d interface */
2269 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2270 .master = &omap3xxx_sad2d_hwmod,
2271 .slave = &omap3xxx_l3_main_hwmod,
2272 .clk = "core_l3_ick",
2273 .user = OCP_USER_MPU,
2276 /* L4_CORE -> L4_WKUP interface */
2277 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2278 .master = &omap3xxx_l4_core_hwmod,
2279 .slave = &omap3xxx_l4_wkup_hwmod,
2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2283 /* L4 CORE -> MMC1 interface */
2284 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2285 .master = &omap3xxx_l4_core_hwmod,
2286 .slave = &omap3xxx_pre_es3_mmc1_hwmod,
2287 .clk = "mmchs1_ick",
2288 .addr = omap2430_mmc1_addr_space,
2289 .user = OCP_USER_MPU | OCP_USER_SDMA,
2290 .flags = OMAP_FIREWALL_L4
2293 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2294 .master = &omap3xxx_l4_core_hwmod,
2295 .slave = &omap3xxx_es3plus_mmc1_hwmod,
2296 .clk = "mmchs1_ick",
2297 .addr = omap2430_mmc1_addr_space,
2298 .user = OCP_USER_MPU | OCP_USER_SDMA,
2299 .flags = OMAP_FIREWALL_L4
2302 /* L4 CORE -> MMC2 interface */
2303 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2304 .master = &omap3xxx_l4_core_hwmod,
2305 .slave = &omap3xxx_pre_es3_mmc2_hwmod,
2306 .clk = "mmchs2_ick",
2307 .addr = omap2430_mmc2_addr_space,
2308 .user = OCP_USER_MPU | OCP_USER_SDMA,
2309 .flags = OMAP_FIREWALL_L4
2312 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2313 .master = &omap3xxx_l4_core_hwmod,
2314 .slave = &omap3xxx_es3plus_mmc2_hwmod,
2315 .clk = "mmchs2_ick",
2316 .addr = omap2430_mmc2_addr_space,
2317 .user = OCP_USER_MPU | OCP_USER_SDMA,
2318 .flags = OMAP_FIREWALL_L4
2321 /* L4 CORE -> MMC3 interface */
2322 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2324 .pa_start = 0x480ad000,
2325 .pa_end = 0x480ad1ff,
2326 .flags = ADDR_TYPE_RT,
2331 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2332 .master = &omap3xxx_l4_core_hwmod,
2333 .slave = &omap3xxx_mmc3_hwmod,
2334 .clk = "mmchs3_ick",
2335 .addr = omap3xxx_mmc3_addr_space,
2336 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337 .flags = OMAP_FIREWALL_L4
2340 /* L4 CORE -> UART1 interface */
2341 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2343 .pa_start = OMAP3_UART1_BASE,
2344 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
2345 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2350 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2351 .master = &omap3xxx_l4_core_hwmod,
2352 .slave = &omap3xxx_uart1_hwmod,
2354 .addr = omap3xxx_uart1_addr_space,
2355 .user = OCP_USER_MPU | OCP_USER_SDMA,
2358 /* L4 CORE -> UART2 interface */
2359 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2361 .pa_start = OMAP3_UART2_BASE,
2362 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
2363 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2368 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2369 .master = &omap3xxx_l4_core_hwmod,
2370 .slave = &omap3xxx_uart2_hwmod,
2372 .addr = omap3xxx_uart2_addr_space,
2373 .user = OCP_USER_MPU | OCP_USER_SDMA,
2376 /* L4 PER -> UART3 interface */
2377 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2379 .pa_start = OMAP3_UART3_BASE,
2380 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
2381 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2386 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2387 .master = &omap3xxx_l4_per_hwmod,
2388 .slave = &omap3xxx_uart3_hwmod,
2390 .addr = omap3xxx_uart3_addr_space,
2391 .user = OCP_USER_MPU | OCP_USER_SDMA,
2394 /* L4 PER -> UART4 interface */
2395 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2397 .pa_start = OMAP3_UART4_BASE,
2398 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
2399 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2404 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2405 .master = &omap3xxx_l4_per_hwmod,
2406 .slave = &omap36xx_uart4_hwmod,
2408 .addr = omap36xx_uart4_addr_space,
2409 .user = OCP_USER_MPU | OCP_USER_SDMA,
2412 /* AM35xx: L4 CORE -> UART4 interface */
2413 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2415 .pa_start = OMAP3_UART4_AM35XX_BASE,
2416 .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2417 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2422 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2423 .master = &omap3xxx_l4_core_hwmod,
2424 .slave = &am35xx_uart4_hwmod,
2426 .addr = am35xx_uart4_addr_space,
2427 .user = OCP_USER_MPU | OCP_USER_SDMA,
2430 /* L4 CORE -> I2C1 interface */
2431 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2432 .master = &omap3xxx_l4_core_hwmod,
2433 .slave = &omap3xxx_i2c1_hwmod,
2435 .addr = omap2_i2c1_addr_space,
2438 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
2440 .flags = OMAP_FIREWALL_L4,
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2446 /* L4 CORE -> I2C2 interface */
2447 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2448 .master = &omap3xxx_l4_core_hwmod,
2449 .slave = &omap3xxx_i2c2_hwmod,
2451 .addr = omap2_i2c2_addr_space,
2454 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
2456 .flags = OMAP_FIREWALL_L4,
2459 .user = OCP_USER_MPU | OCP_USER_SDMA,
2462 /* L4 CORE -> I2C3 interface */
2463 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2465 .pa_start = 0x48060000,
2466 .pa_end = 0x48060000 + SZ_128 - 1,
2467 .flags = ADDR_TYPE_RT,
2472 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2473 .master = &omap3xxx_l4_core_hwmod,
2474 .slave = &omap3xxx_i2c3_hwmod,
2476 .addr = omap3xxx_i2c3_addr_space,
2479 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
2481 .flags = OMAP_FIREWALL_L4,
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2487 /* L4 CORE -> SR1 interface */
2488 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2490 .pa_start = OMAP34XX_SR1_BASE,
2491 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
2492 .flags = ADDR_TYPE_RT,
2497 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2498 .master = &omap3xxx_l4_core_hwmod,
2499 .slave = &omap34xx_sr1_hwmod,
2501 .addr = omap3_sr1_addr_space,
2502 .user = OCP_USER_MPU,
2505 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2506 .master = &omap3xxx_l4_core_hwmod,
2507 .slave = &omap36xx_sr1_hwmod,
2509 .addr = omap3_sr1_addr_space,
2510 .user = OCP_USER_MPU,
2513 /* L4 CORE -> SR1 interface */
2514 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2516 .pa_start = OMAP34XX_SR2_BASE,
2517 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
2518 .flags = ADDR_TYPE_RT,
2523 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2524 .master = &omap3xxx_l4_core_hwmod,
2525 .slave = &omap34xx_sr2_hwmod,
2527 .addr = omap3_sr2_addr_space,
2528 .user = OCP_USER_MPU,
2531 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2532 .master = &omap3xxx_l4_core_hwmod,
2533 .slave = &omap36xx_sr2_hwmod,
2535 .addr = omap3_sr2_addr_space,
2536 .user = OCP_USER_MPU,
2539 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2541 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
2542 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2543 .flags = ADDR_TYPE_RT
2548 /* l4_core -> usbhsotg */
2549 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2550 .master = &omap3xxx_l4_core_hwmod,
2551 .slave = &omap3xxx_usbhsotg_hwmod,
2553 .addr = omap3xxx_usbhsotg_addrs,
2554 .user = OCP_USER_MPU,
2557 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2559 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
2560 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2561 .flags = ADDR_TYPE_RT
2566 /* l4_core -> usbhsotg */
2567 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2568 .master = &omap3xxx_l4_core_hwmod,
2569 .slave = &am35xx_usbhsotg_hwmod,
2570 .clk = "hsotgusb_ick",
2571 .addr = am35xx_usbhsotg_addrs,
2572 .user = OCP_USER_MPU,
2575 /* L4_WKUP -> L4_SEC interface */
2576 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2577 .master = &omap3xxx_l4_wkup_hwmod,
2578 .slave = &omap3xxx_l4_sec_hwmod,
2579 .user = OCP_USER_MPU | OCP_USER_SDMA,
2582 /* IVA2 <- L3 interface */
2583 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2584 .master = &omap3xxx_l3_main_hwmod,
2585 .slave = &omap3xxx_iva_hwmod,
2586 .clk = "core_l3_ick",
2587 .user = OCP_USER_MPU | OCP_USER_SDMA,
2590 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2592 .pa_start = 0x48318000,
2593 .pa_end = 0x48318000 + SZ_1K - 1,
2594 .flags = ADDR_TYPE_RT
2599 /* l4_wkup -> timer1 */
2600 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2601 .master = &omap3xxx_l4_wkup_hwmod,
2602 .slave = &omap3xxx_timer1_hwmod,
2604 .addr = omap3xxx_timer1_addrs,
2605 .user = OCP_USER_MPU | OCP_USER_SDMA,
2608 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2610 .pa_start = 0x49032000,
2611 .pa_end = 0x49032000 + SZ_1K - 1,
2612 .flags = ADDR_TYPE_RT
2617 /* l4_per -> timer2 */
2618 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2619 .master = &omap3xxx_l4_per_hwmod,
2620 .slave = &omap3xxx_timer2_hwmod,
2622 .addr = omap3xxx_timer2_addrs,
2623 .user = OCP_USER_MPU | OCP_USER_SDMA,
2626 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2628 .pa_start = 0x49034000,
2629 .pa_end = 0x49034000 + SZ_1K - 1,
2630 .flags = ADDR_TYPE_RT
2635 /* l4_per -> timer3 */
2636 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2637 .master = &omap3xxx_l4_per_hwmod,
2638 .slave = &omap3xxx_timer3_hwmod,
2640 .addr = omap3xxx_timer3_addrs,
2641 .user = OCP_USER_MPU | OCP_USER_SDMA,
2644 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2646 .pa_start = 0x49036000,
2647 .pa_end = 0x49036000 + SZ_1K - 1,
2648 .flags = ADDR_TYPE_RT
2653 /* l4_per -> timer4 */
2654 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2655 .master = &omap3xxx_l4_per_hwmod,
2656 .slave = &omap3xxx_timer4_hwmod,
2658 .addr = omap3xxx_timer4_addrs,
2659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2662 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2664 .pa_start = 0x49038000,
2665 .pa_end = 0x49038000 + SZ_1K - 1,
2666 .flags = ADDR_TYPE_RT
2671 /* l4_per -> timer5 */
2672 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2673 .master = &omap3xxx_l4_per_hwmod,
2674 .slave = &omap3xxx_timer5_hwmod,
2676 .addr = omap3xxx_timer5_addrs,
2677 .user = OCP_USER_MPU | OCP_USER_SDMA,
2680 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2682 .pa_start = 0x4903A000,
2683 .pa_end = 0x4903A000 + SZ_1K - 1,
2684 .flags = ADDR_TYPE_RT
2689 /* l4_per -> timer6 */
2690 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2691 .master = &omap3xxx_l4_per_hwmod,
2692 .slave = &omap3xxx_timer6_hwmod,
2694 .addr = omap3xxx_timer6_addrs,
2695 .user = OCP_USER_MPU | OCP_USER_SDMA,
2698 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2700 .pa_start = 0x4903C000,
2701 .pa_end = 0x4903C000 + SZ_1K - 1,
2702 .flags = ADDR_TYPE_RT
2707 /* l4_per -> timer7 */
2708 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2709 .master = &omap3xxx_l4_per_hwmod,
2710 .slave = &omap3xxx_timer7_hwmod,
2712 .addr = omap3xxx_timer7_addrs,
2713 .user = OCP_USER_MPU | OCP_USER_SDMA,
2716 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2718 .pa_start = 0x4903E000,
2719 .pa_end = 0x4903E000 + SZ_1K - 1,
2720 .flags = ADDR_TYPE_RT
2725 /* l4_per -> timer8 */
2726 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2727 .master = &omap3xxx_l4_per_hwmod,
2728 .slave = &omap3xxx_timer8_hwmod,
2730 .addr = omap3xxx_timer8_addrs,
2731 .user = OCP_USER_MPU | OCP_USER_SDMA,
2734 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2736 .pa_start = 0x49040000,
2737 .pa_end = 0x49040000 + SZ_1K - 1,
2738 .flags = ADDR_TYPE_RT
2743 /* l4_per -> timer9 */
2744 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2745 .master = &omap3xxx_l4_per_hwmod,
2746 .slave = &omap3xxx_timer9_hwmod,
2748 .addr = omap3xxx_timer9_addrs,
2749 .user = OCP_USER_MPU | OCP_USER_SDMA,
2752 /* l4_core -> timer10 */
2753 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2754 .master = &omap3xxx_l4_core_hwmod,
2755 .slave = &omap3xxx_timer10_hwmod,
2757 .addr = omap2_timer10_addrs,
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2761 /* l4_core -> timer11 */
2762 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2763 .master = &omap3xxx_l4_core_hwmod,
2764 .slave = &omap3xxx_timer11_hwmod,
2766 .addr = omap2_timer11_addrs,
2767 .user = OCP_USER_MPU | OCP_USER_SDMA,
2770 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2772 .pa_start = 0x48304000,
2773 .pa_end = 0x48304000 + SZ_1K - 1,
2774 .flags = ADDR_TYPE_RT
2779 /* l4_core -> timer12 */
2780 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2781 .master = &omap3xxx_l4_sec_hwmod,
2782 .slave = &omap3xxx_timer12_hwmod,
2784 .addr = omap3xxx_timer12_addrs,
2785 .user = OCP_USER_MPU | OCP_USER_SDMA,
2788 /* l4_wkup -> wd_timer2 */
2789 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2791 .pa_start = 0x48314000,
2792 .pa_end = 0x4831407f,
2793 .flags = ADDR_TYPE_RT
2798 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2799 .master = &omap3xxx_l4_wkup_hwmod,
2800 .slave = &omap3xxx_wd_timer2_hwmod,
2802 .addr = omap3xxx_wd_timer2_addrs,
2803 .user = OCP_USER_MPU | OCP_USER_SDMA,
2806 /* l4_core -> dss */
2807 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2808 .master = &omap3xxx_l4_core_hwmod,
2809 .slave = &omap3430es1_dss_core_hwmod,
2811 .addr = omap2_dss_addrs,
2814 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2815 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2816 .flags = OMAP_FIREWALL_L4,
2819 .user = OCP_USER_MPU | OCP_USER_SDMA,
2822 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2823 .master = &omap3xxx_l4_core_hwmod,
2824 .slave = &omap3xxx_dss_core_hwmod,
2826 .addr = omap2_dss_addrs,
2829 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2830 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2831 .flags = OMAP_FIREWALL_L4,
2834 .user = OCP_USER_MPU | OCP_USER_SDMA,
2837 /* l4_core -> dss_dispc */
2838 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2839 .master = &omap3xxx_l4_core_hwmod,
2840 .slave = &omap3xxx_dss_dispc_hwmod,
2842 .addr = omap2_dss_dispc_addrs,
2845 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2846 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2847 .flags = OMAP_FIREWALL_L4,
2850 .user = OCP_USER_MPU | OCP_USER_SDMA,
2853 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2855 .pa_start = 0x4804FC00,
2856 .pa_end = 0x4804FFFF,
2857 .flags = ADDR_TYPE_RT
2862 /* l4_core -> dss_dsi1 */
2863 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2864 .master = &omap3xxx_l4_core_hwmod,
2865 .slave = &omap3xxx_dss_dsi1_hwmod,
2867 .addr = omap3xxx_dss_dsi1_addrs,
2870 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2871 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2872 .flags = OMAP_FIREWALL_L4,
2875 .user = OCP_USER_MPU | OCP_USER_SDMA,
2878 /* l4_core -> dss_rfbi */
2879 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2880 .master = &omap3xxx_l4_core_hwmod,
2881 .slave = &omap3xxx_dss_rfbi_hwmod,
2883 .addr = omap2_dss_rfbi_addrs,
2886 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2887 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2888 .flags = OMAP_FIREWALL_L4,
2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894 /* l4_core -> dss_venc */
2895 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2896 .master = &omap3xxx_l4_core_hwmod,
2897 .slave = &omap3xxx_dss_venc_hwmod,
2899 .addr = omap2_dss_venc_addrs,
2902 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2903 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2904 .flags = OMAP_FIREWALL_L4,
2907 .flags = OCPIF_SWSUP_IDLE,
2908 .user = OCP_USER_MPU | OCP_USER_SDMA,
2911 /* l4_wkup -> gpio1 */
2912 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2914 .pa_start = 0x48310000,
2915 .pa_end = 0x483101ff,
2916 .flags = ADDR_TYPE_RT
2921 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2922 .master = &omap3xxx_l4_wkup_hwmod,
2923 .slave = &omap3xxx_gpio1_hwmod,
2924 .addr = omap3xxx_gpio1_addrs,
2925 .user = OCP_USER_MPU | OCP_USER_SDMA,
2928 /* l4_per -> gpio2 */
2929 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2931 .pa_start = 0x49050000,
2932 .pa_end = 0x490501ff,
2933 .flags = ADDR_TYPE_RT
2938 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2939 .master = &omap3xxx_l4_per_hwmod,
2940 .slave = &omap3xxx_gpio2_hwmod,
2941 .addr = omap3xxx_gpio2_addrs,
2942 .user = OCP_USER_MPU | OCP_USER_SDMA,
2945 /* l4_per -> gpio3 */
2946 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2948 .pa_start = 0x49052000,
2949 .pa_end = 0x490521ff,
2950 .flags = ADDR_TYPE_RT
2955 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2956 .master = &omap3xxx_l4_per_hwmod,
2957 .slave = &omap3xxx_gpio3_hwmod,
2958 .addr = omap3xxx_gpio3_addrs,
2959 .user = OCP_USER_MPU | OCP_USER_SDMA,
2964 * The memory management unit performs virtual to physical address translation
2965 * for its requestors.
2968 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2972 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2973 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2974 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2975 .sysc_fields = &omap_hwmod_sysc_type1,
2978 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2985 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2987 .da_end = 0xfffff000,
2988 .nr_tlb_entries = 8,
2991 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2992 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2997 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2999 .pa_start = 0x480bd400,
3000 .pa_end = 0x480bd47f,
3001 .flags = ADDR_TYPE_RT,
3006 /* l4_core -> mmu isp */
3007 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3008 .master = &omap3xxx_l4_core_hwmod,
3009 .slave = &omap3xxx_mmu_isp_hwmod,
3010 .addr = omap3xxx_mmu_isp_addrs,
3011 .user = OCP_USER_MPU | OCP_USER_SDMA,
3014 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3016 .class = &omap3xxx_mmu_hwmod_class,
3017 .mpu_irqs = omap3xxx_mmu_isp_irqs,
3018 .main_clk = "cam_ick",
3019 .dev_attr = &mmu_isp_dev_attr,
3020 .flags = HWMOD_NO_IDLEST,
3023 #ifdef CONFIG_OMAP_IOMMU_IVA2
3027 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3028 .da_start = 0x11000000,
3029 .da_end = 0xfffff000,
3030 .nr_tlb_entries = 32,
3033 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3034 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3039 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3040 { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3043 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3045 .pa_start = 0x5d000000,
3046 .pa_end = 0x5d00007f,
3047 .flags = ADDR_TYPE_RT,
3052 /* l3_main -> iva mmu */
3053 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3054 .master = &omap3xxx_l3_main_hwmod,
3055 .slave = &omap3xxx_mmu_iva_hwmod,
3056 .addr = omap3xxx_mmu_iva_addrs,
3057 .user = OCP_USER_MPU | OCP_USER_SDMA,
3060 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3062 .class = &omap3xxx_mmu_hwmod_class,
3063 .mpu_irqs = omap3xxx_mmu_iva_irqs,
3064 .rst_lines = omap3xxx_mmu_iva_resets,
3065 .rst_lines_cnt = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3066 .main_clk = "iva2_ck",
3069 .module_offs = OMAP3430_IVA2_MOD,
3072 .dev_attr = &mmu_iva_dev_attr,
3073 .flags = HWMOD_NO_IDLEST,
3078 /* l4_per -> gpio4 */
3079 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3081 .pa_start = 0x49054000,
3082 .pa_end = 0x490541ff,
3083 .flags = ADDR_TYPE_RT
3088 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3089 .master = &omap3xxx_l4_per_hwmod,
3090 .slave = &omap3xxx_gpio4_hwmod,
3091 .addr = omap3xxx_gpio4_addrs,
3092 .user = OCP_USER_MPU | OCP_USER_SDMA,
3095 /* l4_per -> gpio5 */
3096 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3098 .pa_start = 0x49056000,
3099 .pa_end = 0x490561ff,
3100 .flags = ADDR_TYPE_RT
3105 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3106 .master = &omap3xxx_l4_per_hwmod,
3107 .slave = &omap3xxx_gpio5_hwmod,
3108 .addr = omap3xxx_gpio5_addrs,
3109 .user = OCP_USER_MPU | OCP_USER_SDMA,
3112 /* l4_per -> gpio6 */
3113 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3115 .pa_start = 0x49058000,
3116 .pa_end = 0x490581ff,
3117 .flags = ADDR_TYPE_RT
3122 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3123 .master = &omap3xxx_l4_per_hwmod,
3124 .slave = &omap3xxx_gpio6_hwmod,
3125 .addr = omap3xxx_gpio6_addrs,
3126 .user = OCP_USER_MPU | OCP_USER_SDMA,
3129 /* dma_system -> L3 */
3130 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3131 .master = &omap3xxx_dma_system_hwmod,
3132 .slave = &omap3xxx_l3_main_hwmod,
3133 .clk = "core_l3_ick",
3134 .user = OCP_USER_MPU | OCP_USER_SDMA,
3137 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3139 .pa_start = 0x48056000,
3140 .pa_end = 0x48056fff,
3141 .flags = ADDR_TYPE_RT
3146 /* l4_cfg -> dma_system */
3147 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3148 .master = &omap3xxx_l4_core_hwmod,
3149 .slave = &omap3xxx_dma_system_hwmod,
3150 .clk = "core_l4_ick",
3151 .addr = omap3xxx_dma_system_addrs,
3152 .user = OCP_USER_MPU | OCP_USER_SDMA,
3155 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3158 .pa_start = 0x48074000,
3159 .pa_end = 0x480740ff,
3160 .flags = ADDR_TYPE_RT
3165 /* l4_core -> mcbsp1 */
3166 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3167 .master = &omap3xxx_l4_core_hwmod,
3168 .slave = &omap3xxx_mcbsp1_hwmod,
3169 .clk = "mcbsp1_ick",
3170 .addr = omap3xxx_mcbsp1_addrs,
3171 .user = OCP_USER_MPU | OCP_USER_SDMA,
3174 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3177 .pa_start = 0x49022000,
3178 .pa_end = 0x490220ff,
3179 .flags = ADDR_TYPE_RT
3184 /* l4_per -> mcbsp2 */
3185 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3186 .master = &omap3xxx_l4_per_hwmod,
3187 .slave = &omap3xxx_mcbsp2_hwmod,
3188 .clk = "mcbsp2_ick",
3189 .addr = omap3xxx_mcbsp2_addrs,
3190 .user = OCP_USER_MPU | OCP_USER_SDMA,
3193 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3196 .pa_start = 0x49024000,
3197 .pa_end = 0x490240ff,
3198 .flags = ADDR_TYPE_RT
3203 /* l4_per -> mcbsp3 */
3204 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3205 .master = &omap3xxx_l4_per_hwmod,
3206 .slave = &omap3xxx_mcbsp3_hwmod,
3207 .clk = "mcbsp3_ick",
3208 .addr = omap3xxx_mcbsp3_addrs,
3209 .user = OCP_USER_MPU | OCP_USER_SDMA,
3212 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3215 .pa_start = 0x49026000,
3216 .pa_end = 0x490260ff,
3217 .flags = ADDR_TYPE_RT
3222 /* l4_per -> mcbsp4 */
3223 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3224 .master = &omap3xxx_l4_per_hwmod,
3225 .slave = &omap3xxx_mcbsp4_hwmod,
3226 .clk = "mcbsp4_ick",
3227 .addr = omap3xxx_mcbsp4_addrs,
3228 .user = OCP_USER_MPU | OCP_USER_SDMA,
3231 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3234 .pa_start = 0x48096000,
3235 .pa_end = 0x480960ff,
3236 .flags = ADDR_TYPE_RT
3241 /* l4_core -> mcbsp5 */
3242 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3243 .master = &omap3xxx_l4_core_hwmod,
3244 .slave = &omap3xxx_mcbsp5_hwmod,
3245 .clk = "mcbsp5_ick",
3246 .addr = omap3xxx_mcbsp5_addrs,
3247 .user = OCP_USER_MPU | OCP_USER_SDMA,
3250 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3253 .pa_start = 0x49028000,
3254 .pa_end = 0x490280ff,
3255 .flags = ADDR_TYPE_RT
3260 /* l4_per -> mcbsp2_sidetone */
3261 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3262 .master = &omap3xxx_l4_per_hwmod,
3263 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
3264 .clk = "mcbsp2_ick",
3265 .addr = omap3xxx_mcbsp2_sidetone_addrs,
3266 .user = OCP_USER_MPU,
3269 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3272 .pa_start = 0x4902A000,
3273 .pa_end = 0x4902A0ff,
3274 .flags = ADDR_TYPE_RT
3279 /* l4_per -> mcbsp3_sidetone */
3280 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3281 .master = &omap3xxx_l4_per_hwmod,
3282 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
3283 .clk = "mcbsp3_ick",
3284 .addr = omap3xxx_mcbsp3_sidetone_addrs,
3285 .user = OCP_USER_MPU,
3288 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3290 .pa_start = 0x48094000,
3291 .pa_end = 0x480941ff,
3292 .flags = ADDR_TYPE_RT,
3297 /* l4_core -> mailbox */
3298 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3299 .master = &omap3xxx_l4_core_hwmod,
3300 .slave = &omap3xxx_mailbox_hwmod,
3301 .addr = omap3xxx_mailbox_addrs,
3302 .user = OCP_USER_MPU | OCP_USER_SDMA,
3305 /* l4 core -> mcspi1 interface */
3306 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3307 .master = &omap3xxx_l4_core_hwmod,
3308 .slave = &omap34xx_mcspi1,
3309 .clk = "mcspi1_ick",
3310 .addr = omap2_mcspi1_addr_space,
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3314 /* l4 core -> mcspi2 interface */
3315 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3316 .master = &omap3xxx_l4_core_hwmod,
3317 .slave = &omap34xx_mcspi2,
3318 .clk = "mcspi2_ick",
3319 .addr = omap2_mcspi2_addr_space,
3320 .user = OCP_USER_MPU | OCP_USER_SDMA,
3323 /* l4 core -> mcspi3 interface */
3324 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3325 .master = &omap3xxx_l4_core_hwmod,
3326 .slave = &omap34xx_mcspi3,
3327 .clk = "mcspi3_ick",
3328 .addr = omap2430_mcspi3_addr_space,
3329 .user = OCP_USER_MPU | OCP_USER_SDMA,
3332 /* l4 core -> mcspi4 interface */
3333 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3335 .pa_start = 0x480ba000,
3336 .pa_end = 0x480ba0ff,
3337 .flags = ADDR_TYPE_RT,
3342 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3343 .master = &omap3xxx_l4_core_hwmod,
3344 .slave = &omap34xx_mcspi4,
3345 .clk = "mcspi4_ick",
3346 .addr = omap34xx_mcspi4_addr_space,
3347 .user = OCP_USER_MPU | OCP_USER_SDMA,
3350 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3351 .master = &omap3xxx_usb_host_hs_hwmod,
3352 .slave = &omap3xxx_l3_main_hwmod,
3353 .clk = "core_l3_ick",
3354 .user = OCP_USER_MPU,
3357 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3360 .pa_start = 0x48064000,
3361 .pa_end = 0x480643ff,
3362 .flags = ADDR_TYPE_RT
3366 .pa_start = 0x48064400,
3367 .pa_end = 0x480647ff,
3371 .pa_start = 0x48064800,
3372 .pa_end = 0x48064cff,
3377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3378 .master = &omap3xxx_l4_core_hwmod,
3379 .slave = &omap3xxx_usb_host_hs_hwmod,
3380 .clk = "usbhost_ick",
3381 .addr = omap3xxx_usb_host_hs_addrs,
3382 .user = OCP_USER_MPU | OCP_USER_SDMA,
3385 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3388 .pa_start = 0x48062000,
3389 .pa_end = 0x48062fff,
3390 .flags = ADDR_TYPE_RT
3395 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3396 .master = &omap3xxx_l4_core_hwmod,
3397 .slave = &omap3xxx_usb_tll_hs_hwmod,
3398 .clk = "usbtll_ick",
3399 .addr = omap3xxx_usb_tll_hs_addrs,
3400 .user = OCP_USER_MPU | OCP_USER_SDMA,
3403 /* l4_core -> hdq1w interface */
3404 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3405 .master = &omap3xxx_l4_core_hwmod,
3406 .slave = &omap3xxx_hdq1w_hwmod,
3408 .addr = omap2_hdq1w_addr_space,
3409 .user = OCP_USER_MPU | OCP_USER_SDMA,
3410 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3413 /* l4_wkup -> 32ksync_counter */
3414 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3416 .pa_start = 0x48320000,
3417 .pa_end = 0x4832001f,
3418 .flags = ADDR_TYPE_RT
3423 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3425 .pa_start = 0x6e000000,
3426 .pa_end = 0x6e000fff,
3427 .flags = ADDR_TYPE_RT
3432 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3433 .master = &omap3xxx_l4_wkup_hwmod,
3434 .slave = &omap3xxx_counter_32k_hwmod,
3435 .clk = "omap_32ksync_ick",
3436 .addr = omap3xxx_counter_32k_addrs,
3437 .user = OCP_USER_MPU | OCP_USER_SDMA,
3440 /* am35xx has Davinci MDIO & EMAC */
3441 static struct omap_hwmod_class am35xx_mdio_class = {
3442 .name = "davinci_mdio",
3445 static struct omap_hwmod am35xx_mdio_hwmod = {
3446 .name = "davinci_mdio",
3447 .class = &am35xx_mdio_class,
3448 .flags = HWMOD_NO_IDLEST,
3452 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3453 * but this will probably require some additional hwmod core support,
3454 * so is left as a future to-do item.
3456 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3457 .master = &am35xx_mdio_hwmod,
3458 .slave = &omap3xxx_l3_main_hwmod,
3460 .user = OCP_USER_MPU,
3463 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3465 .pa_start = AM35XX_IPSS_MDIO_BASE,
3466 .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3467 .flags = ADDR_TYPE_RT,
3472 /* l4_core -> davinci mdio */
3474 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3475 * but this will probably require some additional hwmod core support,
3476 * so is left as a future to-do item.
3478 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3479 .master = &omap3xxx_l4_core_hwmod,
3480 .slave = &am35xx_mdio_hwmod,
3482 .addr = am35xx_mdio_addrs,
3483 .user = OCP_USER_MPU,
3486 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3487 { .name = "rxthresh", .irq = 67 + OMAP_INTC_START, },
3488 { .name = "rx_pulse", .irq = 68 + OMAP_INTC_START, },
3489 { .name = "tx_pulse", .irq = 69 + OMAP_INTC_START },
3490 { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3494 static struct omap_hwmod_class am35xx_emac_class = {
3495 .name = "davinci_emac",
3498 static struct omap_hwmod am35xx_emac_hwmod = {
3499 .name = "davinci_emac",
3500 .mpu_irqs = am35xx_emac_mpu_irqs,
3501 .class = &am35xx_emac_class,
3502 .flags = HWMOD_NO_IDLEST,
3505 /* l3_core -> davinci emac interface */
3507 * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3508 * but this will probably require some additional hwmod core support,
3509 * so is left as a future to-do item.
3511 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3512 .master = &am35xx_emac_hwmod,
3513 .slave = &omap3xxx_l3_main_hwmod,
3515 .user = OCP_USER_MPU,
3518 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3520 .pa_start = AM35XX_IPSS_EMAC_BASE,
3521 .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3522 .flags = ADDR_TYPE_RT,
3527 /* l4_core -> davinci emac */
3529 * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3530 * but this will probably require some additional hwmod core support,
3531 * so is left as a future to-do item.
3533 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3534 .master = &omap3xxx_l4_core_hwmod,
3535 .slave = &am35xx_emac_hwmod,
3537 .addr = am35xx_emac_addrs,
3538 .user = OCP_USER_MPU,
3541 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3542 .master = &omap3xxx_l3_main_hwmod,
3543 .slave = &omap3xxx_gpmc_hwmod,
3544 .clk = "core_l3_ick",
3545 .addr = omap3xxx_gpmc_addrs,
3546 .user = OCP_USER_MPU | OCP_USER_SDMA,
3549 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3550 &omap3xxx_l3_main__l4_core,
3551 &omap3xxx_l3_main__l4_per,
3552 &omap3xxx_mpu__l3_main,
3553 &omap3xxx_l3_main__l4_debugss,
3554 &omap3xxx_l4_core__l4_wkup,
3555 &omap3xxx_l4_core__mmc3,
3556 &omap3_l4_core__uart1,
3557 &omap3_l4_core__uart2,
3558 &omap3_l4_per__uart3,
3559 &omap3_l4_core__i2c1,
3560 &omap3_l4_core__i2c2,
3561 &omap3_l4_core__i2c3,
3562 &omap3xxx_l4_wkup__l4_sec,
3563 &omap3xxx_l4_wkup__timer1,
3564 &omap3xxx_l4_per__timer2,
3565 &omap3xxx_l4_per__timer3,
3566 &omap3xxx_l4_per__timer4,
3567 &omap3xxx_l4_per__timer5,
3568 &omap3xxx_l4_per__timer6,
3569 &omap3xxx_l4_per__timer7,
3570 &omap3xxx_l4_per__timer8,
3571 &omap3xxx_l4_per__timer9,
3572 &omap3xxx_l4_core__timer10,
3573 &omap3xxx_l4_core__timer11,
3574 &omap3xxx_l4_wkup__wd_timer2,
3575 &omap3xxx_l4_wkup__gpio1,
3576 &omap3xxx_l4_per__gpio2,
3577 &omap3xxx_l4_per__gpio3,
3578 &omap3xxx_l4_per__gpio4,
3579 &omap3xxx_l4_per__gpio5,
3580 &omap3xxx_l4_per__gpio6,
3581 &omap3xxx_dma_system__l3,
3582 &omap3xxx_l4_core__dma_system,
3583 &omap3xxx_l4_core__mcbsp1,
3584 &omap3xxx_l4_per__mcbsp2,
3585 &omap3xxx_l4_per__mcbsp3,
3586 &omap3xxx_l4_per__mcbsp4,
3587 &omap3xxx_l4_core__mcbsp5,
3588 &omap3xxx_l4_per__mcbsp2_sidetone,
3589 &omap3xxx_l4_per__mcbsp3_sidetone,
3590 &omap34xx_l4_core__mcspi1,
3591 &omap34xx_l4_core__mcspi2,
3592 &omap34xx_l4_core__mcspi3,
3593 &omap34xx_l4_core__mcspi4,
3594 &omap3xxx_l4_wkup__counter_32k,
3595 &omap3xxx_l3_main__gpmc,
3599 /* GP-only hwmod links */
3600 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3601 &omap3xxx_l4_sec__timer12,
3605 /* 3430ES1-only hwmod links */
3606 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3607 &omap3430es1_dss__l3,
3608 &omap3430es1_l4_core__dss,
3612 /* 3430ES2+-only hwmod links */
3613 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3615 &omap3xxx_l4_core__dss,
3616 &omap3xxx_usbhsotg__l3,
3617 &omap3xxx_l4_core__usbhsotg,
3618 &omap3xxx_usb_host_hs__l3_main_2,
3619 &omap3xxx_l4_core__usb_host_hs,
3620 &omap3xxx_l4_core__usb_tll_hs,
3624 /* <= 3430ES3-only hwmod links */
3625 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3626 &omap3xxx_l4_core__pre_es3_mmc1,
3627 &omap3xxx_l4_core__pre_es3_mmc2,
3631 /* 3430ES3+-only hwmod links */
3632 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3633 &omap3xxx_l4_core__es3plus_mmc1,
3634 &omap3xxx_l4_core__es3plus_mmc2,
3638 /* 34xx-only hwmod links (all ES revisions) */
3639 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3641 &omap34xx_l4_core__sr1,
3642 &omap34xx_l4_core__sr2,
3643 &omap3xxx_l4_core__mailbox,
3644 &omap3xxx_l4_core__hdq1w,
3645 &omap3xxx_sad2d__l3,
3646 &omap3xxx_l4_core__mmu_isp,
3647 #ifdef CONFIG_OMAP_IOMMU_IVA2
3648 &omap3xxx_l3_main__mmu_iva,
3653 /* 36xx-only hwmod links (all ES revisions) */
3654 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3656 &omap36xx_l4_per__uart4,
3658 &omap3xxx_l4_core__dss,
3659 &omap36xx_l4_core__sr1,
3660 &omap36xx_l4_core__sr2,
3661 &omap3xxx_usbhsotg__l3,
3662 &omap3xxx_l4_core__usbhsotg,
3663 &omap3xxx_l4_core__mailbox,
3664 &omap3xxx_usb_host_hs__l3_main_2,
3665 &omap3xxx_l4_core__usb_host_hs,
3666 &omap3xxx_l4_core__usb_tll_hs,
3667 &omap3xxx_l4_core__es3plus_mmc1,
3668 &omap3xxx_l4_core__es3plus_mmc2,
3669 &omap3xxx_l4_core__hdq1w,
3670 &omap3xxx_sad2d__l3,
3671 &omap3xxx_l4_core__mmu_isp,
3672 #ifdef CONFIG_OMAP_IOMMU_IVA2
3673 &omap3xxx_l3_main__mmu_iva,
3678 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3680 &omap3xxx_l4_core__dss,
3681 &am35xx_usbhsotg__l3,
3682 &am35xx_l4_core__usbhsotg,
3683 &am35xx_l4_core__uart4,
3684 &omap3xxx_usb_host_hs__l3_main_2,
3685 &omap3xxx_l4_core__usb_host_hs,
3686 &omap3xxx_l4_core__usb_tll_hs,
3687 &omap3xxx_l4_core__es3plus_mmc1,
3688 &omap3xxx_l4_core__es3plus_mmc2,
3689 &omap3xxx_l4_core__hdq1w,
3691 &am35xx_l4_core__mdio,
3693 &am35xx_l4_core__emac,
3697 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3698 &omap3xxx_l4_core__dss_dispc,
3699 &omap3xxx_l4_core__dss_dsi1,
3700 &omap3xxx_l4_core__dss_rfbi,
3701 &omap3xxx_l4_core__dss_venc,
3705 int __init omap3xxx_hwmod_init(void)
3708 struct omap_hwmod_ocp_if **h = NULL;
3713 /* Register hwmod links common to all OMAP3 */
3714 r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3718 /* Register GP-only hwmod links. */
3719 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3720 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3728 * Register hwmod links common to individual OMAP3 families, all
3729 * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3730 * All possible revisions should be included in this conditional.
3732 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3733 rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3734 rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3735 h = omap34xx_hwmod_ocp_ifs;
3736 } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3737 h = am35xx_hwmod_ocp_ifs;
3738 } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3739 rev == OMAP3630_REV_ES1_2) {
3740 h = omap36xx_hwmod_ocp_ifs;
3742 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3746 r = omap_hwmod_register_links(h);
3751 * Register hwmod links specific to certain ES levels of a
3752 * particular family of silicon (e.g., 34xx ES1.0)
3755 if (rev == OMAP3430_REV_ES1_0) {
3756 h = omap3430es1_hwmod_ocp_ifs;
3757 } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3758 rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3759 rev == OMAP3430_REV_ES3_1_2) {
3760 h = omap3430es2plus_hwmod_ocp_ifs;
3764 r = omap_hwmod_register_links(h);
3770 if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3771 rev == OMAP3430_REV_ES2_1) {
3772 h = omap3430_pre_es3_hwmod_ocp_ifs;
3773 } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3774 rev == OMAP3430_REV_ES3_1_2) {
3775 h = omap3430_es3plus_hwmod_ocp_ifs;
3779 r = omap_hwmod_register_links(h);
3784 * DSS code presumes that dss_core hwmod is handled first,
3785 * _before_ any other DSS related hwmods so register common
3786 * DSS hwmod links last to ensure that dss_core is already
3787 * registered. Otherwise some change things may happen, for
3788 * ex. if dispc is handled before dss_core and DSS is enabled
3789 * in bootloader DISPC will be reset with outputs enabled
3790 * which sometimes leads to unrecoverable L3 error. XXX The
3791 * long-term fix to this is to ensure hwmods are set up in
3792 * dependency order in the hwmod core code.
3794 r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);