2 * Copyright (C) 2013 Texas Instruments Incorporated
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_33xx_43xx_common_data.h"
22 #include "omap_hwmod_common_data.h"
27 static struct omap_hwmod am43xx_l4_hs_hwmod = {
29 .class = &am33xx_l4_hwmod_class,
30 .clkdm_name = "l3_clkdm",
31 .flags = HWMOD_INIT_NO_IDLE,
32 .main_clk = "l4hs_gclk",
35 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
36 .modulemode = MODULEMODE_SWCTRL,
41 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
42 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
45 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
47 .class = &am33xx_wkup_m3_hwmod_class,
48 .clkdm_name = "l4_wkup_aon_clkdm",
49 /* Keep hardreset asserted */
50 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
51 .main_clk = "sys_clkin_ck",
54 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
55 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
56 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
57 .modulemode = MODULEMODE_SWCTRL,
60 .rst_lines = am33xx_wkup_m3_resets,
61 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
64 static struct omap_hwmod am43xx_control_hwmod = {
66 .class = &am33xx_control_hwmod_class,
67 .clkdm_name = "l4_wkup_clkdm",
68 .flags = HWMOD_INIT_NO_IDLE,
69 .main_clk = "sys_clkin_ck",
72 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
73 .modulemode = MODULEMODE_SWCTRL,
78 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
79 { .role = "dbclk", .clk = "gpio0_dbclk" },
82 static struct omap_hwmod am43xx_gpio0_hwmod = {
84 .class = &am33xx_gpio_hwmod_class,
85 .clkdm_name = "l4_wkup_clkdm",
86 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
87 .main_clk = "sys_clkin_ck",
90 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
91 .modulemode = MODULEMODE_SWCTRL,
94 .opt_clks = gpio0_opt_clks,
95 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
96 .dev_attr = &gpio_dev_attr,
99 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
102 .sysc_flags = SYSC_HAS_SIDLEMODE,
103 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
104 .sysc_fields = &omap_hwmod_sysc_type1,
107 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
109 .sysc = &am43xx_synctimer_sysc,
112 static struct omap_hwmod am43xx_synctimer_hwmod = {
113 .name = "counter_32k",
114 .class = &am43xx_synctimer_hwmod_class,
115 .clkdm_name = "l4_wkup_aon_clkdm",
116 .flags = HWMOD_SWSUP_SIDLE,
117 .main_clk = "synctimer_32kclk",
120 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
121 .modulemode = MODULEMODE_SWCTRL,
126 static struct omap_hwmod am43xx_timer8_hwmod = {
128 .class = &am33xx_timer_hwmod_class,
129 .clkdm_name = "l4ls_clkdm",
130 .main_clk = "timer8_fck",
133 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
134 .modulemode = MODULEMODE_SWCTRL,
139 static struct omap_hwmod am43xx_timer9_hwmod = {
141 .class = &am33xx_timer_hwmod_class,
142 .clkdm_name = "l4ls_clkdm",
143 .main_clk = "timer9_fck",
146 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
147 .modulemode = MODULEMODE_SWCTRL,
152 static struct omap_hwmod am43xx_timer10_hwmod = {
154 .class = &am33xx_timer_hwmod_class,
155 .clkdm_name = "l4ls_clkdm",
156 .main_clk = "timer10_fck",
159 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
160 .modulemode = MODULEMODE_SWCTRL,
165 static struct omap_hwmod am43xx_timer11_hwmod = {
167 .class = &am33xx_timer_hwmod_class,
168 .clkdm_name = "l4ls_clkdm",
169 .main_clk = "timer11_fck",
172 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
173 .modulemode = MODULEMODE_SWCTRL,
178 static struct omap_hwmod am43xx_epwmss3_hwmod = {
180 .class = &am33xx_epwmss_hwmod_class,
181 .clkdm_name = "l4ls_clkdm",
182 .main_clk = "l4ls_gclk",
185 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
186 .modulemode = MODULEMODE_SWCTRL,
191 static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
193 .class = &am33xx_ehrpwm_hwmod_class,
194 .clkdm_name = "l4ls_clkdm",
195 .main_clk = "l4ls_gclk",
198 static struct omap_hwmod am43xx_epwmss4_hwmod = {
200 .class = &am33xx_epwmss_hwmod_class,
201 .clkdm_name = "l4ls_clkdm",
202 .main_clk = "l4ls_gclk",
205 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
206 .modulemode = MODULEMODE_SWCTRL,
211 static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
213 .class = &am33xx_ehrpwm_hwmod_class,
214 .clkdm_name = "l4ls_clkdm",
215 .main_clk = "l4ls_gclk",
218 static struct omap_hwmod am43xx_epwmss5_hwmod = {
220 .class = &am33xx_epwmss_hwmod_class,
221 .clkdm_name = "l4ls_clkdm",
222 .main_clk = "l4ls_gclk",
225 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
226 .modulemode = MODULEMODE_SWCTRL,
231 static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
233 .class = &am33xx_ehrpwm_hwmod_class,
234 .clkdm_name = "l4ls_clkdm",
235 .main_clk = "l4ls_gclk",
238 static struct omap_hwmod am43xx_spi2_hwmod = {
240 .class = &am33xx_spi_hwmod_class,
241 .clkdm_name = "l4ls_clkdm",
242 .main_clk = "dpll_per_m2_div4_ck",
245 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
246 .modulemode = MODULEMODE_SWCTRL,
249 .dev_attr = &mcspi_attrib,
252 static struct omap_hwmod am43xx_spi3_hwmod = {
254 .class = &am33xx_spi_hwmod_class,
255 .clkdm_name = "l4ls_clkdm",
256 .main_clk = "dpll_per_m2_div4_ck",
259 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
260 .modulemode = MODULEMODE_SWCTRL,
263 .dev_attr = &mcspi_attrib,
266 static struct omap_hwmod am43xx_spi4_hwmod = {
268 .class = &am33xx_spi_hwmod_class,
269 .clkdm_name = "l4ls_clkdm",
270 .main_clk = "dpll_per_m2_div4_ck",
273 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
274 .modulemode = MODULEMODE_SWCTRL,
277 .dev_attr = &mcspi_attrib,
280 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
281 { .role = "dbclk", .clk = "gpio4_dbclk" },
284 static struct omap_hwmod am43xx_gpio4_hwmod = {
286 .class = &am33xx_gpio_hwmod_class,
287 .clkdm_name = "l4ls_clkdm",
288 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
289 .main_clk = "l4ls_gclk",
292 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
293 .modulemode = MODULEMODE_SWCTRL,
296 .opt_clks = gpio4_opt_clks,
297 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
298 .dev_attr = &gpio_dev_attr,
301 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
302 { .role = "dbclk", .clk = "gpio5_dbclk" },
305 static struct omap_hwmod am43xx_gpio5_hwmod = {
307 .class = &am33xx_gpio_hwmod_class,
308 .clkdm_name = "l4ls_clkdm",
309 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
310 .main_clk = "l4ls_gclk",
313 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
314 .modulemode = MODULEMODE_SWCTRL,
317 .opt_clks = gpio5_opt_clks,
318 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
319 .dev_attr = &gpio_dev_attr,
322 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
326 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
328 .class = &am43xx_ocp2scp_hwmod_class,
329 .clkdm_name = "l4ls_clkdm",
330 .main_clk = "l4ls_gclk",
333 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
334 .modulemode = MODULEMODE_SWCTRL,
339 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
341 .class = &am43xx_ocp2scp_hwmod_class,
342 .clkdm_name = "l4ls_clkdm",
343 .main_clk = "l4ls_gclk",
346 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
347 .modulemode = MODULEMODE_SWCTRL,
352 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
355 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
357 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
358 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
359 MSTANDBY_NO | MSTANDBY_SMART |
360 MSTANDBY_SMART_WKUP),
361 .sysc_fields = &omap_hwmod_sysc_type2,
364 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
365 .name = "usb_otg_ss",
366 .sysc = &am43xx_usb_otg_ss_sysc,
369 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
370 .name = "usb_otg_ss0",
371 .class = &am43xx_usb_otg_ss_hwmod_class,
372 .clkdm_name = "l3s_clkdm",
373 .main_clk = "l3s_gclk",
376 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
377 .modulemode = MODULEMODE_SWCTRL,
382 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
383 .name = "usb_otg_ss1",
384 .class = &am43xx_usb_otg_ss_hwmod_class,
385 .clkdm_name = "l3s_clkdm",
386 .main_clk = "l3s_gclk",
389 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
390 .modulemode = MODULEMODE_SWCTRL,
395 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
397 .sysc_flags = SYSC_HAS_SIDLEMODE,
398 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
400 .sysc_fields = &omap_hwmod_sysc_type2,
403 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
405 .sysc = &am43xx_qspi_sysc,
408 static struct omap_hwmod am43xx_qspi_hwmod = {
410 .class = &am43xx_qspi_hwmod_class,
411 .clkdm_name = "l3s_clkdm",
412 .main_clk = "l3s_gclk",
415 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
416 .modulemode = MODULEMODE_SWCTRL,
423 * TouchScreen Controller (Analog-To-Digital Converter)
425 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
428 .sysc_flags = SYSC_HAS_SIDLEMODE,
429 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
431 .sysc_fields = &omap_hwmod_sysc_type2,
434 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
436 .sysc = &am43xx_adc_tsc_sysc,
439 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
441 .class = &am43xx_adc_tsc_hwmod_class,
442 .clkdm_name = "l3s_tsc_clkdm",
443 .main_clk = "adc_tsc_fck",
446 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
447 .modulemode = MODULEMODE_SWCTRL,
454 static struct omap_hwmod am43xx_dss_core_hwmod = {
456 .class = &omap2_dss_hwmod_class,
457 .clkdm_name = "dss_clkdm",
458 .main_clk = "disp_clk",
461 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
462 .modulemode = MODULEMODE_SWCTRL,
469 struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
471 .has_framedonetv_irq = 0
474 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
478 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
479 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
480 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
482 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
483 .sysc_fields = &omap_hwmod_sysc_type1,
486 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
488 .sysc = &am43xx_dispc_sysc,
491 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
493 .class = &am43xx_dispc_hwmod_class,
494 .clkdm_name = "dss_clkdm",
495 .main_clk = "disp_clk",
498 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
501 .dev_attr = &am43xx_dss_dispc_dev_attr,
502 .parent_hwmod = &am43xx_dss_core_hwmod,
507 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
509 .class = &omap2_rfbi_hwmod_class,
510 .clkdm_name = "dss_clkdm",
511 .main_clk = "disp_clk",
514 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
517 .parent_hwmod = &am43xx_dss_core_hwmod,
521 static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
525 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
526 .sysc_fields = &omap_hwmod_sysc_type1,
529 static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
531 .sysc = &am43xx_hdq1w_sysc,
532 .reset = &omap_hdq1w_reset,
535 static struct omap_hwmod am43xx_hdq1w_hwmod = {
537 .class = &am43xx_hdq1w_hwmod_class,
538 .clkdm_name = "l4ls_clkdm",
541 .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
542 .modulemode = MODULEMODE_SWCTRL,
548 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
549 .master = &am33xx_l3_main_hwmod,
550 .slave = &am43xx_l4_hs_hwmod,
552 .user = OCP_USER_MPU | OCP_USER_SDMA,
555 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
556 .master = &am43xx_wkup_m3_hwmod,
557 .slave = &am33xx_l4_wkup_hwmod,
558 .clk = "sys_clkin_ck",
559 .user = OCP_USER_MPU | OCP_USER_SDMA,
562 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
563 .master = &am33xx_l4_wkup_hwmod,
564 .slave = &am43xx_wkup_m3_hwmod,
565 .clk = "sys_clkin_ck",
566 .user = OCP_USER_MPU | OCP_USER_SDMA,
569 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
570 .master = &am33xx_l3_main_hwmod,
571 .slave = &am33xx_pruss_hwmod,
572 .clk = "dpll_core_m4_ck",
573 .user = OCP_USER_MPU,
576 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
577 .master = &am33xx_l4_wkup_hwmod,
578 .slave = &am33xx_smartreflex0_hwmod,
579 .clk = "sys_clkin_ck",
580 .user = OCP_USER_MPU,
583 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
584 .master = &am33xx_l4_wkup_hwmod,
585 .slave = &am33xx_smartreflex1_hwmod,
586 .clk = "sys_clkin_ck",
587 .user = OCP_USER_MPU,
590 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
591 .master = &am33xx_l4_wkup_hwmod,
592 .slave = &am43xx_control_hwmod,
593 .clk = "sys_clkin_ck",
594 .user = OCP_USER_MPU,
597 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
598 .master = &am33xx_l4_wkup_hwmod,
599 .slave = &am33xx_i2c1_hwmod,
600 .clk = "sys_clkin_ck",
601 .user = OCP_USER_MPU,
604 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
605 .master = &am33xx_l4_wkup_hwmod,
606 .slave = &am43xx_gpio0_hwmod,
607 .clk = "sys_clkin_ck",
608 .user = OCP_USER_MPU | OCP_USER_SDMA,
611 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
612 .master = &am33xx_l4_wkup_hwmod,
613 .slave = &am43xx_adc_tsc_hwmod,
614 .clk = "dpll_core_m4_div2_ck",
615 .user = OCP_USER_MPU,
618 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
619 .master = &am43xx_l4_hs_hwmod,
620 .slave = &am33xx_cpgmac0_hwmod,
621 .clk = "cpsw_125mhz_gclk",
622 .user = OCP_USER_MPU,
625 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
626 .master = &am33xx_l4_wkup_hwmod,
627 .slave = &am33xx_timer1_hwmod,
628 .clk = "sys_clkin_ck",
629 .user = OCP_USER_MPU,
632 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
633 .master = &am33xx_l4_wkup_hwmod,
634 .slave = &am33xx_uart1_hwmod,
635 .clk = "sys_clkin_ck",
636 .user = OCP_USER_MPU,
639 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
640 .master = &am33xx_l4_wkup_hwmod,
641 .slave = &am33xx_wd_timer1_hwmod,
642 .clk = "sys_clkin_ck",
643 .user = OCP_USER_MPU,
646 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
647 .master = &am33xx_l4_wkup_hwmod,
648 .slave = &am43xx_synctimer_hwmod,
649 .clk = "sys_clkin_ck",
650 .user = OCP_USER_MPU,
653 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
654 .master = &am33xx_l4_ls_hwmod,
655 .slave = &am43xx_timer8_hwmod,
657 .user = OCP_USER_MPU,
660 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
661 .master = &am33xx_l4_ls_hwmod,
662 .slave = &am43xx_timer9_hwmod,
664 .user = OCP_USER_MPU,
667 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
668 .master = &am33xx_l4_ls_hwmod,
669 .slave = &am43xx_timer10_hwmod,
671 .user = OCP_USER_MPU,
674 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
675 .master = &am33xx_l4_ls_hwmod,
676 .slave = &am43xx_timer11_hwmod,
678 .user = OCP_USER_MPU,
681 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
682 .master = &am33xx_l4_ls_hwmod,
683 .slave = &am43xx_epwmss3_hwmod,
685 .user = OCP_USER_MPU,
688 static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
689 .master = &am43xx_epwmss3_hwmod,
690 .slave = &am43xx_ehrpwm3_hwmod,
692 .user = OCP_USER_MPU,
695 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
696 .master = &am33xx_l4_ls_hwmod,
697 .slave = &am43xx_epwmss4_hwmod,
699 .user = OCP_USER_MPU,
702 static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
703 .master = &am43xx_epwmss4_hwmod,
704 .slave = &am43xx_ehrpwm4_hwmod,
706 .user = OCP_USER_MPU,
709 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
710 .master = &am33xx_l4_ls_hwmod,
711 .slave = &am43xx_epwmss5_hwmod,
713 .user = OCP_USER_MPU,
716 static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
717 .master = &am43xx_epwmss5_hwmod,
718 .slave = &am43xx_ehrpwm5_hwmod,
720 .user = OCP_USER_MPU,
723 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
724 .master = &am33xx_l4_ls_hwmod,
725 .slave = &am43xx_spi2_hwmod,
727 .user = OCP_USER_MPU,
730 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
731 .master = &am33xx_l4_ls_hwmod,
732 .slave = &am43xx_spi3_hwmod,
734 .user = OCP_USER_MPU,
737 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
738 .master = &am33xx_l4_ls_hwmod,
739 .slave = &am43xx_spi4_hwmod,
741 .user = OCP_USER_MPU,
744 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
745 .master = &am33xx_l4_ls_hwmod,
746 .slave = &am43xx_gpio4_hwmod,
748 .user = OCP_USER_MPU | OCP_USER_SDMA,
751 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
752 .master = &am33xx_l4_ls_hwmod,
753 .slave = &am43xx_gpio5_hwmod,
755 .user = OCP_USER_MPU | OCP_USER_SDMA,
758 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
759 .master = &am33xx_l4_ls_hwmod,
760 .slave = &am43xx_ocp2scp0_hwmod,
762 .user = OCP_USER_MPU,
765 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
766 .master = &am33xx_l4_ls_hwmod,
767 .slave = &am43xx_ocp2scp1_hwmod,
769 .user = OCP_USER_MPU,
772 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
773 .master = &am33xx_l3_s_hwmod,
774 .slave = &am43xx_usb_otg_ss0_hwmod,
776 .user = OCP_USER_MPU | OCP_USER_SDMA,
779 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
780 .master = &am33xx_l3_s_hwmod,
781 .slave = &am43xx_usb_otg_ss1_hwmod,
783 .user = OCP_USER_MPU | OCP_USER_SDMA,
786 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
787 .master = &am33xx_l3_s_hwmod,
788 .slave = &am43xx_qspi_hwmod,
790 .user = OCP_USER_MPU | OCP_USER_SDMA,
793 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
794 .master = &am43xx_dss_core_hwmod,
795 .slave = &am33xx_l3_main_hwmod,
797 .user = OCP_USER_MPU | OCP_USER_SDMA,
800 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
801 .master = &am33xx_l4_ls_hwmod,
802 .slave = &am43xx_dss_core_hwmod,
804 .user = OCP_USER_MPU | OCP_USER_SDMA,
807 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
808 .master = &am33xx_l4_ls_hwmod,
809 .slave = &am43xx_dss_dispc_hwmod,
811 .user = OCP_USER_MPU | OCP_USER_SDMA,
814 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
815 .master = &am33xx_l4_ls_hwmod,
816 .slave = &am43xx_dss_rfbi_hwmod,
818 .user = OCP_USER_MPU | OCP_USER_SDMA,
821 static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
822 .master = &am33xx_l4_ls_hwmod,
823 .slave = &am43xx_hdq1w_hwmod,
825 .user = OCP_USER_MPU | OCP_USER_SDMA,
828 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
829 &am33xx_l4_wkup__synctimer,
830 &am43xx_l4_ls__timer8,
831 &am43xx_l4_ls__timer9,
832 &am43xx_l4_ls__timer10,
833 &am43xx_l4_ls__timer11,
834 &am43xx_l4_ls__epwmss3,
835 &am43xx_epwmss3__ehrpwm3,
836 &am43xx_l4_ls__epwmss4,
837 &am43xx_epwmss4__ehrpwm4,
838 &am43xx_l4_ls__epwmss5,
839 &am43xx_epwmss5__ehrpwm5,
840 &am43xx_l4_ls__mcspi2,
841 &am43xx_l4_ls__mcspi3,
842 &am43xx_l4_ls__mcspi4,
843 &am43xx_l4_ls__gpio4,
844 &am43xx_l4_ls__gpio5,
845 &am43xx_l3_main__pruss,
846 &am33xx_mpu__l3_main,
849 &am33xx_l3_s__l4_wkup,
850 &am43xx_l3_main__l4_hs,
851 &am33xx_l3_main__l3_s,
852 &am33xx_l3_main__l3_instr,
853 &am33xx_l3_main__gfx,
854 &am33xx_l3_s__l3_main,
855 &am33xx_pruss__l3_main,
856 &am43xx_wkup_m3__l4_wkup,
857 &am33xx_gfx__l3_main,
858 &am43xx_l4_wkup__wkup_m3,
859 &am43xx_l4_wkup__control,
860 &am43xx_l4_wkup__smartreflex0,
861 &am43xx_l4_wkup__smartreflex1,
862 &am43xx_l4_wkup__uart1,
863 &am43xx_l4_wkup__timer1,
864 &am43xx_l4_wkup__i2c1,
865 &am43xx_l4_wkup__gpio0,
866 &am43xx_l4_wkup__wd_timer1,
867 &am43xx_l4_wkup__adc_tsc,
869 &am33xx_l4_per__dcan0,
870 &am33xx_l4_per__dcan1,
871 &am33xx_l4_per__gpio1,
872 &am33xx_l4_per__gpio2,
873 &am33xx_l4_per__gpio3,
874 &am33xx_l4_per__i2c2,
875 &am33xx_l4_per__i2c3,
876 &am33xx_l4_per__mailbox,
877 &am33xx_l4_ls__mcasp0,
878 &am33xx_l4_ls__mcasp1,
882 &am33xx_l4_ls__timer2,
883 &am33xx_l4_ls__timer3,
884 &am33xx_l4_ls__timer4,
885 &am33xx_l4_ls__timer5,
886 &am33xx_l4_ls__timer6,
887 &am33xx_l4_ls__timer7,
888 &am33xx_l3_main__tpcc,
889 &am33xx_l4_ls__uart2,
890 &am33xx_l4_ls__uart3,
891 &am33xx_l4_ls__uart4,
892 &am33xx_l4_ls__uart5,
893 &am33xx_l4_ls__uart6,
894 &am33xx_l4_ls__spinlock,
896 &am33xx_l4_ls__epwmss0,
897 &am33xx_epwmss0__ecap0,
898 &am33xx_epwmss0__eqep0,
899 &am33xx_epwmss0__ehrpwm0,
900 &am33xx_l4_ls__epwmss1,
901 &am33xx_epwmss1__ecap1,
902 &am33xx_epwmss1__eqep1,
903 &am33xx_epwmss1__ehrpwm1,
904 &am33xx_l4_ls__epwmss2,
905 &am33xx_epwmss2__ecap2,
906 &am33xx_epwmss2__eqep2,
907 &am33xx_epwmss2__ehrpwm2,
909 &am33xx_l4_ls__mcspi0,
910 &am33xx_l4_ls__mcspi1,
911 &am33xx_l3_main__tptc0,
912 &am33xx_l3_main__tptc1,
913 &am33xx_l3_main__tptc2,
914 &am33xx_l3_main__ocmc,
915 &am43xx_l4_hs__cpgmac0,
916 &am33xx_cpgmac0__mdio,
917 &am33xx_l3_main__sha0,
918 &am33xx_l3_main__aes0,
919 &am43xx_l4_ls__ocp2scp0,
920 &am43xx_l4_ls__ocp2scp1,
921 &am43xx_l3_s__usbotgss0,
922 &am43xx_l3_s__usbotgss1,
923 &am43xx_dss__l3_main,
925 &am43xx_l4_ls__dss_dispc,
926 &am43xx_l4_ls__dss_rfbi,
927 &am43xx_l4_ls__hdq1w,
931 int __init am43xx_hwmod_init(void)
933 omap_hwmod_am43xx_reg();
935 return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);