2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
26 #include <plat/omap_hwmod.h>
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
34 #include <plat/iommu.h>
36 #include "omap_hwmod_common_data.h"
40 #include "prm-regbits-44xx.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
54 * 'c2c_target_fw' class
55 * instance(s): c2c_target_fw
57 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
58 .name = "c2c_target_fw",
62 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
63 .name = "c2c_target_fw",
64 .class = &omap44xx_c2c_target_fw_hwmod_class,
65 .clkdm_name = "d2d_clkdm",
68 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
69 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
83 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
84 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
88 static struct omap_hwmod omap44xx_dmm_hwmod = {
90 .class = &omap44xx_dmm_hwmod_class,
91 .clkdm_name = "l3_emif_clkdm",
92 .mpu_irqs = omap44xx_dmm_irqs,
95 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
96 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
103 * instance(s): emif_fw
105 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
110 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
112 .class = &omap44xx_emif_fw_hwmod_class,
113 .clkdm_name = "l3_emif_clkdm",
116 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
117 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
124 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
126 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
131 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
133 .class = &omap44xx_l3_hwmod_class,
134 .clkdm_name = "l3_instr_clkdm",
137 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
138 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
139 .modulemode = MODULEMODE_HWCTRL,
145 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
146 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
147 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
151 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
153 .class = &omap44xx_l3_hwmod_class,
154 .clkdm_name = "l3_1_clkdm",
155 .mpu_irqs = omap44xx_l3_main_1_irqs,
158 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
159 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
165 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
167 .class = &omap44xx_l3_hwmod_class,
168 .clkdm_name = "l3_2_clkdm",
171 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
172 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
178 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
180 .class = &omap44xx_l3_hwmod_class,
181 .clkdm_name = "l3_instr_clkdm",
184 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
185 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
186 .modulemode = MODULEMODE_HWCTRL,
193 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
195 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
200 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
202 .class = &omap44xx_l4_hwmod_class,
203 .clkdm_name = "abe_clkdm",
206 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
207 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
208 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
209 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
215 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
217 .class = &omap44xx_l4_hwmod_class,
218 .clkdm_name = "l4_cfg_clkdm",
221 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
222 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
228 static struct omap_hwmod omap44xx_l4_per_hwmod = {
230 .class = &omap44xx_l4_hwmod_class,
231 .clkdm_name = "l4_per_clkdm",
234 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
241 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
243 .class = &omap44xx_l4_hwmod_class,
244 .clkdm_name = "l4_wkup_clkdm",
247 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
248 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
255 * instance(s): mpu_private
257 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
262 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
263 .name = "mpu_private",
264 .class = &omap44xx_mpu_bus_hwmod_class,
265 .clkdm_name = "mpuss_clkdm",
268 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
275 * instance(s): ocp_wp_noc
277 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
278 .name = "ocp_wp_noc",
282 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
283 .name = "ocp_wp_noc",
284 .class = &omap44xx_ocp_wp_noc_hwmod_class,
285 .clkdm_name = "l3_instr_clkdm",
288 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
289 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
290 .modulemode = MODULEMODE_HWCTRL,
296 * Modules omap_hwmod structures
298 * The following IPs are excluded for the moment because:
299 * - They do not need an explicit SW control using omap_hwmod API.
300 * - They still need to be validated with the driver
301 * properly adapted to omap_hwmod / omap_device
308 * audio engine sub system
311 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
314 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
315 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
316 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
317 MSTANDBY_SMART_WKUP),
318 .sysc_fields = &omap_hwmod_sysc_type2,
321 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
323 .sysc = &omap44xx_aess_sysc,
327 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
328 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
332 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
333 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
334 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
335 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
336 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
337 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
338 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
339 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
340 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
344 static struct omap_hwmod omap44xx_aess_hwmod = {
346 .class = &omap44xx_aess_hwmod_class,
347 .clkdm_name = "abe_clkdm",
348 .mpu_irqs = omap44xx_aess_irqs,
349 .sdma_reqs = omap44xx_aess_sdma_reqs,
350 .main_clk = "aess_fck",
353 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
354 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
355 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
356 .modulemode = MODULEMODE_SWCTRL,
363 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
367 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
372 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
373 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
377 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
378 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
382 static struct omap_hwmod omap44xx_c2c_hwmod = {
384 .class = &omap44xx_c2c_hwmod_class,
385 .clkdm_name = "d2d_clkdm",
386 .mpu_irqs = omap44xx_c2c_irqs,
387 .sdma_reqs = omap44xx_c2c_sdma_reqs,
390 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
391 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
398 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
401 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
404 .sysc_flags = SYSC_HAS_SIDLEMODE,
405 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
406 .sysc_fields = &omap_hwmod_sysc_type1,
409 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
411 .sysc = &omap44xx_counter_sysc,
415 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
416 .name = "counter_32k",
417 .class = &omap44xx_counter_hwmod_class,
418 .clkdm_name = "l4_wkup_clkdm",
419 .flags = HWMOD_SWSUP_SIDLE,
420 .main_clk = "sys_32k_ck",
423 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
424 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
430 * 'ctrl_module' class
431 * attila core control module + core pad control module + wkup pad control
432 * module + attila wkup control module
435 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
438 .sysc_flags = SYSC_HAS_SIDLEMODE,
439 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
441 .sysc_fields = &omap_hwmod_sysc_type2,
444 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
445 .name = "ctrl_module",
446 .sysc = &omap44xx_ctrl_module_sysc,
449 /* ctrl_module_core */
450 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
451 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
455 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
456 .name = "ctrl_module_core",
457 .class = &omap44xx_ctrl_module_hwmod_class,
458 .clkdm_name = "l4_cfg_clkdm",
459 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
462 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
467 /* ctrl_module_pad_core */
468 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
469 .name = "ctrl_module_pad_core",
470 .class = &omap44xx_ctrl_module_hwmod_class,
471 .clkdm_name = "l4_cfg_clkdm",
474 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
479 /* ctrl_module_wkup */
480 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
481 .name = "ctrl_module_wkup",
482 .class = &omap44xx_ctrl_module_hwmod_class,
483 .clkdm_name = "l4_wkup_clkdm",
486 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
491 /* ctrl_module_pad_wkup */
492 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
493 .name = "ctrl_module_pad_wkup",
494 .class = &omap44xx_ctrl_module_hwmod_class,
495 .clkdm_name = "l4_wkup_clkdm",
498 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
505 * debug and emulation sub system
508 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
513 static struct omap_hwmod omap44xx_debugss_hwmod = {
515 .class = &omap44xx_debugss_hwmod_class,
516 .clkdm_name = "emu_sys_clkdm",
517 .main_clk = "trace_clk_div_ck",
520 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
528 * dma controller for data exchange between memory to memory (i.e. internal or
529 * external memory) and gp peripherals to memory or memory to gp peripherals
532 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
536 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
537 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
538 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
539 SYSS_HAS_RESET_STATUS),
540 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
541 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
542 .sysc_fields = &omap_hwmod_sysc_type1,
545 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
547 .sysc = &omap44xx_dma_sysc,
551 static struct omap_dma_dev_attr dma_dev_attr = {
552 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
553 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
558 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
559 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
560 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
561 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
562 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
566 static struct omap_hwmod omap44xx_dma_system_hwmod = {
567 .name = "dma_system",
568 .class = &omap44xx_dma_hwmod_class,
569 .clkdm_name = "l3_dma_clkdm",
570 .mpu_irqs = omap44xx_dma_system_irqs,
571 .main_clk = "l3_div_ck",
574 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
575 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
578 .dev_attr = &dma_dev_attr,
583 * digital microphone controller
586 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
589 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
590 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
591 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
593 .sysc_fields = &omap_hwmod_sysc_type2,
596 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
598 .sysc = &omap44xx_dmic_sysc,
602 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
603 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
607 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
608 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
612 static struct omap_hwmod omap44xx_dmic_hwmod = {
614 .class = &omap44xx_dmic_hwmod_class,
615 .clkdm_name = "abe_clkdm",
616 .mpu_irqs = omap44xx_dmic_irqs,
617 .sdma_reqs = omap44xx_dmic_sdma_reqs,
618 .main_clk = "dmic_fck",
621 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
622 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
623 .modulemode = MODULEMODE_SWCTRL,
633 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
638 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
639 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
643 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
644 { .name = "dsp", .rst_shift = 0 },
647 static struct omap_hwmod omap44xx_dsp_hwmod = {
649 .class = &omap44xx_dsp_hwmod_class,
650 .clkdm_name = "tesla_clkdm",
651 .mpu_irqs = omap44xx_dsp_irqs,
652 .rst_lines = omap44xx_dsp_resets,
653 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
654 .main_clk = "dsp_fck",
657 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
658 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
659 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
660 .modulemode = MODULEMODE_HWCTRL,
670 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
673 .sysc_flags = SYSS_HAS_RESET_STATUS,
676 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
678 .sysc = &omap44xx_dss_sysc,
679 .reset = omap_dss_reset,
683 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
684 { .role = "sys_clk", .clk = "dss_sys_clk" },
685 { .role = "tv_clk", .clk = "dss_tv_clk" },
686 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
689 static struct omap_hwmod omap44xx_dss_hwmod = {
691 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
692 .class = &omap44xx_dss_hwmod_class,
693 .clkdm_name = "l3_dss_clkdm",
694 .main_clk = "dss_dss_clk",
697 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
698 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
701 .opt_clks = dss_opt_clks,
702 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
710 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
714 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
715 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
716 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
717 SYSS_HAS_RESET_STATUS),
718 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
719 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
720 .sysc_fields = &omap_hwmod_sysc_type1,
723 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
725 .sysc = &omap44xx_dispc_sysc,
729 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
730 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
734 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
735 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
739 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
741 .has_framedonetv_irq = 1
744 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
746 .class = &omap44xx_dispc_hwmod_class,
747 .clkdm_name = "l3_dss_clkdm",
748 .mpu_irqs = omap44xx_dss_dispc_irqs,
749 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
750 .main_clk = "dss_dss_clk",
753 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
754 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
757 .dev_attr = &omap44xx_dss_dispc_dev_attr
762 * display serial interface controller
765 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
769 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
770 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
771 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
772 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
773 .sysc_fields = &omap_hwmod_sysc_type1,
776 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
778 .sysc = &omap44xx_dsi_sysc,
782 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
783 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
787 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
788 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
792 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
793 { .role = "sys_clk", .clk = "dss_sys_clk" },
796 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
798 .class = &omap44xx_dsi_hwmod_class,
799 .clkdm_name = "l3_dss_clkdm",
800 .mpu_irqs = omap44xx_dss_dsi1_irqs,
801 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
802 .main_clk = "dss_dss_clk",
805 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
806 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
809 .opt_clks = dss_dsi1_opt_clks,
810 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
814 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
815 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
819 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
820 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
824 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
825 { .role = "sys_clk", .clk = "dss_sys_clk" },
828 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
830 .class = &omap44xx_dsi_hwmod_class,
831 .clkdm_name = "l3_dss_clkdm",
832 .mpu_irqs = omap44xx_dss_dsi2_irqs,
833 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
834 .main_clk = "dss_dss_clk",
837 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
838 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
841 .opt_clks = dss_dsi2_opt_clks,
842 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
850 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
853 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
855 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
857 .sysc_fields = &omap_hwmod_sysc_type2,
860 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
862 .sysc = &omap44xx_hdmi_sysc,
866 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
867 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
871 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
872 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
876 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
877 { .role = "sys_clk", .clk = "dss_sys_clk" },
880 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
882 .class = &omap44xx_hdmi_hwmod_class,
883 .clkdm_name = "l3_dss_clkdm",
885 * HDMI audio requires to use no-idle mode. Hence,
886 * set idle mode by software.
888 .flags = HWMOD_SWSUP_SIDLE,
889 .mpu_irqs = omap44xx_dss_hdmi_irqs,
890 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
891 .main_clk = "dss_48mhz_clk",
894 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
895 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
898 .opt_clks = dss_hdmi_opt_clks,
899 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
904 * remote frame buffer interface
907 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
911 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
912 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
913 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
914 .sysc_fields = &omap_hwmod_sysc_type1,
917 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
919 .sysc = &omap44xx_rfbi_sysc,
923 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
924 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
928 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
929 { .role = "ick", .clk = "dss_fck" },
932 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
934 .class = &omap44xx_rfbi_hwmod_class,
935 .clkdm_name = "l3_dss_clkdm",
936 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
937 .main_clk = "dss_dss_clk",
940 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
941 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
944 .opt_clks = dss_rfbi_opt_clks,
945 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
953 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
958 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
960 .class = &omap44xx_venc_hwmod_class,
961 .clkdm_name = "l3_dss_clkdm",
962 .main_clk = "dss_tv_clk",
965 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
966 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
973 * bch error location module
976 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
980 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
981 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
982 SYSS_HAS_RESET_STATUS),
983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
984 .sysc_fields = &omap_hwmod_sysc_type1,
987 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
989 .sysc = &omap44xx_elm_sysc,
993 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
994 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
998 static struct omap_hwmod omap44xx_elm_hwmod = {
1000 .class = &omap44xx_elm_hwmod_class,
1001 .clkdm_name = "l4_per_clkdm",
1002 .mpu_irqs = omap44xx_elm_irqs,
1005 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1006 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1013 * external memory interface no1
1016 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1020 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1022 .sysc = &omap44xx_emif_sysc,
1026 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1027 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1031 static struct omap_hwmod omap44xx_emif1_hwmod = {
1033 .class = &omap44xx_emif_hwmod_class,
1034 .clkdm_name = "l3_emif_clkdm",
1035 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1036 .mpu_irqs = omap44xx_emif1_irqs,
1037 .main_clk = "ddrphy_ck",
1040 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1041 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_HWCTRL,
1048 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1049 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1053 static struct omap_hwmod omap44xx_emif2_hwmod = {
1055 .class = &omap44xx_emif_hwmod_class,
1056 .clkdm_name = "l3_emif_clkdm",
1057 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1058 .mpu_irqs = omap44xx_emif2_irqs,
1059 .main_clk = "ddrphy_ck",
1062 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1063 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1064 .modulemode = MODULEMODE_HWCTRL,
1071 * face detection hw accelerator module
1074 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1076 .sysc_offs = 0x0010,
1078 * FDIF needs 100 OCP clk cycles delay after a softreset before
1079 * accessing sysconfig again.
1080 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1081 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083 * TODO: Indicate errata when available.
1086 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1087 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1089 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1090 .sysc_fields = &omap_hwmod_sysc_type2,
1093 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1095 .sysc = &omap44xx_fdif_sysc,
1099 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1100 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1104 static struct omap_hwmod omap44xx_fdif_hwmod = {
1106 .class = &omap44xx_fdif_hwmod_class,
1107 .clkdm_name = "iss_clkdm",
1108 .mpu_irqs = omap44xx_fdif_irqs,
1109 .main_clk = "fdif_fck",
1112 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1113 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1114 .modulemode = MODULEMODE_SWCTRL,
1121 * general purpose io module
1124 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1126 .sysc_offs = 0x0010,
1127 .syss_offs = 0x0114,
1128 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1129 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1130 SYSS_HAS_RESET_STATUS),
1131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1133 .sysc_fields = &omap_hwmod_sysc_type1,
1136 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1138 .sysc = &omap44xx_gpio_sysc,
1143 static struct omap_gpio_dev_attr gpio_dev_attr = {
1149 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1150 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1154 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1155 { .role = "dbclk", .clk = "gpio1_dbclk" },
1158 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1160 .class = &omap44xx_gpio_hwmod_class,
1161 .clkdm_name = "l4_wkup_clkdm",
1162 .mpu_irqs = omap44xx_gpio1_irqs,
1163 .main_clk = "gpio1_ick",
1166 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1167 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1168 .modulemode = MODULEMODE_HWCTRL,
1171 .opt_clks = gpio1_opt_clks,
1172 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1173 .dev_attr = &gpio_dev_attr,
1177 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1178 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1182 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1183 { .role = "dbclk", .clk = "gpio2_dbclk" },
1186 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188 .class = &omap44xx_gpio_hwmod_class,
1189 .clkdm_name = "l4_per_clkdm",
1190 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1191 .mpu_irqs = omap44xx_gpio2_irqs,
1192 .main_clk = "gpio2_ick",
1195 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1196 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1197 .modulemode = MODULEMODE_HWCTRL,
1200 .opt_clks = gpio2_opt_clks,
1201 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1202 .dev_attr = &gpio_dev_attr,
1206 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1207 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1211 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1212 { .role = "dbclk", .clk = "gpio3_dbclk" },
1215 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1217 .class = &omap44xx_gpio_hwmod_class,
1218 .clkdm_name = "l4_per_clkdm",
1219 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1220 .mpu_irqs = omap44xx_gpio3_irqs,
1221 .main_clk = "gpio3_ick",
1224 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1225 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1226 .modulemode = MODULEMODE_HWCTRL,
1229 .opt_clks = gpio3_opt_clks,
1230 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1231 .dev_attr = &gpio_dev_attr,
1235 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1236 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1240 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1241 { .role = "dbclk", .clk = "gpio4_dbclk" },
1244 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1246 .class = &omap44xx_gpio_hwmod_class,
1247 .clkdm_name = "l4_per_clkdm",
1248 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249 .mpu_irqs = omap44xx_gpio4_irqs,
1250 .main_clk = "gpio4_ick",
1253 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1254 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1255 .modulemode = MODULEMODE_HWCTRL,
1258 .opt_clks = gpio4_opt_clks,
1259 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1260 .dev_attr = &gpio_dev_attr,
1264 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1265 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1269 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1270 { .role = "dbclk", .clk = "gpio5_dbclk" },
1273 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1275 .class = &omap44xx_gpio_hwmod_class,
1276 .clkdm_name = "l4_per_clkdm",
1277 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1278 .mpu_irqs = omap44xx_gpio5_irqs,
1279 .main_clk = "gpio5_ick",
1282 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1283 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1284 .modulemode = MODULEMODE_HWCTRL,
1287 .opt_clks = gpio5_opt_clks,
1288 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1289 .dev_attr = &gpio_dev_attr,
1293 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1294 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1298 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1299 { .role = "dbclk", .clk = "gpio6_dbclk" },
1302 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1304 .class = &omap44xx_gpio_hwmod_class,
1305 .clkdm_name = "l4_per_clkdm",
1306 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1307 .mpu_irqs = omap44xx_gpio6_irqs,
1308 .main_clk = "gpio6_ick",
1311 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1312 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1313 .modulemode = MODULEMODE_HWCTRL,
1316 .opt_clks = gpio6_opt_clks,
1317 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1318 .dev_attr = &gpio_dev_attr,
1323 * general purpose memory controller
1326 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1328 .sysc_offs = 0x0010,
1329 .syss_offs = 0x0014,
1330 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1331 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1332 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1333 .sysc_fields = &omap_hwmod_sysc_type1,
1336 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1338 .sysc = &omap44xx_gpmc_sysc,
1342 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1343 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1347 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1348 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1352 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1354 .class = &omap44xx_gpmc_hwmod_class,
1355 .clkdm_name = "l3_2_clkdm",
1357 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1358 * block. It is not being added due to any known bugs with
1359 * resetting the GPMC IP block, but rather because any timings
1360 * set by the bootloader are not being correctly programmed by
1361 * the kernel from the board file or DT data.
1362 * HWMOD_INIT_NO_RESET should be removed ASAP.
1364 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1365 .mpu_irqs = omap44xx_gpmc_irqs,
1366 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1369 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1370 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1371 .modulemode = MODULEMODE_HWCTRL,
1378 * 2d/3d graphics accelerator
1381 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1382 .rev_offs = 0x1fc00,
1383 .sysc_offs = 0x1fc10,
1384 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1385 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1386 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1387 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1388 .sysc_fields = &omap_hwmod_sysc_type2,
1391 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1393 .sysc = &omap44xx_gpu_sysc,
1397 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1398 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1402 static struct omap_hwmod omap44xx_gpu_hwmod = {
1404 .class = &omap44xx_gpu_hwmod_class,
1405 .clkdm_name = "l3_gfx_clkdm",
1406 .mpu_irqs = omap44xx_gpu_irqs,
1407 .main_clk = "gpu_fck",
1410 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1411 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1412 .modulemode = MODULEMODE_SWCTRL,
1419 * hdq / 1-wire serial interface controller
1422 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1424 .sysc_offs = 0x0014,
1425 .syss_offs = 0x0018,
1426 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1427 SYSS_HAS_RESET_STATUS),
1428 .sysc_fields = &omap_hwmod_sysc_type1,
1431 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1433 .sysc = &omap44xx_hdq1w_sysc,
1437 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1438 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1442 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1444 .class = &omap44xx_hdq1w_hwmod_class,
1445 .clkdm_name = "l4_per_clkdm",
1446 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1447 .mpu_irqs = omap44xx_hdq1w_irqs,
1448 .main_clk = "hdq1w_fck",
1451 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1452 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1453 .modulemode = MODULEMODE_SWCTRL,
1460 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1464 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1466 .sysc_offs = 0x0010,
1467 .syss_offs = 0x0014,
1468 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1469 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1470 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1471 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1472 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1473 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1474 .sysc_fields = &omap_hwmod_sysc_type1,
1477 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1479 .sysc = &omap44xx_hsi_sysc,
1483 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1484 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1485 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1486 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1490 static struct omap_hwmod omap44xx_hsi_hwmod = {
1492 .class = &omap44xx_hsi_hwmod_class,
1493 .clkdm_name = "l3_init_clkdm",
1494 .mpu_irqs = omap44xx_hsi_irqs,
1495 .main_clk = "hsi_fck",
1498 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1499 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1500 .modulemode = MODULEMODE_HWCTRL,
1507 * multimaster high-speed i2c controller
1510 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1511 .sysc_offs = 0x0010,
1512 .syss_offs = 0x0090,
1513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1514 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1515 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518 .clockact = CLOCKACT_TEST_ICLK,
1519 .sysc_fields = &omap_hwmod_sysc_type1,
1522 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1524 .sysc = &omap44xx_i2c_sysc,
1525 .rev = OMAP_I2C_IP_VERSION_2,
1526 .reset = &omap_i2c_reset,
1529 static struct omap_i2c_dev_attr i2c_dev_attr = {
1530 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1531 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548 .class = &omap44xx_i2c_hwmod_class,
1549 .clkdm_name = "l4_per_clkdm",
1550 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551 .mpu_irqs = omap44xx_i2c1_irqs,
1552 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1553 .main_clk = "i2c1_fck",
1556 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558 .modulemode = MODULEMODE_SWCTRL,
1561 .dev_attr = &i2c_dev_attr,
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578 .class = &omap44xx_i2c_hwmod_class,
1579 .clkdm_name = "l4_per_clkdm",
1580 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581 .mpu_irqs = omap44xx_i2c2_irqs,
1582 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1583 .main_clk = "i2c2_fck",
1586 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588 .modulemode = MODULEMODE_SWCTRL,
1591 .dev_attr = &i2c_dev_attr,
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608 .class = &omap44xx_i2c_hwmod_class,
1609 .clkdm_name = "l4_per_clkdm",
1610 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611 .mpu_irqs = omap44xx_i2c3_irqs,
1612 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1613 .main_clk = "i2c3_fck",
1616 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618 .modulemode = MODULEMODE_SWCTRL,
1621 .dev_attr = &i2c_dev_attr,
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638 .class = &omap44xx_i2c_hwmod_class,
1639 .clkdm_name = "l4_per_clkdm",
1640 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641 .mpu_irqs = omap44xx_i2c4_irqs,
1642 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1643 .main_clk = "i2c4_fck",
1646 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648 .modulemode = MODULEMODE_SWCTRL,
1651 .dev_attr = &i2c_dev_attr,
1656 * imaging processor unit
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670 { .name = "cpu0", .rst_shift = 0 },
1671 { .name = "cpu1", .rst_shift = 1 },
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676 .class = &omap44xx_ipu_hwmod_class,
1677 .clkdm_name = "ducati_clkdm",
1678 .mpu_irqs = omap44xx_ipu_irqs,
1679 .rst_lines = omap44xx_ipu_resets,
1680 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1681 .main_clk = "ipu_fck",
1684 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687 .modulemode = MODULEMODE_HWCTRL,
1694 * external images sensor pixel data processor
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699 .sysc_offs = 0x0010,
1701 * ISS needs 100 OCP clk cycles delay after a softreset before
1702 * accessing sysconfig again.
1703 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706 * TODO: Indicate errata when available.
1709 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714 .sysc_fields = &omap_hwmod_sysc_type2,
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719 .sysc = &omap44xx_iss_sysc,
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1742 .class = &omap44xx_iss_hwmod_class,
1743 .clkdm_name = "iss_clkdm",
1744 .mpu_irqs = omap44xx_iss_irqs,
1745 .sdma_reqs = omap44xx_iss_sdma_reqs,
1746 .main_clk = "iss_fck",
1749 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751 .modulemode = MODULEMODE_SWCTRL,
1754 .opt_clks = iss_opt_clks,
1755 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1760 * multi-standard video encoder/decoder hardware accelerator
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776 { .name = "seq0", .rst_shift = 0 },
1777 { .name = "seq1", .rst_shift = 1 },
1778 { .name = "logic", .rst_shift = 2 },
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1783 .class = &omap44xx_iva_hwmod_class,
1784 .clkdm_name = "ivahd_clkdm",
1785 .mpu_irqs = omap44xx_iva_irqs,
1786 .rst_lines = omap44xx_iva_resets,
1787 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1788 .main_clk = "iva_fck",
1791 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794 .modulemode = MODULEMODE_HWCTRL,
1801 * keyboard controller
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806 .sysc_offs = 0x0010,
1807 .syss_offs = 0x0014,
1808 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811 SYSS_HAS_RESET_STATUS),
1812 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813 .sysc_fields = &omap_hwmod_sysc_type1,
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818 .sysc = &omap44xx_kbd_sysc,
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829 .class = &omap44xx_kbd_hwmod_class,
1830 .clkdm_name = "l4_wkup_clkdm",
1831 .mpu_irqs = omap44xx_kbd_irqs,
1832 .main_clk = "kbd_fck",
1835 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837 .modulemode = MODULEMODE_SWCTRL,
1844 * mailbox module allowing communication between the on-chip processors using a
1845 * queued mailbox-interrupt mechanism.
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850 .sysc_offs = 0x0010,
1851 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852 SYSC_HAS_SOFTRESET),
1853 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854 .sysc_fields = &omap_hwmod_sysc_type2,
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859 .sysc = &omap44xx_mailbox_sysc,
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870 .class = &omap44xx_mailbox_hwmod_class,
1871 .clkdm_name = "l4_cfg_clkdm",
1872 .mpu_irqs = omap44xx_mailbox_irqs,
1875 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1883 * multi-channel audio serial port controller
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892 .sysc_offs = 0x0004,
1893 .sysc_flags = SYSC_HAS_SIDLEMODE,
1894 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901 .sysc = &omap44xx_mcasp_sysc,
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919 .class = &omap44xx_mcasp_hwmod_class,
1920 .clkdm_name = "abe_clkdm",
1921 .mpu_irqs = omap44xx_mcasp_irqs,
1922 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1923 .main_clk = "mcasp_fck",
1926 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928 .modulemode = MODULEMODE_SWCTRL,
1935 * multi channel buffered serial port controller
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939 .sysc_offs = 0x008c,
1940 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943 .sysc_fields = &omap_hwmod_sysc_type1,
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948 .sysc = &omap44xx_mcbsp_sysc,
1949 .rev = MCBSP_CONFIG_TYPE4,
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965 { .role = "pad_fck", .clk = "pad_clks_ck" },
1966 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971 .class = &omap44xx_mcbsp_hwmod_class,
1972 .clkdm_name = "abe_clkdm",
1973 .mpu_irqs = omap44xx_mcbsp1_irqs,
1974 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1975 .main_clk = "mcbsp1_fck",
1978 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980 .modulemode = MODULEMODE_SWCTRL,
1983 .opt_clks = mcbsp1_opt_clks,
1984 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000 { .role = "pad_fck", .clk = "pad_clks_ck" },
2001 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006 .class = &omap44xx_mcbsp_hwmod_class,
2007 .clkdm_name = "abe_clkdm",
2008 .mpu_irqs = omap44xx_mcbsp2_irqs,
2009 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2010 .main_clk = "mcbsp2_fck",
2013 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015 .modulemode = MODULEMODE_SWCTRL,
2018 .opt_clks = mcbsp2_opt_clks,
2019 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035 { .role = "pad_fck", .clk = "pad_clks_ck" },
2036 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041 .class = &omap44xx_mcbsp_hwmod_class,
2042 .clkdm_name = "abe_clkdm",
2043 .mpu_irqs = omap44xx_mcbsp3_irqs,
2044 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2045 .main_clk = "mcbsp3_fck",
2048 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050 .modulemode = MODULEMODE_SWCTRL,
2053 .opt_clks = mcbsp3_opt_clks,
2054 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070 { .role = "pad_fck", .clk = "pad_clks_ck" },
2071 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076 .class = &omap44xx_mcbsp_hwmod_class,
2077 .clkdm_name = "l4_per_clkdm",
2078 .mpu_irqs = omap44xx_mcbsp4_irqs,
2079 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2080 .main_clk = "mcbsp4_fck",
2083 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085 .modulemode = MODULEMODE_SWCTRL,
2088 .opt_clks = mcbsp4_opt_clks,
2089 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
2094 * multi channel pdm controller (proprietary interface with phoenix power
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100 .sysc_offs = 0x0010,
2101 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105 .sysc_fields = &omap_hwmod_sysc_type2,
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110 .sysc = &omap44xx_mcpdm_sysc,
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127 .class = &omap44xx_mcpdm_hwmod_class,
2128 .clkdm_name = "abe_clkdm",
2130 * It's suspected that the McPDM requires an off-chip main
2131 * functional clock, controlled via I2C. This IP block is
2132 * currently reset very early during boot, before I2C is
2133 * available, so it doesn't seem that we have any choice in
2134 * the kernel other than to avoid resetting it.
2136 .flags = HWMOD_EXT_OPT_MAIN_CLK,
2137 .mpu_irqs = omap44xx_mcpdm_irqs,
2138 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2139 .main_clk = "mcpdm_fck",
2142 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2143 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2144 .modulemode = MODULEMODE_SWCTRL,
2151 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2155 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2157 .sysc_offs = 0x0010,
2158 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2159 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2162 .sysc_fields = &omap_hwmod_sysc_type2,
2165 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2167 .sysc = &omap44xx_mcspi_sysc,
2168 .rev = OMAP4_MCSPI_REV,
2172 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2173 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2177 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2178 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2179 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2180 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2181 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2182 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2183 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2184 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2185 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2189 /* mcspi1 dev_attr */
2190 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2191 .num_chipselect = 4,
2194 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2196 .class = &omap44xx_mcspi_hwmod_class,
2197 .clkdm_name = "l4_per_clkdm",
2198 .mpu_irqs = omap44xx_mcspi1_irqs,
2199 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2200 .main_clk = "mcspi1_fck",
2203 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2204 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2205 .modulemode = MODULEMODE_SWCTRL,
2208 .dev_attr = &mcspi1_dev_attr,
2212 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2213 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2217 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2218 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2219 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2220 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2221 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2225 /* mcspi2 dev_attr */
2226 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2227 .num_chipselect = 2,
2230 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2232 .class = &omap44xx_mcspi_hwmod_class,
2233 .clkdm_name = "l4_per_clkdm",
2234 .mpu_irqs = omap44xx_mcspi2_irqs,
2235 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2236 .main_clk = "mcspi2_fck",
2239 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2240 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2241 .modulemode = MODULEMODE_SWCTRL,
2244 .dev_attr = &mcspi2_dev_attr,
2248 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2249 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2253 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2254 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2255 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2256 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2257 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2261 /* mcspi3 dev_attr */
2262 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2263 .num_chipselect = 2,
2266 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2268 .class = &omap44xx_mcspi_hwmod_class,
2269 .clkdm_name = "l4_per_clkdm",
2270 .mpu_irqs = omap44xx_mcspi3_irqs,
2271 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2272 .main_clk = "mcspi3_fck",
2275 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2276 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2277 .modulemode = MODULEMODE_SWCTRL,
2280 .dev_attr = &mcspi3_dev_attr,
2284 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2285 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2289 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2290 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2291 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2295 /* mcspi4 dev_attr */
2296 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2297 .num_chipselect = 1,
2300 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2302 .class = &omap44xx_mcspi_hwmod_class,
2303 .clkdm_name = "l4_per_clkdm",
2304 .mpu_irqs = omap44xx_mcspi4_irqs,
2305 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2306 .main_clk = "mcspi4_fck",
2309 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2310 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2311 .modulemode = MODULEMODE_SWCTRL,
2314 .dev_attr = &mcspi4_dev_attr,
2319 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2322 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2324 .sysc_offs = 0x0010,
2325 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2326 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2327 SYSC_HAS_SOFTRESET),
2328 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2329 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2330 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2331 .sysc_fields = &omap_hwmod_sysc_type2,
2334 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2336 .sysc = &omap44xx_mmc_sysc,
2340 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2341 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2345 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2346 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2347 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2352 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2353 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2356 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2358 .class = &omap44xx_mmc_hwmod_class,
2359 .clkdm_name = "l3_init_clkdm",
2360 .mpu_irqs = omap44xx_mmc1_irqs,
2361 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2362 .main_clk = "mmc1_fck",
2365 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2366 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2367 .modulemode = MODULEMODE_SWCTRL,
2370 .dev_attr = &mmc1_dev_attr,
2374 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2375 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2379 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2380 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2381 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2385 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2387 .class = &omap44xx_mmc_hwmod_class,
2388 .clkdm_name = "l3_init_clkdm",
2389 .mpu_irqs = omap44xx_mmc2_irqs,
2390 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2391 .main_clk = "mmc2_fck",
2394 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2395 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2396 .modulemode = MODULEMODE_SWCTRL,
2402 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2403 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2407 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2408 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2409 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2413 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2415 .class = &omap44xx_mmc_hwmod_class,
2416 .clkdm_name = "l4_per_clkdm",
2417 .mpu_irqs = omap44xx_mmc3_irqs,
2418 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2419 .main_clk = "mmc3_fck",
2422 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2423 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2424 .modulemode = MODULEMODE_SWCTRL,
2430 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2431 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2435 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2436 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2437 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2441 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2443 .class = &omap44xx_mmc_hwmod_class,
2444 .clkdm_name = "l4_per_clkdm",
2445 .mpu_irqs = omap44xx_mmc4_irqs,
2446 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2447 .main_clk = "mmc4_fck",
2450 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2451 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2452 .modulemode = MODULEMODE_SWCTRL,
2458 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2459 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2463 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2464 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2465 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2469 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2471 .class = &omap44xx_mmc_hwmod_class,
2472 .clkdm_name = "l4_per_clkdm",
2473 .mpu_irqs = omap44xx_mmc5_irqs,
2474 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2475 .main_clk = "mmc5_fck",
2478 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2479 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2480 .modulemode = MODULEMODE_SWCTRL,
2487 * The memory management unit performs virtual to physical address translation
2488 * for its requestors.
2491 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2495 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2496 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2497 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2498 .sysc_fields = &omap_hwmod_sysc_type1,
2501 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2508 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2510 .da_end = 0xfffff000,
2511 .nr_tlb_entries = 32,
2514 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2515 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2516 { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2520 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2521 { .name = "mmu_cache", .rst_shift = 2 },
2524 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2526 .pa_start = 0x55082000,
2527 .pa_end = 0x550820ff,
2528 .flags = ADDR_TYPE_RT,
2533 /* l3_main_2 -> mmu_ipu */
2534 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2535 .master = &omap44xx_l3_main_2_hwmod,
2536 .slave = &omap44xx_mmu_ipu_hwmod,
2538 .addr = omap44xx_mmu_ipu_addrs,
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2544 .class = &omap44xx_mmu_hwmod_class,
2545 .clkdm_name = "ducati_clkdm",
2546 .mpu_irqs = omap44xx_mmu_ipu_irqs,
2547 .rst_lines = omap44xx_mmu_ipu_resets,
2548 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2549 .main_clk = "ducati_clk_mux_ck",
2552 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2553 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2554 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2555 .modulemode = MODULEMODE_HWCTRL,
2558 .dev_attr = &mmu_ipu_dev_attr,
2563 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2565 .da_end = 0xfffff000,
2566 .nr_tlb_entries = 32,
2569 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2570 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2571 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2575 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2576 { .name = "mmu_cache", .rst_shift = 1 },
2579 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2581 .pa_start = 0x4a066000,
2582 .pa_end = 0x4a0660ff,
2583 .flags = ADDR_TYPE_RT,
2589 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2590 .master = &omap44xx_l4_cfg_hwmod,
2591 .slave = &omap44xx_mmu_dsp_hwmod,
2593 .addr = omap44xx_mmu_dsp_addrs,
2594 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2599 .class = &omap44xx_mmu_hwmod_class,
2600 .clkdm_name = "tesla_clkdm",
2601 .mpu_irqs = omap44xx_mmu_dsp_irqs,
2602 .rst_lines = omap44xx_mmu_dsp_resets,
2603 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2604 .main_clk = "dpll_iva_m4x2_ck",
2607 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2608 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2609 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2610 .modulemode = MODULEMODE_HWCTRL,
2613 .dev_attr = &mmu_dsp_dev_attr,
2621 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2626 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2627 { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2628 { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2629 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2630 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2631 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2635 static struct omap_hwmod omap44xx_mpu_hwmod = {
2637 .class = &omap44xx_mpu_hwmod_class,
2638 .clkdm_name = "mpuss_clkdm",
2639 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2640 .mpu_irqs = omap44xx_mpu_irqs,
2641 .main_clk = "dpll_mpu_m2_ck",
2644 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2645 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2652 * top-level core on-chip ram
2655 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2660 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2662 .class = &omap44xx_ocmc_ram_hwmod_class,
2663 .clkdm_name = "l3_2_clkdm",
2666 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2667 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2674 * bridge to transform ocp interface protocol to scp (serial control port)
2678 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2680 .sysc_offs = 0x0010,
2681 .syss_offs = 0x0014,
2682 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2683 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2684 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2685 .sysc_fields = &omap_hwmod_sysc_type1,
2688 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2690 .sysc = &omap44xx_ocp2scp_sysc,
2693 /* ocp2scp dev_attr */
2694 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2697 .start = 0x4a0ad080,
2699 .flags = IORESOURCE_MEM,
2702 /* XXX: Remove this once control module driver is in place */
2704 .start = 0x4a002300,
2706 .flags = IORESOURCE_MEM,
2711 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2713 .drv_name = "omap-usb2",
2714 .res = omap44xx_usb_phy_and_pll_addrs,
2719 /* ocp2scp_usb_phy */
2720 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2721 .name = "ocp2scp_usb_phy",
2722 .class = &omap44xx_ocp2scp_hwmod_class,
2723 .clkdm_name = "l3_init_clkdm",
2724 .main_clk = "ocp2scp_usb_phy_phy_48m",
2727 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2728 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2729 .modulemode = MODULEMODE_HWCTRL,
2732 .dev_attr = ocp2scp_dev_attr,
2737 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2738 * + clock manager 1 (in always on power domain) + local prm in mpu
2741 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2746 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2748 .class = &omap44xx_prcm_hwmod_class,
2749 .clkdm_name = "l4_wkup_clkdm",
2750 .flags = HWMOD_NO_IDLEST,
2753 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2759 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2760 .name = "cm_core_aon",
2761 .class = &omap44xx_prcm_hwmod_class,
2762 .flags = HWMOD_NO_IDLEST,
2765 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2771 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2773 .class = &omap44xx_prcm_hwmod_class,
2774 .flags = HWMOD_NO_IDLEST,
2777 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2783 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2784 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2788 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2789 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2790 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2793 static struct omap_hwmod omap44xx_prm_hwmod = {
2795 .class = &omap44xx_prcm_hwmod_class,
2796 .mpu_irqs = omap44xx_prm_irqs,
2797 .rst_lines = omap44xx_prm_resets,
2798 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2803 * system clock and reset manager
2806 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2811 static struct omap_hwmod omap44xx_scrm_hwmod = {
2813 .class = &omap44xx_scrm_hwmod_class,
2814 .clkdm_name = "l4_wkup_clkdm",
2817 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2824 * shared level 2 memory interface
2827 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2832 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2834 .class = &omap44xx_sl2if_hwmod_class,
2835 .clkdm_name = "ivahd_clkdm",
2838 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2839 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2840 .modulemode = MODULEMODE_HWCTRL,
2847 * bidirectional, multi-drop, multi-channel two-line serial interface between
2848 * the device and external components
2851 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2853 .sysc_offs = 0x0010,
2854 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2855 SYSC_HAS_SOFTRESET),
2856 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2858 .sysc_fields = &omap_hwmod_sysc_type2,
2861 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2863 .sysc = &omap44xx_slimbus_sysc,
2867 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2868 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2872 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2873 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2874 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2875 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2876 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2877 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2878 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2879 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2880 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2884 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2885 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2886 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2887 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2888 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2891 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2893 .class = &omap44xx_slimbus_hwmod_class,
2894 .clkdm_name = "abe_clkdm",
2895 .mpu_irqs = omap44xx_slimbus1_irqs,
2896 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2899 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2900 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2901 .modulemode = MODULEMODE_SWCTRL,
2904 .opt_clks = slimbus1_opt_clks,
2905 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2909 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2910 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2914 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2915 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2916 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2917 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2918 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2919 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2920 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2921 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2922 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2926 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2927 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2928 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2929 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2932 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2934 .class = &omap44xx_slimbus_hwmod_class,
2935 .clkdm_name = "l4_per_clkdm",
2936 .mpu_irqs = omap44xx_slimbus2_irqs,
2937 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2940 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2941 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2942 .modulemode = MODULEMODE_SWCTRL,
2945 .opt_clks = slimbus2_opt_clks,
2946 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2950 * 'smartreflex' class
2951 * smartreflex module (monitor silicon performance and outputs a measure of
2952 * performance error)
2955 /* The IP is not compliant to type1 / type2 scheme */
2956 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2961 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2962 .sysc_offs = 0x0038,
2963 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2964 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2966 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2969 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2970 .name = "smartreflex",
2971 .sysc = &omap44xx_smartreflex_sysc,
2975 /* smartreflex_core */
2976 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2977 .sensor_voltdm_name = "core",
2980 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2981 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2985 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2986 .name = "smartreflex_core",
2987 .class = &omap44xx_smartreflex_hwmod_class,
2988 .clkdm_name = "l4_ao_clkdm",
2989 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2991 .main_clk = "smartreflex_core_fck",
2994 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2995 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2996 .modulemode = MODULEMODE_SWCTRL,
2999 .dev_attr = &smartreflex_core_dev_attr,
3002 /* smartreflex_iva */
3003 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3004 .sensor_voltdm_name = "iva",
3007 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3008 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3012 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3013 .name = "smartreflex_iva",
3014 .class = &omap44xx_smartreflex_hwmod_class,
3015 .clkdm_name = "l4_ao_clkdm",
3016 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3017 .main_clk = "smartreflex_iva_fck",
3020 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3021 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3022 .modulemode = MODULEMODE_SWCTRL,
3025 .dev_attr = &smartreflex_iva_dev_attr,
3028 /* smartreflex_mpu */
3029 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3030 .sensor_voltdm_name = "mpu",
3033 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3034 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3038 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3039 .name = "smartreflex_mpu",
3040 .class = &omap44xx_smartreflex_hwmod_class,
3041 .clkdm_name = "l4_ao_clkdm",
3042 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3043 .main_clk = "smartreflex_mpu_fck",
3046 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3047 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3048 .modulemode = MODULEMODE_SWCTRL,
3051 .dev_attr = &smartreflex_mpu_dev_attr,
3056 * spinlock provides hardware assistance for synchronizing the processes
3057 * running on multiple processors
3060 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3062 .sysc_offs = 0x0010,
3063 .syss_offs = 0x0014,
3064 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3065 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3066 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3067 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3069 .sysc_fields = &omap_hwmod_sysc_type1,
3072 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3074 .sysc = &omap44xx_spinlock_sysc,
3078 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3080 .class = &omap44xx_spinlock_hwmod_class,
3081 .clkdm_name = "l4_cfg_clkdm",
3084 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3085 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3092 * general purpose timer module with accurate 1ms tick
3093 * This class contains several variants: ['timer_1ms', 'timer']
3096 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3098 .sysc_offs = 0x0010,
3099 .syss_offs = 0x0014,
3100 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3101 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3102 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3103 SYSS_HAS_RESET_STATUS),
3104 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3105 .sysc_fields = &omap_hwmod_sysc_type1,
3108 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3110 .sysc = &omap44xx_timer_1ms_sysc,
3113 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3115 .sysc_offs = 0x0010,
3116 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3117 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3118 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3120 .sysc_fields = &omap_hwmod_sysc_type2,
3123 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3125 .sysc = &omap44xx_timer_sysc,
3128 /* always-on timers dev attribute */
3129 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3130 .timer_capability = OMAP_TIMER_ALWON,
3133 /* pwm timers dev attribute */
3134 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3135 .timer_capability = OMAP_TIMER_HAS_PWM,
3138 /* timers with DSP interrupt dev attribute */
3139 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3140 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
3143 /* pwm timers with DSP interrupt dev attribute */
3144 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3145 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3149 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3150 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3154 static struct omap_hwmod omap44xx_timer1_hwmod = {
3156 .class = &omap44xx_timer_1ms_hwmod_class,
3157 .clkdm_name = "l4_wkup_clkdm",
3158 .mpu_irqs = omap44xx_timer1_irqs,
3159 .main_clk = "timer1_fck",
3162 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3163 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3164 .modulemode = MODULEMODE_SWCTRL,
3167 .dev_attr = &capability_alwon_dev_attr,
3171 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3172 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3176 static struct omap_hwmod omap44xx_timer2_hwmod = {
3178 .class = &omap44xx_timer_1ms_hwmod_class,
3179 .clkdm_name = "l4_per_clkdm",
3180 .mpu_irqs = omap44xx_timer2_irqs,
3181 .main_clk = "timer2_fck",
3184 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3185 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3186 .modulemode = MODULEMODE_SWCTRL,
3192 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3193 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3197 static struct omap_hwmod omap44xx_timer3_hwmod = {
3199 .class = &omap44xx_timer_hwmod_class,
3200 .clkdm_name = "l4_per_clkdm",
3201 .mpu_irqs = omap44xx_timer3_irqs,
3202 .main_clk = "timer3_fck",
3205 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3206 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3207 .modulemode = MODULEMODE_SWCTRL,
3213 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3214 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3218 static struct omap_hwmod omap44xx_timer4_hwmod = {
3220 .class = &omap44xx_timer_hwmod_class,
3221 .clkdm_name = "l4_per_clkdm",
3222 .mpu_irqs = omap44xx_timer4_irqs,
3223 .main_clk = "timer4_fck",
3226 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3227 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3228 .modulemode = MODULEMODE_SWCTRL,
3234 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3235 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3239 static struct omap_hwmod omap44xx_timer5_hwmod = {
3241 .class = &omap44xx_timer_hwmod_class,
3242 .clkdm_name = "abe_clkdm",
3243 .mpu_irqs = omap44xx_timer5_irqs,
3244 .main_clk = "timer5_fck",
3247 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3248 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3249 .modulemode = MODULEMODE_SWCTRL,
3252 .dev_attr = &capability_dsp_dev_attr,
3256 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3257 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3261 static struct omap_hwmod omap44xx_timer6_hwmod = {
3263 .class = &omap44xx_timer_hwmod_class,
3264 .clkdm_name = "abe_clkdm",
3265 .mpu_irqs = omap44xx_timer6_irqs,
3267 .main_clk = "timer6_fck",
3270 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3271 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3272 .modulemode = MODULEMODE_SWCTRL,
3275 .dev_attr = &capability_dsp_dev_attr,
3279 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3280 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3284 static struct omap_hwmod omap44xx_timer7_hwmod = {
3286 .class = &omap44xx_timer_hwmod_class,
3287 .clkdm_name = "abe_clkdm",
3288 .mpu_irqs = omap44xx_timer7_irqs,
3289 .main_clk = "timer7_fck",
3292 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3293 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3294 .modulemode = MODULEMODE_SWCTRL,
3297 .dev_attr = &capability_dsp_dev_attr,
3301 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3302 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3306 static struct omap_hwmod omap44xx_timer8_hwmod = {
3308 .class = &omap44xx_timer_hwmod_class,
3309 .clkdm_name = "abe_clkdm",
3310 .mpu_irqs = omap44xx_timer8_irqs,
3311 .main_clk = "timer8_fck",
3314 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3315 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3316 .modulemode = MODULEMODE_SWCTRL,
3319 .dev_attr = &capability_dsp_pwm_dev_attr,
3323 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3324 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3328 static struct omap_hwmod omap44xx_timer9_hwmod = {
3330 .class = &omap44xx_timer_hwmod_class,
3331 .clkdm_name = "l4_per_clkdm",
3332 .mpu_irqs = omap44xx_timer9_irqs,
3333 .main_clk = "timer9_fck",
3336 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3337 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3338 .modulemode = MODULEMODE_SWCTRL,
3341 .dev_attr = &capability_pwm_dev_attr,
3345 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3346 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3350 static struct omap_hwmod omap44xx_timer10_hwmod = {
3352 .class = &omap44xx_timer_1ms_hwmod_class,
3353 .clkdm_name = "l4_per_clkdm",
3354 .mpu_irqs = omap44xx_timer10_irqs,
3355 .main_clk = "timer10_fck",
3358 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3359 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3360 .modulemode = MODULEMODE_SWCTRL,
3363 .dev_attr = &capability_pwm_dev_attr,
3367 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3368 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3372 static struct omap_hwmod omap44xx_timer11_hwmod = {
3374 .class = &omap44xx_timer_hwmod_class,
3375 .clkdm_name = "l4_per_clkdm",
3376 .mpu_irqs = omap44xx_timer11_irqs,
3377 .main_clk = "timer11_fck",
3380 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3381 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3382 .modulemode = MODULEMODE_SWCTRL,
3385 .dev_attr = &capability_pwm_dev_attr,
3390 * universal asynchronous receiver/transmitter (uart)
3393 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3395 .sysc_offs = 0x0054,
3396 .syss_offs = 0x0058,
3397 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3398 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3399 SYSS_HAS_RESET_STATUS),
3400 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3402 .sysc_fields = &omap_hwmod_sysc_type1,
3405 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3407 .sysc = &omap44xx_uart_sysc,
3411 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3412 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3416 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3417 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3418 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3422 static struct omap_hwmod omap44xx_uart1_hwmod = {
3424 .class = &omap44xx_uart_hwmod_class,
3425 .clkdm_name = "l4_per_clkdm",
3426 .mpu_irqs = omap44xx_uart1_irqs,
3427 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3428 .main_clk = "uart1_fck",
3431 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3432 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3433 .modulemode = MODULEMODE_SWCTRL,
3439 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3440 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3444 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3445 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3446 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3450 static struct omap_hwmod omap44xx_uart2_hwmod = {
3452 .class = &omap44xx_uart_hwmod_class,
3453 .clkdm_name = "l4_per_clkdm",
3454 .mpu_irqs = omap44xx_uart2_irqs,
3455 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3456 .main_clk = "uart2_fck",
3459 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3460 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3461 .modulemode = MODULEMODE_SWCTRL,
3467 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3468 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3472 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3473 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3474 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3478 static struct omap_hwmod omap44xx_uart3_hwmod = {
3480 .class = &omap44xx_uart_hwmod_class,
3481 .clkdm_name = "l4_per_clkdm",
3482 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3483 .mpu_irqs = omap44xx_uart3_irqs,
3484 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3485 .main_clk = "uart3_fck",
3488 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3489 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3490 .modulemode = MODULEMODE_SWCTRL,
3496 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3497 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3501 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3502 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3503 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3507 static struct omap_hwmod omap44xx_uart4_hwmod = {
3509 .class = &omap44xx_uart_hwmod_class,
3510 .clkdm_name = "l4_per_clkdm",
3511 .mpu_irqs = omap44xx_uart4_irqs,
3512 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3513 .main_clk = "uart4_fck",
3516 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3517 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3518 .modulemode = MODULEMODE_SWCTRL,
3524 * 'usb_host_fs' class
3525 * full-speed usb host controller
3528 /* The IP is not compliant to type1 / type2 scheme */
3529 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3535 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3537 .sysc_offs = 0x0210,
3538 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3539 SYSC_HAS_SOFTRESET),
3540 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3542 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3545 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3546 .name = "usb_host_fs",
3547 .sysc = &omap44xx_usb_host_fs_sysc,
3551 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3552 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3553 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3557 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3558 .name = "usb_host_fs",
3559 .class = &omap44xx_usb_host_fs_hwmod_class,
3560 .clkdm_name = "l3_init_clkdm",
3561 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3562 .main_clk = "usb_host_fs_fck",
3565 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3566 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3567 .modulemode = MODULEMODE_SWCTRL,
3573 * 'usb_host_hs' class
3574 * high-speed multi-port usb host controller
3577 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3579 .sysc_offs = 0x0010,
3580 .syss_offs = 0x0014,
3581 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3582 SYSC_HAS_SOFTRESET),
3583 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3584 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3585 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3586 .sysc_fields = &omap_hwmod_sysc_type2,
3589 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3590 .name = "usb_host_hs",
3591 .sysc = &omap44xx_usb_host_hs_sysc,
3595 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3596 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3597 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3601 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3602 .name = "usb_host_hs",
3603 .class = &omap44xx_usb_host_hs_hwmod_class,
3604 .clkdm_name = "l3_init_clkdm",
3605 .main_clk = "usb_host_hs_fck",
3608 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3609 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3610 .modulemode = MODULEMODE_SWCTRL,
3613 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3616 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3620 * In the following configuration :
3621 * - USBHOST module is set to smart-idle mode
3622 * - PRCM asserts idle_req to the USBHOST module ( This typically
3623 * happens when the system is going to a low power mode : all ports
3624 * have been suspended, the master part of the USBHOST module has
3625 * entered the standby state, and SW has cut the functional clocks)
3626 * - an USBHOST interrupt occurs before the module is able to answer
3627 * idle_ack, typically a remote wakeup IRQ.
3628 * Then the USB HOST module will enter a deadlock situation where it
3629 * is no more accessible nor functional.
3632 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3636 * Errata: USB host EHCI may stall when entering smart-standby mode
3640 * When the USBHOST module is set to smart-standby mode, and when it is
3641 * ready to enter the standby state (i.e. all ports are suspended and
3642 * all attached devices are in suspend mode), then it can wrongly assert
3643 * the Mstandby signal too early while there are still some residual OCP
3644 * transactions ongoing. If this condition occurs, the internal state
3645 * machine may go to an undefined state and the USB link may be stuck
3646 * upon the next resume.
3649 * Don't use smart standby; use only force standby,
3650 * hence HWMOD_SWSUP_MSTANDBY
3654 * During system boot; If the hwmod framework resets the module
3655 * the module will have smart idle settings; which can lead to deadlock
3656 * (above Errata Id:i660); so, dont reset the module during boot;
3657 * Use HWMOD_INIT_NO_RESET.
3660 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3661 HWMOD_INIT_NO_RESET,
3665 * 'usb_otg_hs' class
3666 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3669 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3671 .sysc_offs = 0x0404,
3672 .syss_offs = 0x0408,
3673 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3674 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3675 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3676 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3677 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3679 .sysc_fields = &omap_hwmod_sysc_type1,
3682 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3683 .name = "usb_otg_hs",
3684 .sysc = &omap44xx_usb_otg_hs_sysc,
3688 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3689 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3690 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3694 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3695 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3698 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3699 .name = "usb_otg_hs",
3700 .class = &omap44xx_usb_otg_hs_hwmod_class,
3701 .clkdm_name = "l3_init_clkdm",
3702 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3703 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
3704 .main_clk = "usb_otg_hs_ick",
3707 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3708 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3709 .modulemode = MODULEMODE_HWCTRL,
3712 .opt_clks = usb_otg_hs_opt_clks,
3713 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3717 * 'usb_tll_hs' class
3718 * usb_tll_hs module is the adapter on the usb_host_hs ports
3721 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3723 .sysc_offs = 0x0010,
3724 .syss_offs = 0x0014,
3725 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3726 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3728 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3729 .sysc_fields = &omap_hwmod_sysc_type1,
3732 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3733 .name = "usb_tll_hs",
3734 .sysc = &omap44xx_usb_tll_hs_sysc,
3737 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3738 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3742 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3743 .name = "usb_tll_hs",
3744 .class = &omap44xx_usb_tll_hs_hwmod_class,
3745 .clkdm_name = "l3_init_clkdm",
3746 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3747 .main_clk = "usb_tll_hs_ick",
3750 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3751 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3752 .modulemode = MODULEMODE_HWCTRL,
3759 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3760 * overflow condition
3763 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3765 .sysc_offs = 0x0010,
3766 .syss_offs = 0x0014,
3767 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3768 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3769 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3771 .sysc_fields = &omap_hwmod_sysc_type1,
3774 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3776 .sysc = &omap44xx_wd_timer_sysc,
3777 .pre_shutdown = &omap2_wd_timer_disable,
3778 .reset = &omap2_wd_timer_reset,
3782 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3783 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3787 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3788 .name = "wd_timer2",
3789 .class = &omap44xx_wd_timer_hwmod_class,
3790 .clkdm_name = "l4_wkup_clkdm",
3791 .mpu_irqs = omap44xx_wd_timer2_irqs,
3792 .main_clk = "wd_timer2_fck",
3795 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3796 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3797 .modulemode = MODULEMODE_SWCTRL,
3803 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3804 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3808 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3809 .name = "wd_timer3",
3810 .class = &omap44xx_wd_timer_hwmod_class,
3811 .clkdm_name = "abe_clkdm",
3812 .mpu_irqs = omap44xx_wd_timer3_irqs,
3813 .main_clk = "wd_timer3_fck",
3816 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3817 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3818 .modulemode = MODULEMODE_SWCTRL,
3828 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3830 .pa_start = 0x4a204000,
3831 .pa_end = 0x4a2040ff,
3832 .flags = ADDR_TYPE_RT
3837 /* c2c -> c2c_target_fw */
3838 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3839 .master = &omap44xx_c2c_hwmod,
3840 .slave = &omap44xx_c2c_target_fw_hwmod,
3841 .clk = "div_core_ck",
3842 .addr = omap44xx_c2c_target_fw_addrs,
3843 .user = OCP_USER_MPU,
3846 /* l4_cfg -> c2c_target_fw */
3847 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3848 .master = &omap44xx_l4_cfg_hwmod,
3849 .slave = &omap44xx_c2c_target_fw_hwmod,
3851 .user = OCP_USER_MPU | OCP_USER_SDMA,
3854 /* l3_main_1 -> dmm */
3855 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3856 .master = &omap44xx_l3_main_1_hwmod,
3857 .slave = &omap44xx_dmm_hwmod,
3859 .user = OCP_USER_SDMA,
3862 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3864 .pa_start = 0x4e000000,
3865 .pa_end = 0x4e0007ff,
3866 .flags = ADDR_TYPE_RT
3872 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3873 .master = &omap44xx_mpu_hwmod,
3874 .slave = &omap44xx_dmm_hwmod,
3876 .addr = omap44xx_dmm_addrs,
3877 .user = OCP_USER_MPU,
3880 /* c2c -> emif_fw */
3881 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3882 .master = &omap44xx_c2c_hwmod,
3883 .slave = &omap44xx_emif_fw_hwmod,
3884 .clk = "div_core_ck",
3885 .user = OCP_USER_MPU | OCP_USER_SDMA,
3888 /* dmm -> emif_fw */
3889 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3890 .master = &omap44xx_dmm_hwmod,
3891 .slave = &omap44xx_emif_fw_hwmod,
3893 .user = OCP_USER_MPU | OCP_USER_SDMA,
3896 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3898 .pa_start = 0x4a20c000,
3899 .pa_end = 0x4a20c0ff,
3900 .flags = ADDR_TYPE_RT
3905 /* l4_cfg -> emif_fw */
3906 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3907 .master = &omap44xx_l4_cfg_hwmod,
3908 .slave = &omap44xx_emif_fw_hwmod,
3910 .addr = omap44xx_emif_fw_addrs,
3911 .user = OCP_USER_MPU,
3914 /* iva -> l3_instr */
3915 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3916 .master = &omap44xx_iva_hwmod,
3917 .slave = &omap44xx_l3_instr_hwmod,
3919 .user = OCP_USER_MPU | OCP_USER_SDMA,
3922 /* l3_main_3 -> l3_instr */
3923 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3924 .master = &omap44xx_l3_main_3_hwmod,
3925 .slave = &omap44xx_l3_instr_hwmod,
3927 .user = OCP_USER_MPU | OCP_USER_SDMA,
3930 /* ocp_wp_noc -> l3_instr */
3931 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3932 .master = &omap44xx_ocp_wp_noc_hwmod,
3933 .slave = &omap44xx_l3_instr_hwmod,
3935 .user = OCP_USER_MPU | OCP_USER_SDMA,
3938 /* dsp -> l3_main_1 */
3939 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3940 .master = &omap44xx_dsp_hwmod,
3941 .slave = &omap44xx_l3_main_1_hwmod,
3943 .user = OCP_USER_MPU | OCP_USER_SDMA,
3946 /* dss -> l3_main_1 */
3947 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3948 .master = &omap44xx_dss_hwmod,
3949 .slave = &omap44xx_l3_main_1_hwmod,
3951 .user = OCP_USER_MPU | OCP_USER_SDMA,
3954 /* l3_main_2 -> l3_main_1 */
3955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3956 .master = &omap44xx_l3_main_2_hwmod,
3957 .slave = &omap44xx_l3_main_1_hwmod,
3959 .user = OCP_USER_MPU | OCP_USER_SDMA,
3962 /* l4_cfg -> l3_main_1 */
3963 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3964 .master = &omap44xx_l4_cfg_hwmod,
3965 .slave = &omap44xx_l3_main_1_hwmod,
3967 .user = OCP_USER_MPU | OCP_USER_SDMA,
3970 /* mmc1 -> l3_main_1 */
3971 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3972 .master = &omap44xx_mmc1_hwmod,
3973 .slave = &omap44xx_l3_main_1_hwmod,
3975 .user = OCP_USER_MPU | OCP_USER_SDMA,
3978 /* mmc2 -> l3_main_1 */
3979 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3980 .master = &omap44xx_mmc2_hwmod,
3981 .slave = &omap44xx_l3_main_1_hwmod,
3983 .user = OCP_USER_MPU | OCP_USER_SDMA,
3986 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3988 .pa_start = 0x44000000,
3989 .pa_end = 0x44000fff,
3990 .flags = ADDR_TYPE_RT
3995 /* mpu -> l3_main_1 */
3996 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3997 .master = &omap44xx_mpu_hwmod,
3998 .slave = &omap44xx_l3_main_1_hwmod,
4000 .addr = omap44xx_l3_main_1_addrs,
4001 .user = OCP_USER_MPU,
4004 /* c2c_target_fw -> l3_main_2 */
4005 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4006 .master = &omap44xx_c2c_target_fw_hwmod,
4007 .slave = &omap44xx_l3_main_2_hwmod,
4009 .user = OCP_USER_MPU | OCP_USER_SDMA,
4012 /* debugss -> l3_main_2 */
4013 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4014 .master = &omap44xx_debugss_hwmod,
4015 .slave = &omap44xx_l3_main_2_hwmod,
4016 .clk = "dbgclk_mux_ck",
4017 .user = OCP_USER_MPU | OCP_USER_SDMA,
4020 /* dma_system -> l3_main_2 */
4021 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4022 .master = &omap44xx_dma_system_hwmod,
4023 .slave = &omap44xx_l3_main_2_hwmod,
4025 .user = OCP_USER_MPU | OCP_USER_SDMA,
4028 /* fdif -> l3_main_2 */
4029 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4030 .master = &omap44xx_fdif_hwmod,
4031 .slave = &omap44xx_l3_main_2_hwmod,
4033 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036 /* gpu -> l3_main_2 */
4037 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4038 .master = &omap44xx_gpu_hwmod,
4039 .slave = &omap44xx_l3_main_2_hwmod,
4041 .user = OCP_USER_MPU | OCP_USER_SDMA,
4044 /* hsi -> l3_main_2 */
4045 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4046 .master = &omap44xx_hsi_hwmod,
4047 .slave = &omap44xx_l3_main_2_hwmod,
4049 .user = OCP_USER_MPU | OCP_USER_SDMA,
4052 /* ipu -> l3_main_2 */
4053 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4054 .master = &omap44xx_ipu_hwmod,
4055 .slave = &omap44xx_l3_main_2_hwmod,
4057 .user = OCP_USER_MPU | OCP_USER_SDMA,
4060 /* iss -> l3_main_2 */
4061 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4062 .master = &omap44xx_iss_hwmod,
4063 .slave = &omap44xx_l3_main_2_hwmod,
4065 .user = OCP_USER_MPU | OCP_USER_SDMA,
4068 /* iva -> l3_main_2 */
4069 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4070 .master = &omap44xx_iva_hwmod,
4071 .slave = &omap44xx_l3_main_2_hwmod,
4073 .user = OCP_USER_MPU | OCP_USER_SDMA,
4076 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4078 .pa_start = 0x44800000,
4079 .pa_end = 0x44801fff,
4080 .flags = ADDR_TYPE_RT
4085 /* l3_main_1 -> l3_main_2 */
4086 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4087 .master = &omap44xx_l3_main_1_hwmod,
4088 .slave = &omap44xx_l3_main_2_hwmod,
4090 .addr = omap44xx_l3_main_2_addrs,
4091 .user = OCP_USER_MPU,
4094 /* l4_cfg -> l3_main_2 */
4095 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4096 .master = &omap44xx_l4_cfg_hwmod,
4097 .slave = &omap44xx_l3_main_2_hwmod,
4099 .user = OCP_USER_MPU | OCP_USER_SDMA,
4102 /* usb_host_fs -> l3_main_2 */
4103 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4104 .master = &omap44xx_usb_host_fs_hwmod,
4105 .slave = &omap44xx_l3_main_2_hwmod,
4107 .user = OCP_USER_MPU | OCP_USER_SDMA,
4110 /* usb_host_hs -> l3_main_2 */
4111 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4112 .master = &omap44xx_usb_host_hs_hwmod,
4113 .slave = &omap44xx_l3_main_2_hwmod,
4115 .user = OCP_USER_MPU | OCP_USER_SDMA,
4118 /* usb_otg_hs -> l3_main_2 */
4119 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4120 .master = &omap44xx_usb_otg_hs_hwmod,
4121 .slave = &omap44xx_l3_main_2_hwmod,
4123 .user = OCP_USER_MPU | OCP_USER_SDMA,
4126 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4128 .pa_start = 0x45000000,
4129 .pa_end = 0x45000fff,
4130 .flags = ADDR_TYPE_RT
4135 /* l3_main_1 -> l3_main_3 */
4136 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4137 .master = &omap44xx_l3_main_1_hwmod,
4138 .slave = &omap44xx_l3_main_3_hwmod,
4140 .addr = omap44xx_l3_main_3_addrs,
4141 .user = OCP_USER_MPU,
4144 /* l3_main_2 -> l3_main_3 */
4145 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4146 .master = &omap44xx_l3_main_2_hwmod,
4147 .slave = &omap44xx_l3_main_3_hwmod,
4149 .user = OCP_USER_MPU | OCP_USER_SDMA,
4152 /* l4_cfg -> l3_main_3 */
4153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4154 .master = &omap44xx_l4_cfg_hwmod,
4155 .slave = &omap44xx_l3_main_3_hwmod,
4157 .user = OCP_USER_MPU | OCP_USER_SDMA,
4160 /* aess -> l4_abe */
4161 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4162 .master = &omap44xx_aess_hwmod,
4163 .slave = &omap44xx_l4_abe_hwmod,
4164 .clk = "ocp_abe_iclk",
4165 .user = OCP_USER_MPU | OCP_USER_SDMA,
4169 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4170 .master = &omap44xx_dsp_hwmod,
4171 .slave = &omap44xx_l4_abe_hwmod,
4172 .clk = "ocp_abe_iclk",
4173 .user = OCP_USER_MPU | OCP_USER_SDMA,
4176 /* l3_main_1 -> l4_abe */
4177 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4178 .master = &omap44xx_l3_main_1_hwmod,
4179 .slave = &omap44xx_l4_abe_hwmod,
4181 .user = OCP_USER_MPU | OCP_USER_SDMA,
4185 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4186 .master = &omap44xx_mpu_hwmod,
4187 .slave = &omap44xx_l4_abe_hwmod,
4188 .clk = "ocp_abe_iclk",
4189 .user = OCP_USER_MPU | OCP_USER_SDMA,
4192 /* l3_main_1 -> l4_cfg */
4193 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4194 .master = &omap44xx_l3_main_1_hwmod,
4195 .slave = &omap44xx_l4_cfg_hwmod,
4197 .user = OCP_USER_MPU | OCP_USER_SDMA,
4200 /* l3_main_2 -> l4_per */
4201 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4202 .master = &omap44xx_l3_main_2_hwmod,
4203 .slave = &omap44xx_l4_per_hwmod,
4205 .user = OCP_USER_MPU | OCP_USER_SDMA,
4208 /* l4_cfg -> l4_wkup */
4209 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4210 .master = &omap44xx_l4_cfg_hwmod,
4211 .slave = &omap44xx_l4_wkup_hwmod,
4213 .user = OCP_USER_MPU | OCP_USER_SDMA,
4216 /* mpu -> mpu_private */
4217 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4218 .master = &omap44xx_mpu_hwmod,
4219 .slave = &omap44xx_mpu_private_hwmod,
4221 .user = OCP_USER_MPU | OCP_USER_SDMA,
4224 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4226 .pa_start = 0x4a102000,
4227 .pa_end = 0x4a10207f,
4228 .flags = ADDR_TYPE_RT
4233 /* l4_cfg -> ocp_wp_noc */
4234 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4235 .master = &omap44xx_l4_cfg_hwmod,
4236 .slave = &omap44xx_ocp_wp_noc_hwmod,
4238 .addr = omap44xx_ocp_wp_noc_addrs,
4239 .user = OCP_USER_MPU | OCP_USER_SDMA,
4242 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4244 .pa_start = 0x401f1000,
4245 .pa_end = 0x401f13ff,
4246 .flags = ADDR_TYPE_RT
4251 /* l4_abe -> aess */
4252 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4253 .master = &omap44xx_l4_abe_hwmod,
4254 .slave = &omap44xx_aess_hwmod,
4255 .clk = "ocp_abe_iclk",
4256 .addr = omap44xx_aess_addrs,
4257 .user = OCP_USER_MPU,
4260 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4262 .pa_start = 0x490f1000,
4263 .pa_end = 0x490f13ff,
4264 .flags = ADDR_TYPE_RT
4269 /* l4_abe -> aess (dma) */
4270 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4271 .master = &omap44xx_l4_abe_hwmod,
4272 .slave = &omap44xx_aess_hwmod,
4273 .clk = "ocp_abe_iclk",
4274 .addr = omap44xx_aess_dma_addrs,
4275 .user = OCP_USER_SDMA,
4278 /* l3_main_2 -> c2c */
4279 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4280 .master = &omap44xx_l3_main_2_hwmod,
4281 .slave = &omap44xx_c2c_hwmod,
4283 .user = OCP_USER_MPU | OCP_USER_SDMA,
4286 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4288 .pa_start = 0x4a304000,
4289 .pa_end = 0x4a30401f,
4290 .flags = ADDR_TYPE_RT
4295 /* l4_wkup -> counter_32k */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4297 .master = &omap44xx_l4_wkup_hwmod,
4298 .slave = &omap44xx_counter_32k_hwmod,
4299 .clk = "l4_wkup_clk_mux_ck",
4300 .addr = omap44xx_counter_32k_addrs,
4301 .user = OCP_USER_MPU | OCP_USER_SDMA,
4304 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4306 .pa_start = 0x4a002000,
4307 .pa_end = 0x4a0027ff,
4308 .flags = ADDR_TYPE_RT
4313 /* l4_cfg -> ctrl_module_core */
4314 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4315 .master = &omap44xx_l4_cfg_hwmod,
4316 .slave = &omap44xx_ctrl_module_core_hwmod,
4318 .addr = omap44xx_ctrl_module_core_addrs,
4319 .user = OCP_USER_MPU | OCP_USER_SDMA,
4322 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4324 .pa_start = 0x4a100000,
4325 .pa_end = 0x4a1007ff,
4326 .flags = ADDR_TYPE_RT
4331 /* l4_cfg -> ctrl_module_pad_core */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4333 .master = &omap44xx_l4_cfg_hwmod,
4334 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4336 .addr = omap44xx_ctrl_module_pad_core_addrs,
4337 .user = OCP_USER_MPU | OCP_USER_SDMA,
4340 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4342 .pa_start = 0x4a30c000,
4343 .pa_end = 0x4a30c7ff,
4344 .flags = ADDR_TYPE_RT
4349 /* l4_wkup -> ctrl_module_wkup */
4350 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4351 .master = &omap44xx_l4_wkup_hwmod,
4352 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4353 .clk = "l4_wkup_clk_mux_ck",
4354 .addr = omap44xx_ctrl_module_wkup_addrs,
4355 .user = OCP_USER_MPU | OCP_USER_SDMA,
4358 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4360 .pa_start = 0x4a31e000,
4361 .pa_end = 0x4a31e7ff,
4362 .flags = ADDR_TYPE_RT
4367 /* l4_wkup -> ctrl_module_pad_wkup */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4369 .master = &omap44xx_l4_wkup_hwmod,
4370 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4371 .clk = "l4_wkup_clk_mux_ck",
4372 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4373 .user = OCP_USER_MPU | OCP_USER_SDMA,
4376 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4378 .pa_start = 0x54160000,
4379 .pa_end = 0x54167fff,
4380 .flags = ADDR_TYPE_RT
4385 /* l3_instr -> debugss */
4386 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4387 .master = &omap44xx_l3_instr_hwmod,
4388 .slave = &omap44xx_debugss_hwmod,
4390 .addr = omap44xx_debugss_addrs,
4391 .user = OCP_USER_MPU | OCP_USER_SDMA,
4394 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4396 .pa_start = 0x4a056000,
4397 .pa_end = 0x4a056fff,
4398 .flags = ADDR_TYPE_RT
4403 /* l4_cfg -> dma_system */
4404 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4405 .master = &omap44xx_l4_cfg_hwmod,
4406 .slave = &omap44xx_dma_system_hwmod,
4408 .addr = omap44xx_dma_system_addrs,
4409 .user = OCP_USER_MPU | OCP_USER_SDMA,
4412 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4415 .pa_start = 0x4012e000,
4416 .pa_end = 0x4012e07f,
4417 .flags = ADDR_TYPE_RT
4422 /* l4_abe -> dmic */
4423 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4424 .master = &omap44xx_l4_abe_hwmod,
4425 .slave = &omap44xx_dmic_hwmod,
4426 .clk = "ocp_abe_iclk",
4427 .addr = omap44xx_dmic_addrs,
4428 .user = OCP_USER_MPU,
4431 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4434 .pa_start = 0x4902e000,
4435 .pa_end = 0x4902e07f,
4436 .flags = ADDR_TYPE_RT
4441 /* l4_abe -> dmic (dma) */
4442 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4443 .master = &omap44xx_l4_abe_hwmod,
4444 .slave = &omap44xx_dmic_hwmod,
4445 .clk = "ocp_abe_iclk",
4446 .addr = omap44xx_dmic_dma_addrs,
4447 .user = OCP_USER_SDMA,
4451 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4452 .master = &omap44xx_dsp_hwmod,
4453 .slave = &omap44xx_iva_hwmod,
4454 .clk = "dpll_iva_m5x2_ck",
4455 .user = OCP_USER_DSP,
4459 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4460 .master = &omap44xx_dsp_hwmod,
4461 .slave = &omap44xx_sl2if_hwmod,
4462 .clk = "dpll_iva_m5x2_ck",
4463 .user = OCP_USER_DSP,
4467 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4468 .master = &omap44xx_l4_cfg_hwmod,
4469 .slave = &omap44xx_dsp_hwmod,
4471 .user = OCP_USER_MPU | OCP_USER_SDMA,
4474 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4476 .pa_start = 0x58000000,
4477 .pa_end = 0x5800007f,
4478 .flags = ADDR_TYPE_RT
4483 /* l3_main_2 -> dss */
4484 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4485 .master = &omap44xx_l3_main_2_hwmod,
4486 .slave = &omap44xx_dss_hwmod,
4488 .addr = omap44xx_dss_dma_addrs,
4489 .user = OCP_USER_SDMA,
4492 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4494 .pa_start = 0x48040000,
4495 .pa_end = 0x4804007f,
4496 .flags = ADDR_TYPE_RT
4502 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4503 .master = &omap44xx_l4_per_hwmod,
4504 .slave = &omap44xx_dss_hwmod,
4506 .addr = omap44xx_dss_addrs,
4507 .user = OCP_USER_MPU,
4510 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4512 .pa_start = 0x58001000,
4513 .pa_end = 0x58001fff,
4514 .flags = ADDR_TYPE_RT
4519 /* l3_main_2 -> dss_dispc */
4520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4521 .master = &omap44xx_l3_main_2_hwmod,
4522 .slave = &omap44xx_dss_dispc_hwmod,
4524 .addr = omap44xx_dss_dispc_dma_addrs,
4525 .user = OCP_USER_SDMA,
4528 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4530 .pa_start = 0x48041000,
4531 .pa_end = 0x48041fff,
4532 .flags = ADDR_TYPE_RT
4537 /* l4_per -> dss_dispc */
4538 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4539 .master = &omap44xx_l4_per_hwmod,
4540 .slave = &omap44xx_dss_dispc_hwmod,
4542 .addr = omap44xx_dss_dispc_addrs,
4543 .user = OCP_USER_MPU,
4546 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4548 .pa_start = 0x58004000,
4549 .pa_end = 0x580041ff,
4550 .flags = ADDR_TYPE_RT
4555 /* l3_main_2 -> dss_dsi1 */
4556 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4557 .master = &omap44xx_l3_main_2_hwmod,
4558 .slave = &omap44xx_dss_dsi1_hwmod,
4560 .addr = omap44xx_dss_dsi1_dma_addrs,
4561 .user = OCP_USER_SDMA,
4564 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4566 .pa_start = 0x48044000,
4567 .pa_end = 0x480441ff,
4568 .flags = ADDR_TYPE_RT
4573 /* l4_per -> dss_dsi1 */
4574 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4575 .master = &omap44xx_l4_per_hwmod,
4576 .slave = &omap44xx_dss_dsi1_hwmod,
4578 .addr = omap44xx_dss_dsi1_addrs,
4579 .user = OCP_USER_MPU,
4582 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4584 .pa_start = 0x58005000,
4585 .pa_end = 0x580051ff,
4586 .flags = ADDR_TYPE_RT
4591 /* l3_main_2 -> dss_dsi2 */
4592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4593 .master = &omap44xx_l3_main_2_hwmod,
4594 .slave = &omap44xx_dss_dsi2_hwmod,
4596 .addr = omap44xx_dss_dsi2_dma_addrs,
4597 .user = OCP_USER_SDMA,
4600 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4602 .pa_start = 0x48045000,
4603 .pa_end = 0x480451ff,
4604 .flags = ADDR_TYPE_RT
4609 /* l4_per -> dss_dsi2 */
4610 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4611 .master = &omap44xx_l4_per_hwmod,
4612 .slave = &omap44xx_dss_dsi2_hwmod,
4614 .addr = omap44xx_dss_dsi2_addrs,
4615 .user = OCP_USER_MPU,
4618 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4620 .pa_start = 0x58006000,
4621 .pa_end = 0x58006fff,
4622 .flags = ADDR_TYPE_RT
4627 /* l3_main_2 -> dss_hdmi */
4628 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4629 .master = &omap44xx_l3_main_2_hwmod,
4630 .slave = &omap44xx_dss_hdmi_hwmod,
4632 .addr = omap44xx_dss_hdmi_dma_addrs,
4633 .user = OCP_USER_SDMA,
4636 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4638 .pa_start = 0x48046000,
4639 .pa_end = 0x48046fff,
4640 .flags = ADDR_TYPE_RT
4645 /* l4_per -> dss_hdmi */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4647 .master = &omap44xx_l4_per_hwmod,
4648 .slave = &omap44xx_dss_hdmi_hwmod,
4650 .addr = omap44xx_dss_hdmi_addrs,
4651 .user = OCP_USER_MPU,
4654 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4656 .pa_start = 0x58002000,
4657 .pa_end = 0x580020ff,
4658 .flags = ADDR_TYPE_RT
4663 /* l3_main_2 -> dss_rfbi */
4664 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4665 .master = &omap44xx_l3_main_2_hwmod,
4666 .slave = &omap44xx_dss_rfbi_hwmod,
4668 .addr = omap44xx_dss_rfbi_dma_addrs,
4669 .user = OCP_USER_SDMA,
4672 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4674 .pa_start = 0x48042000,
4675 .pa_end = 0x480420ff,
4676 .flags = ADDR_TYPE_RT
4681 /* l4_per -> dss_rfbi */
4682 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4683 .master = &omap44xx_l4_per_hwmod,
4684 .slave = &omap44xx_dss_rfbi_hwmod,
4686 .addr = omap44xx_dss_rfbi_addrs,
4687 .user = OCP_USER_MPU,
4690 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4692 .pa_start = 0x58003000,
4693 .pa_end = 0x580030ff,
4694 .flags = ADDR_TYPE_RT
4699 /* l3_main_2 -> dss_venc */
4700 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4701 .master = &omap44xx_l3_main_2_hwmod,
4702 .slave = &omap44xx_dss_venc_hwmod,
4704 .addr = omap44xx_dss_venc_dma_addrs,
4705 .user = OCP_USER_SDMA,
4708 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4710 .pa_start = 0x48043000,
4711 .pa_end = 0x480430ff,
4712 .flags = ADDR_TYPE_RT
4717 /* l4_per -> dss_venc */
4718 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4719 .master = &omap44xx_l4_per_hwmod,
4720 .slave = &omap44xx_dss_venc_hwmod,
4722 .addr = omap44xx_dss_venc_addrs,
4723 .user = OCP_USER_MPU,
4726 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4728 .pa_start = 0x48078000,
4729 .pa_end = 0x48078fff,
4730 .flags = ADDR_TYPE_RT
4736 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4737 .master = &omap44xx_l4_per_hwmod,
4738 .slave = &omap44xx_elm_hwmod,
4740 .addr = omap44xx_elm_addrs,
4741 .user = OCP_USER_MPU | OCP_USER_SDMA,
4744 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4746 .pa_start = 0x4c000000,
4747 .pa_end = 0x4c0000ff,
4748 .flags = ADDR_TYPE_RT
4753 /* emif_fw -> emif1 */
4754 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4755 .master = &omap44xx_emif_fw_hwmod,
4756 .slave = &omap44xx_emif1_hwmod,
4758 .addr = omap44xx_emif1_addrs,
4759 .user = OCP_USER_MPU | OCP_USER_SDMA,
4762 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4764 .pa_start = 0x4d000000,
4765 .pa_end = 0x4d0000ff,
4766 .flags = ADDR_TYPE_RT
4771 /* emif_fw -> emif2 */
4772 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4773 .master = &omap44xx_emif_fw_hwmod,
4774 .slave = &omap44xx_emif2_hwmod,
4776 .addr = omap44xx_emif2_addrs,
4777 .user = OCP_USER_MPU | OCP_USER_SDMA,
4780 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4782 .pa_start = 0x4a10a000,
4783 .pa_end = 0x4a10a1ff,
4784 .flags = ADDR_TYPE_RT
4789 /* l4_cfg -> fdif */
4790 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4791 .master = &omap44xx_l4_cfg_hwmod,
4792 .slave = &omap44xx_fdif_hwmod,
4794 .addr = omap44xx_fdif_addrs,
4795 .user = OCP_USER_MPU | OCP_USER_SDMA,
4798 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4800 .pa_start = 0x4a310000,
4801 .pa_end = 0x4a3101ff,
4802 .flags = ADDR_TYPE_RT
4807 /* l4_wkup -> gpio1 */
4808 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4809 .master = &omap44xx_l4_wkup_hwmod,
4810 .slave = &omap44xx_gpio1_hwmod,
4811 .clk = "l4_wkup_clk_mux_ck",
4812 .addr = omap44xx_gpio1_addrs,
4813 .user = OCP_USER_MPU | OCP_USER_SDMA,
4816 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4818 .pa_start = 0x48055000,
4819 .pa_end = 0x480551ff,
4820 .flags = ADDR_TYPE_RT
4825 /* l4_per -> gpio2 */
4826 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4827 .master = &omap44xx_l4_per_hwmod,
4828 .slave = &omap44xx_gpio2_hwmod,
4830 .addr = omap44xx_gpio2_addrs,
4831 .user = OCP_USER_MPU | OCP_USER_SDMA,
4834 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4836 .pa_start = 0x48057000,
4837 .pa_end = 0x480571ff,
4838 .flags = ADDR_TYPE_RT
4843 /* l4_per -> gpio3 */
4844 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4845 .master = &omap44xx_l4_per_hwmod,
4846 .slave = &omap44xx_gpio3_hwmod,
4848 .addr = omap44xx_gpio3_addrs,
4849 .user = OCP_USER_MPU | OCP_USER_SDMA,
4852 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4854 .pa_start = 0x48059000,
4855 .pa_end = 0x480591ff,
4856 .flags = ADDR_TYPE_RT
4861 /* l4_per -> gpio4 */
4862 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4863 .master = &omap44xx_l4_per_hwmod,
4864 .slave = &omap44xx_gpio4_hwmod,
4866 .addr = omap44xx_gpio4_addrs,
4867 .user = OCP_USER_MPU | OCP_USER_SDMA,
4870 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4872 .pa_start = 0x4805b000,
4873 .pa_end = 0x4805b1ff,
4874 .flags = ADDR_TYPE_RT
4879 /* l4_per -> gpio5 */
4880 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4881 .master = &omap44xx_l4_per_hwmod,
4882 .slave = &omap44xx_gpio5_hwmod,
4884 .addr = omap44xx_gpio5_addrs,
4885 .user = OCP_USER_MPU | OCP_USER_SDMA,
4888 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4890 .pa_start = 0x4805d000,
4891 .pa_end = 0x4805d1ff,
4892 .flags = ADDR_TYPE_RT
4897 /* l4_per -> gpio6 */
4898 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4899 .master = &omap44xx_l4_per_hwmod,
4900 .slave = &omap44xx_gpio6_hwmod,
4902 .addr = omap44xx_gpio6_addrs,
4903 .user = OCP_USER_MPU | OCP_USER_SDMA,
4906 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4908 .pa_start = 0x50000000,
4909 .pa_end = 0x500003ff,
4910 .flags = ADDR_TYPE_RT
4915 /* l3_main_2 -> gpmc */
4916 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4917 .master = &omap44xx_l3_main_2_hwmod,
4918 .slave = &omap44xx_gpmc_hwmod,
4920 .addr = omap44xx_gpmc_addrs,
4921 .user = OCP_USER_MPU | OCP_USER_SDMA,
4924 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4926 .pa_start = 0x56000000,
4927 .pa_end = 0x5600ffff,
4928 .flags = ADDR_TYPE_RT
4933 /* l3_main_2 -> gpu */
4934 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4935 .master = &omap44xx_l3_main_2_hwmod,
4936 .slave = &omap44xx_gpu_hwmod,
4938 .addr = omap44xx_gpu_addrs,
4939 .user = OCP_USER_MPU | OCP_USER_SDMA,
4942 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4944 .pa_start = 0x480b2000,
4945 .pa_end = 0x480b201f,
4946 .flags = ADDR_TYPE_RT
4951 /* l4_per -> hdq1w */
4952 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4953 .master = &omap44xx_l4_per_hwmod,
4954 .slave = &omap44xx_hdq1w_hwmod,
4956 .addr = omap44xx_hdq1w_addrs,
4957 .user = OCP_USER_MPU | OCP_USER_SDMA,
4960 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4962 .pa_start = 0x4a058000,
4963 .pa_end = 0x4a05bfff,
4964 .flags = ADDR_TYPE_RT
4970 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4971 .master = &omap44xx_l4_cfg_hwmod,
4972 .slave = &omap44xx_hsi_hwmod,
4974 .addr = omap44xx_hsi_addrs,
4975 .user = OCP_USER_MPU | OCP_USER_SDMA,
4978 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4980 .pa_start = 0x48070000,
4981 .pa_end = 0x480700ff,
4982 .flags = ADDR_TYPE_RT
4987 /* l4_per -> i2c1 */
4988 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4989 .master = &omap44xx_l4_per_hwmod,
4990 .slave = &omap44xx_i2c1_hwmod,
4992 .addr = omap44xx_i2c1_addrs,
4993 .user = OCP_USER_MPU | OCP_USER_SDMA,
4996 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4998 .pa_start = 0x48072000,
4999 .pa_end = 0x480720ff,
5000 .flags = ADDR_TYPE_RT
5005 /* l4_per -> i2c2 */
5006 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5007 .master = &omap44xx_l4_per_hwmod,
5008 .slave = &omap44xx_i2c2_hwmod,
5010 .addr = omap44xx_i2c2_addrs,
5011 .user = OCP_USER_MPU | OCP_USER_SDMA,
5014 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5016 .pa_start = 0x48060000,
5017 .pa_end = 0x480600ff,
5018 .flags = ADDR_TYPE_RT
5023 /* l4_per -> i2c3 */
5024 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5025 .master = &omap44xx_l4_per_hwmod,
5026 .slave = &omap44xx_i2c3_hwmod,
5028 .addr = omap44xx_i2c3_addrs,
5029 .user = OCP_USER_MPU | OCP_USER_SDMA,
5032 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5034 .pa_start = 0x48350000,
5035 .pa_end = 0x483500ff,
5036 .flags = ADDR_TYPE_RT
5041 /* l4_per -> i2c4 */
5042 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5043 .master = &omap44xx_l4_per_hwmod,
5044 .slave = &omap44xx_i2c4_hwmod,
5046 .addr = omap44xx_i2c4_addrs,
5047 .user = OCP_USER_MPU | OCP_USER_SDMA,
5050 /* l3_main_2 -> ipu */
5051 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5052 .master = &omap44xx_l3_main_2_hwmod,
5053 .slave = &omap44xx_ipu_hwmod,
5055 .user = OCP_USER_MPU | OCP_USER_SDMA,
5058 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5060 .pa_start = 0x52000000,
5061 .pa_end = 0x520000ff,
5062 .flags = ADDR_TYPE_RT
5067 /* l3_main_2 -> iss */
5068 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5069 .master = &omap44xx_l3_main_2_hwmod,
5070 .slave = &omap44xx_iss_hwmod,
5072 .addr = omap44xx_iss_addrs,
5073 .user = OCP_USER_MPU | OCP_USER_SDMA,
5077 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5078 .master = &omap44xx_iva_hwmod,
5079 .slave = &omap44xx_sl2if_hwmod,
5080 .clk = "dpll_iva_m5x2_ck",
5081 .user = OCP_USER_IVA,
5084 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5086 .pa_start = 0x5a000000,
5087 .pa_end = 0x5a07ffff,
5088 .flags = ADDR_TYPE_RT
5093 /* l3_main_2 -> iva */
5094 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5095 .master = &omap44xx_l3_main_2_hwmod,
5096 .slave = &omap44xx_iva_hwmod,
5098 .addr = omap44xx_iva_addrs,
5099 .user = OCP_USER_MPU,
5102 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5104 .pa_start = 0x4a31c000,
5105 .pa_end = 0x4a31c07f,
5106 .flags = ADDR_TYPE_RT
5111 /* l4_wkup -> kbd */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5113 .master = &omap44xx_l4_wkup_hwmod,
5114 .slave = &omap44xx_kbd_hwmod,
5115 .clk = "l4_wkup_clk_mux_ck",
5116 .addr = omap44xx_kbd_addrs,
5117 .user = OCP_USER_MPU | OCP_USER_SDMA,
5120 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5122 .pa_start = 0x4a0f4000,
5123 .pa_end = 0x4a0f41ff,
5124 .flags = ADDR_TYPE_RT
5129 /* l4_cfg -> mailbox */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5131 .master = &omap44xx_l4_cfg_hwmod,
5132 .slave = &omap44xx_mailbox_hwmod,
5134 .addr = omap44xx_mailbox_addrs,
5135 .user = OCP_USER_MPU | OCP_USER_SDMA,
5138 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5140 .pa_start = 0x40128000,
5141 .pa_end = 0x401283ff,
5142 .flags = ADDR_TYPE_RT
5147 /* l4_abe -> mcasp */
5148 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5149 .master = &omap44xx_l4_abe_hwmod,
5150 .slave = &omap44xx_mcasp_hwmod,
5151 .clk = "ocp_abe_iclk",
5152 .addr = omap44xx_mcasp_addrs,
5153 .user = OCP_USER_MPU,
5156 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5158 .pa_start = 0x49028000,
5159 .pa_end = 0x490283ff,
5160 .flags = ADDR_TYPE_RT
5165 /* l4_abe -> mcasp (dma) */
5166 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5167 .master = &omap44xx_l4_abe_hwmod,
5168 .slave = &omap44xx_mcasp_hwmod,
5169 .clk = "ocp_abe_iclk",
5170 .addr = omap44xx_mcasp_dma_addrs,
5171 .user = OCP_USER_SDMA,
5174 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5177 .pa_start = 0x40122000,
5178 .pa_end = 0x401220ff,
5179 .flags = ADDR_TYPE_RT
5184 /* l4_abe -> mcbsp1 */
5185 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5186 .master = &omap44xx_l4_abe_hwmod,
5187 .slave = &omap44xx_mcbsp1_hwmod,
5188 .clk = "ocp_abe_iclk",
5189 .addr = omap44xx_mcbsp1_addrs,
5190 .user = OCP_USER_MPU,
5193 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5196 .pa_start = 0x49022000,
5197 .pa_end = 0x490220ff,
5198 .flags = ADDR_TYPE_RT
5203 /* l4_abe -> mcbsp1 (dma) */
5204 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5205 .master = &omap44xx_l4_abe_hwmod,
5206 .slave = &omap44xx_mcbsp1_hwmod,
5207 .clk = "ocp_abe_iclk",
5208 .addr = omap44xx_mcbsp1_dma_addrs,
5209 .user = OCP_USER_SDMA,
5212 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5215 .pa_start = 0x40124000,
5216 .pa_end = 0x401240ff,
5217 .flags = ADDR_TYPE_RT
5222 /* l4_abe -> mcbsp2 */
5223 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5224 .master = &omap44xx_l4_abe_hwmod,
5225 .slave = &omap44xx_mcbsp2_hwmod,
5226 .clk = "ocp_abe_iclk",
5227 .addr = omap44xx_mcbsp2_addrs,
5228 .user = OCP_USER_MPU,
5231 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5234 .pa_start = 0x49024000,
5235 .pa_end = 0x490240ff,
5236 .flags = ADDR_TYPE_RT
5241 /* l4_abe -> mcbsp2 (dma) */
5242 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5243 .master = &omap44xx_l4_abe_hwmod,
5244 .slave = &omap44xx_mcbsp2_hwmod,
5245 .clk = "ocp_abe_iclk",
5246 .addr = omap44xx_mcbsp2_dma_addrs,
5247 .user = OCP_USER_SDMA,
5250 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5253 .pa_start = 0x40126000,
5254 .pa_end = 0x401260ff,
5255 .flags = ADDR_TYPE_RT
5260 /* l4_abe -> mcbsp3 */
5261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5262 .master = &omap44xx_l4_abe_hwmod,
5263 .slave = &omap44xx_mcbsp3_hwmod,
5264 .clk = "ocp_abe_iclk",
5265 .addr = omap44xx_mcbsp3_addrs,
5266 .user = OCP_USER_MPU,
5269 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5272 .pa_start = 0x49026000,
5273 .pa_end = 0x490260ff,
5274 .flags = ADDR_TYPE_RT
5279 /* l4_abe -> mcbsp3 (dma) */
5280 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5281 .master = &omap44xx_l4_abe_hwmod,
5282 .slave = &omap44xx_mcbsp3_hwmod,
5283 .clk = "ocp_abe_iclk",
5284 .addr = omap44xx_mcbsp3_dma_addrs,
5285 .user = OCP_USER_SDMA,
5288 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5290 .pa_start = 0x48096000,
5291 .pa_end = 0x480960ff,
5292 .flags = ADDR_TYPE_RT
5297 /* l4_per -> mcbsp4 */
5298 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5299 .master = &omap44xx_l4_per_hwmod,
5300 .slave = &omap44xx_mcbsp4_hwmod,
5302 .addr = omap44xx_mcbsp4_addrs,
5303 .user = OCP_USER_MPU | OCP_USER_SDMA,
5306 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5309 .pa_start = 0x40132000,
5310 .pa_end = 0x4013207f,
5311 .flags = ADDR_TYPE_RT
5316 /* l4_abe -> mcpdm */
5317 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5318 .master = &omap44xx_l4_abe_hwmod,
5319 .slave = &omap44xx_mcpdm_hwmod,
5320 .clk = "ocp_abe_iclk",
5321 .addr = omap44xx_mcpdm_addrs,
5322 .user = OCP_USER_MPU,
5325 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5328 .pa_start = 0x49032000,
5329 .pa_end = 0x4903207f,
5330 .flags = ADDR_TYPE_RT
5335 /* l4_abe -> mcpdm (dma) */
5336 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5337 .master = &omap44xx_l4_abe_hwmod,
5338 .slave = &omap44xx_mcpdm_hwmod,
5339 .clk = "ocp_abe_iclk",
5340 .addr = omap44xx_mcpdm_dma_addrs,
5341 .user = OCP_USER_SDMA,
5344 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5346 .pa_start = 0x48098000,
5347 .pa_end = 0x480981ff,
5348 .flags = ADDR_TYPE_RT
5353 /* l4_per -> mcspi1 */
5354 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5355 .master = &omap44xx_l4_per_hwmod,
5356 .slave = &omap44xx_mcspi1_hwmod,
5358 .addr = omap44xx_mcspi1_addrs,
5359 .user = OCP_USER_MPU | OCP_USER_SDMA,
5362 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5364 .pa_start = 0x4809a000,
5365 .pa_end = 0x4809a1ff,
5366 .flags = ADDR_TYPE_RT
5371 /* l4_per -> mcspi2 */
5372 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5373 .master = &omap44xx_l4_per_hwmod,
5374 .slave = &omap44xx_mcspi2_hwmod,
5376 .addr = omap44xx_mcspi2_addrs,
5377 .user = OCP_USER_MPU | OCP_USER_SDMA,
5380 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5382 .pa_start = 0x480b8000,
5383 .pa_end = 0x480b81ff,
5384 .flags = ADDR_TYPE_RT
5389 /* l4_per -> mcspi3 */
5390 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5391 .master = &omap44xx_l4_per_hwmod,
5392 .slave = &omap44xx_mcspi3_hwmod,
5394 .addr = omap44xx_mcspi3_addrs,
5395 .user = OCP_USER_MPU | OCP_USER_SDMA,
5398 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5400 .pa_start = 0x480ba000,
5401 .pa_end = 0x480ba1ff,
5402 .flags = ADDR_TYPE_RT
5407 /* l4_per -> mcspi4 */
5408 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5409 .master = &omap44xx_l4_per_hwmod,
5410 .slave = &omap44xx_mcspi4_hwmod,
5412 .addr = omap44xx_mcspi4_addrs,
5413 .user = OCP_USER_MPU | OCP_USER_SDMA,
5416 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5418 .pa_start = 0x4809c000,
5419 .pa_end = 0x4809c3ff,
5420 .flags = ADDR_TYPE_RT
5425 /* l4_per -> mmc1 */
5426 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5427 .master = &omap44xx_l4_per_hwmod,
5428 .slave = &omap44xx_mmc1_hwmod,
5430 .addr = omap44xx_mmc1_addrs,
5431 .user = OCP_USER_MPU | OCP_USER_SDMA,
5434 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5436 .pa_start = 0x480b4000,
5437 .pa_end = 0x480b43ff,
5438 .flags = ADDR_TYPE_RT
5443 /* l4_per -> mmc2 */
5444 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5445 .master = &omap44xx_l4_per_hwmod,
5446 .slave = &omap44xx_mmc2_hwmod,
5448 .addr = omap44xx_mmc2_addrs,
5449 .user = OCP_USER_MPU | OCP_USER_SDMA,
5452 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5454 .pa_start = 0x480ad000,
5455 .pa_end = 0x480ad3ff,
5456 .flags = ADDR_TYPE_RT
5461 /* l4_per -> mmc3 */
5462 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5463 .master = &omap44xx_l4_per_hwmod,
5464 .slave = &omap44xx_mmc3_hwmod,
5466 .addr = omap44xx_mmc3_addrs,
5467 .user = OCP_USER_MPU | OCP_USER_SDMA,
5470 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5472 .pa_start = 0x480d1000,
5473 .pa_end = 0x480d13ff,
5474 .flags = ADDR_TYPE_RT
5479 /* l4_per -> mmc4 */
5480 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5481 .master = &omap44xx_l4_per_hwmod,
5482 .slave = &omap44xx_mmc4_hwmod,
5484 .addr = omap44xx_mmc4_addrs,
5485 .user = OCP_USER_MPU | OCP_USER_SDMA,
5488 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5490 .pa_start = 0x480d5000,
5491 .pa_end = 0x480d53ff,
5492 .flags = ADDR_TYPE_RT
5497 /* l4_per -> mmc5 */
5498 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5499 .master = &omap44xx_l4_per_hwmod,
5500 .slave = &omap44xx_mmc5_hwmod,
5502 .addr = omap44xx_mmc5_addrs,
5503 .user = OCP_USER_MPU | OCP_USER_SDMA,
5506 /* l3_main_2 -> ocmc_ram */
5507 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5508 .master = &omap44xx_l3_main_2_hwmod,
5509 .slave = &omap44xx_ocmc_ram_hwmod,
5511 .user = OCP_USER_MPU | OCP_USER_SDMA,
5514 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5516 .pa_start = 0x4a0ad000,
5517 .pa_end = 0x4a0ad01f,
5518 .flags = ADDR_TYPE_RT
5523 /* l4_cfg -> ocp2scp_usb_phy */
5524 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5525 .master = &omap44xx_l4_cfg_hwmod,
5526 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5528 .addr = omap44xx_ocp2scp_usb_phy_addrs,
5529 .user = OCP_USER_MPU | OCP_USER_SDMA,
5532 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5534 .pa_start = 0x48243000,
5535 .pa_end = 0x48243fff,
5536 .flags = ADDR_TYPE_RT
5541 /* mpu_private -> prcm_mpu */
5542 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5543 .master = &omap44xx_mpu_private_hwmod,
5544 .slave = &omap44xx_prcm_mpu_hwmod,
5546 .addr = omap44xx_prcm_mpu_addrs,
5547 .user = OCP_USER_MPU | OCP_USER_SDMA,
5550 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5552 .pa_start = 0x4a004000,
5553 .pa_end = 0x4a004fff,
5554 .flags = ADDR_TYPE_RT
5559 /* l4_wkup -> cm_core_aon */
5560 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5561 .master = &omap44xx_l4_wkup_hwmod,
5562 .slave = &omap44xx_cm_core_aon_hwmod,
5563 .clk = "l4_wkup_clk_mux_ck",
5564 .addr = omap44xx_cm_core_aon_addrs,
5565 .user = OCP_USER_MPU | OCP_USER_SDMA,
5568 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5570 .pa_start = 0x4a008000,
5571 .pa_end = 0x4a009fff,
5572 .flags = ADDR_TYPE_RT
5577 /* l4_cfg -> cm_core */
5578 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5579 .master = &omap44xx_l4_cfg_hwmod,
5580 .slave = &omap44xx_cm_core_hwmod,
5582 .addr = omap44xx_cm_core_addrs,
5583 .user = OCP_USER_MPU | OCP_USER_SDMA,
5586 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5588 .pa_start = 0x4a306000,
5589 .pa_end = 0x4a307fff,
5590 .flags = ADDR_TYPE_RT
5595 /* l4_wkup -> prm */
5596 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5597 .master = &omap44xx_l4_wkup_hwmod,
5598 .slave = &omap44xx_prm_hwmod,
5599 .clk = "l4_wkup_clk_mux_ck",
5600 .addr = omap44xx_prm_addrs,
5601 .user = OCP_USER_MPU | OCP_USER_SDMA,
5604 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5606 .pa_start = 0x4a30a000,
5607 .pa_end = 0x4a30a7ff,
5608 .flags = ADDR_TYPE_RT
5613 /* l4_wkup -> scrm */
5614 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5615 .master = &omap44xx_l4_wkup_hwmod,
5616 .slave = &omap44xx_scrm_hwmod,
5617 .clk = "l4_wkup_clk_mux_ck",
5618 .addr = omap44xx_scrm_addrs,
5619 .user = OCP_USER_MPU | OCP_USER_SDMA,
5622 /* l3_main_2 -> sl2if */
5623 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5624 .master = &omap44xx_l3_main_2_hwmod,
5625 .slave = &omap44xx_sl2if_hwmod,
5627 .user = OCP_USER_MPU | OCP_USER_SDMA,
5630 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5632 .pa_start = 0x4012c000,
5633 .pa_end = 0x4012c3ff,
5634 .flags = ADDR_TYPE_RT
5639 /* l4_abe -> slimbus1 */
5640 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5641 .master = &omap44xx_l4_abe_hwmod,
5642 .slave = &omap44xx_slimbus1_hwmod,
5643 .clk = "ocp_abe_iclk",
5644 .addr = omap44xx_slimbus1_addrs,
5645 .user = OCP_USER_MPU,
5648 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5650 .pa_start = 0x4902c000,
5651 .pa_end = 0x4902c3ff,
5652 .flags = ADDR_TYPE_RT
5657 /* l4_abe -> slimbus1 (dma) */
5658 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5659 .master = &omap44xx_l4_abe_hwmod,
5660 .slave = &omap44xx_slimbus1_hwmod,
5661 .clk = "ocp_abe_iclk",
5662 .addr = omap44xx_slimbus1_dma_addrs,
5663 .user = OCP_USER_SDMA,
5666 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5668 .pa_start = 0x48076000,
5669 .pa_end = 0x480763ff,
5670 .flags = ADDR_TYPE_RT
5675 /* l4_per -> slimbus2 */
5676 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5677 .master = &omap44xx_l4_per_hwmod,
5678 .slave = &omap44xx_slimbus2_hwmod,
5680 .addr = omap44xx_slimbus2_addrs,
5681 .user = OCP_USER_MPU | OCP_USER_SDMA,
5684 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5686 .pa_start = 0x4a0dd000,
5687 .pa_end = 0x4a0dd03f,
5688 .flags = ADDR_TYPE_RT
5693 /* l4_cfg -> smartreflex_core */
5694 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5695 .master = &omap44xx_l4_cfg_hwmod,
5696 .slave = &omap44xx_smartreflex_core_hwmod,
5698 .addr = omap44xx_smartreflex_core_addrs,
5699 .user = OCP_USER_MPU | OCP_USER_SDMA,
5702 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5704 .pa_start = 0x4a0db000,
5705 .pa_end = 0x4a0db03f,
5706 .flags = ADDR_TYPE_RT
5711 /* l4_cfg -> smartreflex_iva */
5712 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5713 .master = &omap44xx_l4_cfg_hwmod,
5714 .slave = &omap44xx_smartreflex_iva_hwmod,
5716 .addr = omap44xx_smartreflex_iva_addrs,
5717 .user = OCP_USER_MPU | OCP_USER_SDMA,
5720 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5722 .pa_start = 0x4a0d9000,
5723 .pa_end = 0x4a0d903f,
5724 .flags = ADDR_TYPE_RT
5729 /* l4_cfg -> smartreflex_mpu */
5730 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5731 .master = &omap44xx_l4_cfg_hwmod,
5732 .slave = &omap44xx_smartreflex_mpu_hwmod,
5734 .addr = omap44xx_smartreflex_mpu_addrs,
5735 .user = OCP_USER_MPU | OCP_USER_SDMA,
5738 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5740 .pa_start = 0x4a0f6000,
5741 .pa_end = 0x4a0f6fff,
5742 .flags = ADDR_TYPE_RT
5747 /* l4_cfg -> spinlock */
5748 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5749 .master = &omap44xx_l4_cfg_hwmod,
5750 .slave = &omap44xx_spinlock_hwmod,
5752 .addr = omap44xx_spinlock_addrs,
5753 .user = OCP_USER_MPU | OCP_USER_SDMA,
5756 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5758 .pa_start = 0x4a318000,
5759 .pa_end = 0x4a31807f,
5760 .flags = ADDR_TYPE_RT
5765 /* l4_wkup -> timer1 */
5766 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5767 .master = &omap44xx_l4_wkup_hwmod,
5768 .slave = &omap44xx_timer1_hwmod,
5769 .clk = "l4_wkup_clk_mux_ck",
5770 .addr = omap44xx_timer1_addrs,
5771 .user = OCP_USER_MPU | OCP_USER_SDMA,
5774 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5776 .pa_start = 0x48032000,
5777 .pa_end = 0x4803207f,
5778 .flags = ADDR_TYPE_RT
5783 /* l4_per -> timer2 */
5784 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5785 .master = &omap44xx_l4_per_hwmod,
5786 .slave = &omap44xx_timer2_hwmod,
5788 .addr = omap44xx_timer2_addrs,
5789 .user = OCP_USER_MPU | OCP_USER_SDMA,
5792 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5794 .pa_start = 0x48034000,
5795 .pa_end = 0x4803407f,
5796 .flags = ADDR_TYPE_RT
5801 /* l4_per -> timer3 */
5802 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5803 .master = &omap44xx_l4_per_hwmod,
5804 .slave = &omap44xx_timer3_hwmod,
5806 .addr = omap44xx_timer3_addrs,
5807 .user = OCP_USER_MPU | OCP_USER_SDMA,
5810 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5812 .pa_start = 0x48036000,
5813 .pa_end = 0x4803607f,
5814 .flags = ADDR_TYPE_RT
5819 /* l4_per -> timer4 */
5820 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5821 .master = &omap44xx_l4_per_hwmod,
5822 .slave = &omap44xx_timer4_hwmod,
5824 .addr = omap44xx_timer4_addrs,
5825 .user = OCP_USER_MPU | OCP_USER_SDMA,
5828 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5830 .pa_start = 0x40138000,
5831 .pa_end = 0x4013807f,
5832 .flags = ADDR_TYPE_RT
5837 /* l4_abe -> timer5 */
5838 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5839 .master = &omap44xx_l4_abe_hwmod,
5840 .slave = &omap44xx_timer5_hwmod,
5841 .clk = "ocp_abe_iclk",
5842 .addr = omap44xx_timer5_addrs,
5843 .user = OCP_USER_MPU,
5846 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5848 .pa_start = 0x49038000,
5849 .pa_end = 0x4903807f,
5850 .flags = ADDR_TYPE_RT
5855 /* l4_abe -> timer5 (dma) */
5856 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5857 .master = &omap44xx_l4_abe_hwmod,
5858 .slave = &omap44xx_timer5_hwmod,
5859 .clk = "ocp_abe_iclk",
5860 .addr = omap44xx_timer5_dma_addrs,
5861 .user = OCP_USER_SDMA,
5864 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5866 .pa_start = 0x4013a000,
5867 .pa_end = 0x4013a07f,
5868 .flags = ADDR_TYPE_RT
5873 /* l4_abe -> timer6 */
5874 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5875 .master = &omap44xx_l4_abe_hwmod,
5876 .slave = &omap44xx_timer6_hwmod,
5877 .clk = "ocp_abe_iclk",
5878 .addr = omap44xx_timer6_addrs,
5879 .user = OCP_USER_MPU,
5882 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5884 .pa_start = 0x4903a000,
5885 .pa_end = 0x4903a07f,
5886 .flags = ADDR_TYPE_RT
5891 /* l4_abe -> timer6 (dma) */
5892 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5893 .master = &omap44xx_l4_abe_hwmod,
5894 .slave = &omap44xx_timer6_hwmod,
5895 .clk = "ocp_abe_iclk",
5896 .addr = omap44xx_timer6_dma_addrs,
5897 .user = OCP_USER_SDMA,
5900 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5902 .pa_start = 0x4013c000,
5903 .pa_end = 0x4013c07f,
5904 .flags = ADDR_TYPE_RT
5909 /* l4_abe -> timer7 */
5910 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5911 .master = &omap44xx_l4_abe_hwmod,
5912 .slave = &omap44xx_timer7_hwmod,
5913 .clk = "ocp_abe_iclk",
5914 .addr = omap44xx_timer7_addrs,
5915 .user = OCP_USER_MPU,
5918 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5920 .pa_start = 0x4903c000,
5921 .pa_end = 0x4903c07f,
5922 .flags = ADDR_TYPE_RT
5927 /* l4_abe -> timer7 (dma) */
5928 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5929 .master = &omap44xx_l4_abe_hwmod,
5930 .slave = &omap44xx_timer7_hwmod,
5931 .clk = "ocp_abe_iclk",
5932 .addr = omap44xx_timer7_dma_addrs,
5933 .user = OCP_USER_SDMA,
5936 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5938 .pa_start = 0x4013e000,
5939 .pa_end = 0x4013e07f,
5940 .flags = ADDR_TYPE_RT
5945 /* l4_abe -> timer8 */
5946 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5947 .master = &omap44xx_l4_abe_hwmod,
5948 .slave = &omap44xx_timer8_hwmod,
5949 .clk = "ocp_abe_iclk",
5950 .addr = omap44xx_timer8_addrs,
5951 .user = OCP_USER_MPU,
5954 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5956 .pa_start = 0x4903e000,
5957 .pa_end = 0x4903e07f,
5958 .flags = ADDR_TYPE_RT
5963 /* l4_abe -> timer8 (dma) */
5964 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5965 .master = &omap44xx_l4_abe_hwmod,
5966 .slave = &omap44xx_timer8_hwmod,
5967 .clk = "ocp_abe_iclk",
5968 .addr = omap44xx_timer8_dma_addrs,
5969 .user = OCP_USER_SDMA,
5972 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5974 .pa_start = 0x4803e000,
5975 .pa_end = 0x4803e07f,
5976 .flags = ADDR_TYPE_RT
5981 /* l4_per -> timer9 */
5982 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5983 .master = &omap44xx_l4_per_hwmod,
5984 .slave = &omap44xx_timer9_hwmod,
5986 .addr = omap44xx_timer9_addrs,
5987 .user = OCP_USER_MPU | OCP_USER_SDMA,
5990 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5992 .pa_start = 0x48086000,
5993 .pa_end = 0x4808607f,
5994 .flags = ADDR_TYPE_RT
5999 /* l4_per -> timer10 */
6000 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6001 .master = &omap44xx_l4_per_hwmod,
6002 .slave = &omap44xx_timer10_hwmod,
6004 .addr = omap44xx_timer10_addrs,
6005 .user = OCP_USER_MPU | OCP_USER_SDMA,
6008 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6010 .pa_start = 0x48088000,
6011 .pa_end = 0x4808807f,
6012 .flags = ADDR_TYPE_RT
6017 /* l4_per -> timer11 */
6018 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6019 .master = &omap44xx_l4_per_hwmod,
6020 .slave = &omap44xx_timer11_hwmod,
6022 .addr = omap44xx_timer11_addrs,
6023 .user = OCP_USER_MPU | OCP_USER_SDMA,
6026 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6028 .pa_start = 0x4806a000,
6029 .pa_end = 0x4806a0ff,
6030 .flags = ADDR_TYPE_RT
6035 /* l4_per -> uart1 */
6036 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6037 .master = &omap44xx_l4_per_hwmod,
6038 .slave = &omap44xx_uart1_hwmod,
6040 .addr = omap44xx_uart1_addrs,
6041 .user = OCP_USER_MPU | OCP_USER_SDMA,
6044 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6046 .pa_start = 0x4806c000,
6047 .pa_end = 0x4806c0ff,
6048 .flags = ADDR_TYPE_RT
6053 /* l4_per -> uart2 */
6054 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6055 .master = &omap44xx_l4_per_hwmod,
6056 .slave = &omap44xx_uart2_hwmod,
6058 .addr = omap44xx_uart2_addrs,
6059 .user = OCP_USER_MPU | OCP_USER_SDMA,
6062 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6064 .pa_start = 0x48020000,
6065 .pa_end = 0x480200ff,
6066 .flags = ADDR_TYPE_RT
6071 /* l4_per -> uart3 */
6072 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6073 .master = &omap44xx_l4_per_hwmod,
6074 .slave = &omap44xx_uart3_hwmod,
6076 .addr = omap44xx_uart3_addrs,
6077 .user = OCP_USER_MPU | OCP_USER_SDMA,
6080 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6082 .pa_start = 0x4806e000,
6083 .pa_end = 0x4806e0ff,
6084 .flags = ADDR_TYPE_RT
6089 /* l4_per -> uart4 */
6090 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6091 .master = &omap44xx_l4_per_hwmod,
6092 .slave = &omap44xx_uart4_hwmod,
6094 .addr = omap44xx_uart4_addrs,
6095 .user = OCP_USER_MPU | OCP_USER_SDMA,
6098 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6100 .pa_start = 0x4a0a9000,
6101 .pa_end = 0x4a0a93ff,
6102 .flags = ADDR_TYPE_RT
6107 /* l4_cfg -> usb_host_fs */
6108 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6109 .master = &omap44xx_l4_cfg_hwmod,
6110 .slave = &omap44xx_usb_host_fs_hwmod,
6112 .addr = omap44xx_usb_host_fs_addrs,
6113 .user = OCP_USER_MPU | OCP_USER_SDMA,
6116 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6119 .pa_start = 0x4a064000,
6120 .pa_end = 0x4a0647ff,
6121 .flags = ADDR_TYPE_RT
6125 .pa_start = 0x4a064800,
6126 .pa_end = 0x4a064bff,
6130 .pa_start = 0x4a064c00,
6131 .pa_end = 0x4a064fff,
6136 /* l4_cfg -> usb_host_hs */
6137 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6138 .master = &omap44xx_l4_cfg_hwmod,
6139 .slave = &omap44xx_usb_host_hs_hwmod,
6141 .addr = omap44xx_usb_host_hs_addrs,
6142 .user = OCP_USER_MPU | OCP_USER_SDMA,
6145 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6147 .pa_start = 0x4a0ab000,
6148 .pa_end = 0x4a0ab7ff,
6149 .flags = ADDR_TYPE_RT
6152 /* XXX: Remove this once control module driver is in place */
6153 .pa_start = 0x4a00233c,
6154 .pa_end = 0x4a00233f,
6155 .flags = ADDR_TYPE_RT
6160 /* l4_cfg -> usb_otg_hs */
6161 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6162 .master = &omap44xx_l4_cfg_hwmod,
6163 .slave = &omap44xx_usb_otg_hs_hwmod,
6165 .addr = omap44xx_usb_otg_hs_addrs,
6166 .user = OCP_USER_MPU | OCP_USER_SDMA,
6169 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6172 .pa_start = 0x4a062000,
6173 .pa_end = 0x4a063fff,
6174 .flags = ADDR_TYPE_RT
6179 /* l4_cfg -> usb_tll_hs */
6180 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6181 .master = &omap44xx_l4_cfg_hwmod,
6182 .slave = &omap44xx_usb_tll_hs_hwmod,
6184 .addr = omap44xx_usb_tll_hs_addrs,
6185 .user = OCP_USER_MPU | OCP_USER_SDMA,
6188 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6190 .pa_start = 0x4a314000,
6191 .pa_end = 0x4a31407f,
6192 .flags = ADDR_TYPE_RT
6197 /* l4_wkup -> wd_timer2 */
6198 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6199 .master = &omap44xx_l4_wkup_hwmod,
6200 .slave = &omap44xx_wd_timer2_hwmod,
6201 .clk = "l4_wkup_clk_mux_ck",
6202 .addr = omap44xx_wd_timer2_addrs,
6203 .user = OCP_USER_MPU | OCP_USER_SDMA,
6206 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6208 .pa_start = 0x40130000,
6209 .pa_end = 0x4013007f,
6210 .flags = ADDR_TYPE_RT
6215 /* l4_abe -> wd_timer3 */
6216 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6217 .master = &omap44xx_l4_abe_hwmod,
6218 .slave = &omap44xx_wd_timer3_hwmod,
6219 .clk = "ocp_abe_iclk",
6220 .addr = omap44xx_wd_timer3_addrs,
6221 .user = OCP_USER_MPU,
6224 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6226 .pa_start = 0x49030000,
6227 .pa_end = 0x4903007f,
6228 .flags = ADDR_TYPE_RT
6233 /* l4_abe -> wd_timer3 (dma) */
6234 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6235 .master = &omap44xx_l4_abe_hwmod,
6236 .slave = &omap44xx_wd_timer3_hwmod,
6237 .clk = "ocp_abe_iclk",
6238 .addr = omap44xx_wd_timer3_dma_addrs,
6239 .user = OCP_USER_SDMA,
6242 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6243 &omap44xx_c2c__c2c_target_fw,
6244 &omap44xx_l4_cfg__c2c_target_fw,
6245 &omap44xx_l3_main_1__dmm,
6247 &omap44xx_c2c__emif_fw,
6248 &omap44xx_dmm__emif_fw,
6249 &omap44xx_l4_cfg__emif_fw,
6250 &omap44xx_iva__l3_instr,
6251 &omap44xx_l3_main_3__l3_instr,
6252 &omap44xx_ocp_wp_noc__l3_instr,
6253 &omap44xx_dsp__l3_main_1,
6254 &omap44xx_dss__l3_main_1,
6255 &omap44xx_l3_main_2__l3_main_1,
6256 &omap44xx_l4_cfg__l3_main_1,
6257 &omap44xx_mmc1__l3_main_1,
6258 &omap44xx_mmc2__l3_main_1,
6259 &omap44xx_mpu__l3_main_1,
6260 &omap44xx_c2c_target_fw__l3_main_2,
6261 &omap44xx_debugss__l3_main_2,
6262 &omap44xx_dma_system__l3_main_2,
6263 &omap44xx_fdif__l3_main_2,
6264 &omap44xx_gpu__l3_main_2,
6265 &omap44xx_hsi__l3_main_2,
6266 &omap44xx_ipu__l3_main_2,
6267 &omap44xx_iss__l3_main_2,
6268 &omap44xx_iva__l3_main_2,
6269 &omap44xx_l3_main_1__l3_main_2,
6270 &omap44xx_l4_cfg__l3_main_2,
6271 /* &omap44xx_usb_host_fs__l3_main_2, */
6272 &omap44xx_usb_host_hs__l3_main_2,
6273 &omap44xx_usb_otg_hs__l3_main_2,
6274 &omap44xx_l3_main_1__l3_main_3,
6275 &omap44xx_l3_main_2__l3_main_3,
6276 &omap44xx_l4_cfg__l3_main_3,
6277 /* &omap44xx_aess__l4_abe, */
6278 &omap44xx_dsp__l4_abe,
6279 &omap44xx_l3_main_1__l4_abe,
6280 &omap44xx_mpu__l4_abe,
6281 &omap44xx_l3_main_1__l4_cfg,
6282 &omap44xx_l3_main_2__l4_per,
6283 &omap44xx_l4_cfg__l4_wkup,
6284 &omap44xx_mpu__mpu_private,
6285 &omap44xx_l4_cfg__ocp_wp_noc,
6286 /* &omap44xx_l4_abe__aess, */
6287 /* &omap44xx_l4_abe__aess_dma, */
6288 &omap44xx_l3_main_2__c2c,
6289 &omap44xx_l4_wkup__counter_32k,
6290 &omap44xx_l4_cfg__ctrl_module_core,
6291 &omap44xx_l4_cfg__ctrl_module_pad_core,
6292 &omap44xx_l4_wkup__ctrl_module_wkup,
6293 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6294 &omap44xx_l3_instr__debugss,
6295 &omap44xx_l4_cfg__dma_system,
6296 &omap44xx_l4_abe__dmic,
6297 &omap44xx_l4_abe__dmic_dma,
6299 /* &omap44xx_dsp__sl2if, */
6300 &omap44xx_l4_cfg__dsp,
6301 &omap44xx_l3_main_2__dss,
6302 &omap44xx_l4_per__dss,
6303 &omap44xx_l3_main_2__dss_dispc,
6304 &omap44xx_l4_per__dss_dispc,
6305 &omap44xx_l3_main_2__dss_dsi1,
6306 &omap44xx_l4_per__dss_dsi1,
6307 &omap44xx_l3_main_2__dss_dsi2,
6308 &omap44xx_l4_per__dss_dsi2,
6309 &omap44xx_l3_main_2__dss_hdmi,
6310 &omap44xx_l4_per__dss_hdmi,
6311 &omap44xx_l3_main_2__dss_rfbi,
6312 &omap44xx_l4_per__dss_rfbi,
6313 &omap44xx_l3_main_2__dss_venc,
6314 &omap44xx_l4_per__dss_venc,
6315 &omap44xx_l4_per__elm,
6316 &omap44xx_emif_fw__emif1,
6317 &omap44xx_emif_fw__emif2,
6318 &omap44xx_l4_cfg__fdif,
6319 &omap44xx_l4_wkup__gpio1,
6320 &omap44xx_l4_per__gpio2,
6321 &omap44xx_l4_per__gpio3,
6322 &omap44xx_l4_per__gpio4,
6323 &omap44xx_l4_per__gpio5,
6324 &omap44xx_l4_per__gpio6,
6325 &omap44xx_l3_main_2__gpmc,
6326 &omap44xx_l3_main_2__gpu,
6327 &omap44xx_l4_per__hdq1w,
6328 &omap44xx_l4_cfg__hsi,
6329 &omap44xx_l4_per__i2c1,
6330 &omap44xx_l4_per__i2c2,
6331 &omap44xx_l4_per__i2c3,
6332 &omap44xx_l4_per__i2c4,
6333 &omap44xx_l3_main_2__ipu,
6334 &omap44xx_l3_main_2__iss,
6335 /* &omap44xx_iva__sl2if, */
6336 &omap44xx_l3_main_2__iva,
6337 &omap44xx_l4_wkup__kbd,
6338 &omap44xx_l4_cfg__mailbox,
6339 &omap44xx_l4_abe__mcasp,
6340 &omap44xx_l4_abe__mcasp_dma,
6341 &omap44xx_l4_abe__mcbsp1,
6342 &omap44xx_l4_abe__mcbsp1_dma,
6343 &omap44xx_l4_abe__mcbsp2,
6344 &omap44xx_l4_abe__mcbsp2_dma,
6345 &omap44xx_l4_abe__mcbsp3,
6346 &omap44xx_l4_abe__mcbsp3_dma,
6347 &omap44xx_l4_per__mcbsp4,
6348 &omap44xx_l4_abe__mcpdm,
6349 &omap44xx_l4_abe__mcpdm_dma,
6350 &omap44xx_l4_per__mcspi1,
6351 &omap44xx_l4_per__mcspi2,
6352 &omap44xx_l4_per__mcspi3,
6353 &omap44xx_l4_per__mcspi4,
6354 &omap44xx_l4_per__mmc1,
6355 &omap44xx_l4_per__mmc2,
6356 &omap44xx_l4_per__mmc3,
6357 &omap44xx_l4_per__mmc4,
6358 &omap44xx_l4_per__mmc5,
6359 &omap44xx_l3_main_2__mmu_ipu,
6360 &omap44xx_l4_cfg__mmu_dsp,
6361 &omap44xx_l3_main_2__ocmc_ram,
6362 &omap44xx_l4_cfg__ocp2scp_usb_phy,
6363 &omap44xx_mpu_private__prcm_mpu,
6364 &omap44xx_l4_wkup__cm_core_aon,
6365 &omap44xx_l4_cfg__cm_core,
6366 &omap44xx_l4_wkup__prm,
6367 &omap44xx_l4_wkup__scrm,
6368 /* &omap44xx_l3_main_2__sl2if, */
6369 &omap44xx_l4_abe__slimbus1,
6370 &omap44xx_l4_abe__slimbus1_dma,
6371 &omap44xx_l4_per__slimbus2,
6372 &omap44xx_l4_cfg__smartreflex_core,
6373 &omap44xx_l4_cfg__smartreflex_iva,
6374 &omap44xx_l4_cfg__smartreflex_mpu,
6375 &omap44xx_l4_cfg__spinlock,
6376 &omap44xx_l4_wkup__timer1,
6377 &omap44xx_l4_per__timer2,
6378 &omap44xx_l4_per__timer3,
6379 &omap44xx_l4_per__timer4,
6380 &omap44xx_l4_abe__timer5,
6381 &omap44xx_l4_abe__timer5_dma,
6382 &omap44xx_l4_abe__timer6,
6383 &omap44xx_l4_abe__timer6_dma,
6384 &omap44xx_l4_abe__timer7,
6385 &omap44xx_l4_abe__timer7_dma,
6386 &omap44xx_l4_abe__timer8,
6387 &omap44xx_l4_abe__timer8_dma,
6388 &omap44xx_l4_per__timer9,
6389 &omap44xx_l4_per__timer10,
6390 &omap44xx_l4_per__timer11,
6391 &omap44xx_l4_per__uart1,
6392 &omap44xx_l4_per__uart2,
6393 &omap44xx_l4_per__uart3,
6394 &omap44xx_l4_per__uart4,
6395 /* &omap44xx_l4_cfg__usb_host_fs, */
6396 &omap44xx_l4_cfg__usb_host_hs,
6397 &omap44xx_l4_cfg__usb_otg_hs,
6398 &omap44xx_l4_cfg__usb_tll_hs,
6399 &omap44xx_l4_wkup__wd_timer2,
6400 &omap44xx_l4_abe__wd_timer3,
6401 &omap44xx_l4_abe__wd_timer3_dma,
6405 int __init omap44xx_hwmod_init(void)
6408 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);