arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 /*
   2  * Hardware modules present on the DRA7xx chips
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Paul Walmsley
   7  * Benoit Cousson
   8  *
   9  * This file is automatically generated from the OMAP hardware databases.
  10  * We respectfully ask that any modifications to this file be coordinated
  11  * with the public linux-omap@vger.kernel.org mailing list and the
  12  * authors above to ensure that the autogeneration scripts are kept
  13  * up-to-date with the file contents.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/io.h>
  21 #include <linux/platform_data/gpio-omap.h>
  22 #include <linux/platform_data/hsmmc-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/i2c-omap.h>
  25
  26 #include <linux/omap-dma.h>
  27 #include <linux/platform_data/spi-omap2-mcspi.h>
  28 #include <linux/platform_data/asoc-ti-mcbsp.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod.h"
  32 #include "omap_hwmod_common_data.h"
  33 #include "cm1_7xx.h"
  34 #include "cm2_7xx.h"
  35 #include "prm7xx.h"
  36 #include "i2c.h"
  37 #include "wd_timer.h"
  38 #include "soc.h"
  39
  40 /* Base offset for all DRA7XX interrupts external to MPUSS */
  41 #define DRA7XX_IRQ_GIC_START    32
  42
  43 /* Base offset for all DRA7XX dma requests */
  44 #define DRA7XX_DMA_REQ_START    1
  45
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /*
  52  * 'l3' class
  53  * instance(s): l3_instr, l3_main_1, l3_main_2
  54  */
  55 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  56         .name   = "l3",
  57 };
  58
  59 /* l3_instr */
  60 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  61         .name           = "l3_instr",
  62         .class          = &dra7xx_l3_hwmod_class,
  63         .clkdm_name     = "l3instr_clkdm",
  64         .prcm = {
  65                 .omap4 = {
  66                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  67                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  68                         .modulemode   = MODULEMODE_HWCTRL,
  69                 },
  70         },
  71 };
  72
  73 /* l3_main_1 */
  74 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  75         .name           = "l3_main_1",
  76         .class          = &dra7xx_l3_hwmod_class,
  77         .clkdm_name     = "l3main1_clkdm",
  78         .prcm = {
  79                 .omap4 = {
  80                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  81                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  82                 },
  83         },
  84 };
  85
  86 /* l3_main_2 */
  87 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  88         .name           = "l3_main_2",
  89         .class          = &dra7xx_l3_hwmod_class,
  90         .clkdm_name     = "l3instr_clkdm",
  91         .prcm = {
  92                 .omap4 = {
  93                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
  94                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
  95                         .modulemode   = MODULEMODE_HWCTRL,
  96                 },
  97         },
  98 };
  99
 100 /*
 101  * 'l4' class
 102  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 103  */
 104 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 105         .name   = "l4",
 106 };
 107
 108 /* l4_cfg */
 109 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 110         .name           = "l4_cfg",
 111         .class          = &dra7xx_l4_hwmod_class,
 112         .clkdm_name     = "l4cfg_clkdm",
 113         .prcm = {
 114                 .omap4 = {
 115                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 116                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 117                 },
 118         },
 119 };
 120
 121 /* l4_per1 */
 122 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 123         .name           = "l4_per1",
 124         .class          = &dra7xx_l4_hwmod_class,
 125         .clkdm_name     = "l4per_clkdm",
 126         .prcm = {
 127                 .omap4 = {
 128                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 129                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 130                 },
 131         },
 132 };
 133
 134 /* l4_per2 */
 135 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 136         .name           = "l4_per2",
 137         .class          = &dra7xx_l4_hwmod_class,
 138         .clkdm_name     = "l4per2_clkdm",
 139         .prcm = {
 140                 .omap4 = {
 141                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 142                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 143                 },
 144         },
 145 };
 146
 147 /* l4_per3 */
 148 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 149         .name           = "l4_per3",
 150         .class          = &dra7xx_l4_hwmod_class,
 151         .clkdm_name     = "l4per3_clkdm",
 152         .prcm = {
 153                 .omap4 = {
 154                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 155                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 156                 },
 157         },
 158 };
 159
 160 /* l4_wkup */
 161 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 162         .name           = "l4_wkup",
 163         .class          = &dra7xx_l4_hwmod_class,
 164         .clkdm_name     = "wkupaon_clkdm",
 165         .prcm = {
 166                 .omap4 = {
 167                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 168                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 169                 },
 170         },
 171 };
 172
 173 /*
 174  * 'atl' class
 175  *
 176  */
 177
 178 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 179         .name   = "atl",
 180 };
 181
 182 /* atl */
 183 static struct omap_hwmod dra7xx_atl_hwmod = {
 184         .name           = "atl",
 185         .class          = &dra7xx_atl_hwmod_class,
 186         .clkdm_name     = "atl_clkdm",
 187         .main_clk       = "atl_gfclk_mux",
 188         .prcm = {
 189                 .omap4 = {
 190                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 191                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 192                         .modulemode   = MODULEMODE_SWCTRL,
 193                 },
 194         },
 195 };
 196
 197 /*
 198  * 'bb2d' class
 199  *
 200  */
 201
 202 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 203         .name   = "bb2d",
 204 };
 205
 206 /* bb2d */
 207 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 208         .name           = "bb2d",
 209         .class          = &dra7xx_bb2d_hwmod_class,
 210         .clkdm_name     = "dss_clkdm",
 211         .main_clk       = "dpll_core_h24x2_ck",
 212         .prcm = {
 213                 .omap4 = {
 214                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 215                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 216                         .modulemode   = MODULEMODE_SWCTRL,
 217                 },
 218         },
 219 };
 220
 221 /*
 222  * 'counter' class
 223  *
 224  */
 225
 226 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
 227         .rev_offs       = 0x0000,
 228         .sysc_offs      = 0x0010,
 229         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 230         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 231                            SIDLE_SMART_WKUP),
 232         .sysc_fields    = &omap_hwmod_sysc_type1,
 233 };
 234
 235 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
 236         .name   = "counter",
 237         .sysc   = &dra7xx_counter_sysc,
 238 };
 239
 240 /* counter_32k */
 241 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
 242         .name           = "counter_32k",
 243         .class          = &dra7xx_counter_hwmod_class,
 244         .clkdm_name     = "wkupaon_clkdm",
 245         .flags          = HWMOD_SWSUP_SIDLE,
 246         .main_clk       = "wkupaon_iclk_mux",
 247         .prcm = {
 248                 .omap4 = {
 249                         .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
 250                         .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
 251                 },
 252         },
 253 };
 254
 255 /*
 256  * 'ctrl_module' class
 257  *
 258  */
 259
 260 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 261         .name   = "ctrl_module",
 262 };
 263
 264 /* ctrl_module_wkup */
 265 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 266         .name           = "ctrl_module_wkup",
 267         .class          = &dra7xx_ctrl_module_hwmod_class,
 268         .clkdm_name     = "wkupaon_clkdm",
 269         .prcm = {
 270                 .omap4 = {
 271                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 272                 },
 273         },
 274 };
 275
 276 /*
 277  * 'gmac' class
 278  * cpsw/gmac sub system
 279  */
 280 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
 281         .rev_offs       = 0x0,
 282         .sysc_offs      = 0x8,
 283         .syss_offs      = 0x4,
 284         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 285                            SYSS_HAS_RESET_STATUS),
 286         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 287                            MSTANDBY_NO),
 288         .sysc_fields    = &omap_hwmod_sysc_type3,
 289 };
 290
 291 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
 292         .name           = "gmac",
 293         .sysc           = &dra7xx_gmac_sysc,
 294 };
 295
 296 static struct omap_hwmod dra7xx_gmac_hwmod = {
 297         .name           = "gmac",
 298         .class          = &dra7xx_gmac_hwmod_class,
 299         .clkdm_name     = "gmac_clkdm",
 300         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 301         .main_clk       = "dpll_gmac_ck",
 302         .mpu_rt_idx     = 1,
 303         .prcm           = {
 304                 .omap4  = {
 305                         .clkctrl_offs   = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
 306                         .context_offs   = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
 307                         .modulemode     = MODULEMODE_SWCTRL,
 308                 },
 309         },
 310 };
 311
 312 /*
 313  * 'mdio' class
 314  */
 315 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
 316         .name           = "davinci_mdio",
 317 };
 318
 319 static struct omap_hwmod dra7xx_mdio_hwmod = {
 320         .name           = "davinci_mdio",
 321         .class          = &dra7xx_mdio_hwmod_class,
 322         .clkdm_name     = "gmac_clkdm",
 323         .main_clk       = "dpll_gmac_ck",
 324 };
 325
 326 /*
 327  * 'dcan' class
 328  *
 329  */
 330
 331 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
 332         .name   = "dcan",
 333 };
 334
 335 /* dcan1 */
 336 static struct omap_hwmod dra7xx_dcan1_hwmod = {
 337         .name           = "dcan1",
 338         .class          = &dra7xx_dcan_hwmod_class,
 339         .clkdm_name     = "wkupaon_clkdm",
 340         .main_clk       = "dcan1_sys_clk_mux",
 341         .prcm = {
 342                 .omap4 = {
 343                         .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
 344                         .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
 345                         .modulemode   = MODULEMODE_SWCTRL,
 346                 },
 347         },
 348 };
 349
 350 /* dcan2 */
 351 static struct omap_hwmod dra7xx_dcan2_hwmod = {
 352         .name           = "dcan2",
 353         .class          = &dra7xx_dcan_hwmod_class,
 354         .clkdm_name     = "l4per2_clkdm",
 355         .main_clk       = "sys_clkin1",
 356         .prcm = {
 357                 .omap4 = {
 358                         .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
 359                         .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
 360                         .modulemode   = MODULEMODE_SWCTRL,
 361                 },
 362         },
 363 };
 364
 365 /*
 366  * 'dma' class
 367  *
 368  */
 369
 370 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
 371         .rev_offs       = 0x0000,
 372         .sysc_offs      = 0x002c,
 373         .syss_offs      = 0x0028,
 374         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 375                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 376                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 377                            SYSS_HAS_RESET_STATUS),
 378         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 379                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 380                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 381         .sysc_fields    = &omap_hwmod_sysc_type1,
 382 };
 383
 384 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
 385         .name   = "dma",
 386         .sysc   = &dra7xx_dma_sysc,
 387 };
 388
 389 /* dma dev_attr */
 390 static struct omap_dma_dev_attr dma_dev_attr = {
 391         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 392                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 393         .lch_count      = 32,
 394 };
 395
 396 /* dma_system */
 397 static struct omap_hwmod dra7xx_dma_system_hwmod = {
 398         .name           = "dma_system",
 399         .class          = &dra7xx_dma_hwmod_class,
 400         .clkdm_name     = "dma_clkdm",
 401         .main_clk       = "l3_iclk_div",
 402         .prcm = {
 403                 .omap4 = {
 404                         .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
 405                         .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
 406                 },
 407         },
 408         .dev_attr       = &dma_dev_attr,
 409 };
 410
 411 /*
 412  * 'dss' class
 413  *
 414  */
 415
 416 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
 417         .rev_offs       = 0x0000,
 418         .syss_offs      = 0x0014,
 419         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 420 };
 421
 422 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
 423         .name   = "dss",
 424         .sysc   = &dra7xx_dss_sysc,
 425         .reset  = omap_dss_reset,
 426 };
 427
 428 /* dss */
 429 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
 430         { .dma_req = 75 + DRA7XX_DMA_REQ_START },
 431         { .dma_req = -1 }
 432 };
 433
 434 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 435         { .role = "dss_clk", .clk = "dss_dss_clk" },
 436         { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
 437         { .role = "32khz_clk", .clk = "dss_32khz_clk" },
 438         { .role = "video2_clk", .clk = "dss_video2_clk" },
 439         { .role = "video1_clk", .clk = "dss_video1_clk" },
 440         { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
 441 };
 442
 443 static struct omap_hwmod dra7xx_dss_hwmod = {
 444         .name           = "dss_core",
 445         .class          = &dra7xx_dss_hwmod_class,
 446         .clkdm_name     = "dss_clkdm",
 447         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 448         .sdma_reqs      = dra7xx_dss_sdma_reqs,
 449         .main_clk       = "dss_dss_clk",
 450         .prcm = {
 451                 .omap4 = {
 452                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 453                         .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
 454                         .modulemode   = MODULEMODE_SWCTRL,
 455                 },
 456         },
 457         .opt_clks       = dss_opt_clks,
 458         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 459 };
 460
 461 /*
 462  * 'dispc' class
 463  * display controller
 464  */
 465
 466 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
 467         .rev_offs       = 0x0000,
 468         .sysc_offs      = 0x0010,
 469         .syss_offs      = 0x0014,
 470         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 471                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 472                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 473                            SYSS_HAS_RESET_STATUS),
 474         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 475                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 476         .sysc_fields    = &omap_hwmod_sysc_type1,
 477 };
 478
 479 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
 480         .name   = "dispc",
 481         .sysc   = &dra7xx_dispc_sysc,
 482 };
 483
 484 /* dss_dispc */
 485 /* dss_dispc dev_attr */
 486 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
 487         .has_framedonetv_irq    = 1,
 488         .manager_count          = 4,
 489 };
 490
 491 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
 492         .name           = "dss_dispc",
 493         .class          = &dra7xx_dispc_hwmod_class,
 494         .clkdm_name     = "dss_clkdm",
 495         .main_clk       = "dss_dss_clk",
 496         .prcm = {
 497                 .omap4 = {
 498                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 500                 },
 501         },
 502         .dev_attr       = &dss_dispc_dev_attr,
 503 };
 504
 505 /*
 506  * 'hdmi' class
 507  * hdmi controller
 508  */
 509
 510 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
 511         .rev_offs       = 0x0000,
 512         .sysc_offs      = 0x0010,
 513         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 514                            SYSC_HAS_SOFTRESET),
 515         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 516                            SIDLE_SMART_WKUP),
 517         .sysc_fields    = &omap_hwmod_sysc_type2,
 518 };
 519
 520 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
 521         .name   = "hdmi",
 522         .sysc   = &dra7xx_hdmi_sysc,
 523 };
 524
 525 /* dss_hdmi */
 526
 527 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 528         { .role = "sys_clk", .clk = "dss_hdmi_clk" },
 529 };
 530
 531 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
 532         .name           = "dss_hdmi",
 533         .class          = &dra7xx_hdmi_hwmod_class,
 534         .clkdm_name     = "dss_clkdm",
 535         .main_clk       = "dss_48mhz_clk",
 536         .prcm = {
 537                 .omap4 = {
 538                         .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
 539                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 540                 },
 541         },
 542         .opt_clks       = dss_hdmi_opt_clks,
 543         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 544 };
 545
 546 /*
 547  * 'elm' class
 548  *
 549  */
 550
 551 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 556                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 557                            SYSS_HAS_RESET_STATUS),
 558         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 559                            SIDLE_SMART_WKUP),
 560         .sysc_fields    = &omap_hwmod_sysc_type1,
 561 };
 562
 563 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
 564         .name   = "elm",
 565         .sysc   = &dra7xx_elm_sysc,
 566 };
 567
 568 /* elm */
 569
 570 static struct omap_hwmod dra7xx_elm_hwmod = {
 571         .name           = "elm",
 572         .class          = &dra7xx_elm_hwmod_class,
 573         .clkdm_name     = "l4per_clkdm",
 574         .main_clk       = "l3_iclk_div",
 575         .prcm = {
 576                 .omap4 = {
 577                         .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
 578                         .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
 579                 },
 580         },
 581 };
 582
 583 /*
 584  * 'gpio' class
 585  *
 586  */
 587
 588 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
 589         .rev_offs       = 0x0000,
 590         .sysc_offs      = 0x0010,
 591         .syss_offs      = 0x0114,
 592         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 593                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 594                            SYSS_HAS_RESET_STATUS),
 595         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 596                            SIDLE_SMART_WKUP),
 597         .sysc_fields    = &omap_hwmod_sysc_type1,
 598 };
 599
 600 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
 601         .name   = "gpio",
 602         .sysc   = &dra7xx_gpio_sysc,
 603         .rev    = 2,
 604 };
 605
 606 /* gpio dev_attr */
 607 static struct omap_gpio_dev_attr gpio_dev_attr = {
 608         .bank_width     = 32,
 609         .dbck_flag      = true,
 610 };
 611
 612 /* gpio1 */
 613 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 614         { .role = "dbclk", .clk = "gpio1_dbclk" },
 615 };
 616
 617 static struct omap_hwmod dra7xx_gpio1_hwmod = {
 618         .name           = "gpio1",
 619         .class          = &dra7xx_gpio_hwmod_class,
 620         .clkdm_name     = "wkupaon_clkdm",
 621         .main_clk       = "wkupaon_iclk_mux",
 622         .prcm = {
 623                 .omap4 = {
 624                         .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
 625                         .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
 626                         .modulemode   = MODULEMODE_HWCTRL,
 627                 },
 628         },
 629         .opt_clks       = gpio1_opt_clks,
 630         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 631         .dev_attr       = &gpio_dev_attr,
 632 };
 633
 634 /* gpio2 */
 635 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 636         { .role = "dbclk", .clk = "gpio2_dbclk" },
 637 };
 638
 639 static struct omap_hwmod dra7xx_gpio2_hwmod = {
 640         .name           = "gpio2",
 641         .class          = &dra7xx_gpio_hwmod_class,
 642         .clkdm_name     = "l4per_clkdm",
 643         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 644         .main_clk       = "l3_iclk_div",
 645         .prcm = {
 646                 .omap4 = {
 647                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
 648                         .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
 649                         .modulemode   = MODULEMODE_HWCTRL,
 650                 },
 651         },
 652         .opt_clks       = gpio2_opt_clks,
 653         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 654         .dev_attr       = &gpio_dev_attr,
 655 };
 656
 657 /* gpio3 */
 658 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 659         { .role = "dbclk", .clk = "gpio3_dbclk" },
 660 };
 661
 662 static struct omap_hwmod dra7xx_gpio3_hwmod = {
 663         .name           = "gpio3",
 664         .class          = &dra7xx_gpio_hwmod_class,
 665         .clkdm_name     = "l4per_clkdm",
 666         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 667         .main_clk       = "l3_iclk_div",
 668         .prcm = {
 669                 .omap4 = {
 670                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
 671                         .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
 672                         .modulemode   = MODULEMODE_HWCTRL,
 673                 },
 674         },
 675         .opt_clks       = gpio3_opt_clks,
 676         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 677         .dev_attr       = &gpio_dev_attr,
 678 };
 679
 680 /* gpio4 */
 681 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 682         { .role = "dbclk", .clk = "gpio4_dbclk" },
 683 };
 684
 685 static struct omap_hwmod dra7xx_gpio4_hwmod = {
 686         .name           = "gpio4",
 687         .class          = &dra7xx_gpio_hwmod_class,
 688         .clkdm_name     = "l4per_clkdm",
 689         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 690         .main_clk       = "l3_iclk_div",
 691         .prcm = {
 692                 .omap4 = {
 693                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
 694                         .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
 695                         .modulemode   = MODULEMODE_HWCTRL,
 696                 },
 697         },
 698         .opt_clks       = gpio4_opt_clks,
 699         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 700         .dev_attr       = &gpio_dev_attr,
 701 };
 702
 703 /* gpio5 */
 704 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 705         { .role = "dbclk", .clk = "gpio5_dbclk" },
 706 };
 707
 708 static struct omap_hwmod dra7xx_gpio5_hwmod = {
 709         .name           = "gpio5",
 710         .class          = &dra7xx_gpio_hwmod_class,
 711         .clkdm_name     = "l4per_clkdm",
 712         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 713         .main_clk       = "l3_iclk_div",
 714         .prcm = {
 715                 .omap4 = {
 716                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
 717                         .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
 718                         .modulemode   = MODULEMODE_HWCTRL,
 719                 },
 720         },
 721         .opt_clks       = gpio5_opt_clks,
 722         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 723         .dev_attr       = &gpio_dev_attr,
 724 };
 725
 726 /* gpio6 */
 727 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 728         { .role = "dbclk", .clk = "gpio6_dbclk" },
 729 };
 730
 731 static struct omap_hwmod dra7xx_gpio6_hwmod = {
 732         .name           = "gpio6",
 733         .class          = &dra7xx_gpio_hwmod_class,
 734         .clkdm_name     = "l4per_clkdm",
 735         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 736         .main_clk       = "l3_iclk_div",
 737         .prcm = {
 738                 .omap4 = {
 739                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
 740                         .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
 741                         .modulemode   = MODULEMODE_HWCTRL,
 742                 },
 743         },
 744         .opt_clks       = gpio6_opt_clks,
 745         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 746         .dev_attr       = &gpio_dev_attr,
 747 };
 748
 749 /* gpio7 */
 750 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
 751         { .role = "dbclk", .clk = "gpio7_dbclk" },
 752 };
 753
 754 static struct omap_hwmod dra7xx_gpio7_hwmod = {
 755         .name           = "gpio7",
 756         .class          = &dra7xx_gpio_hwmod_class,
 757         .clkdm_name     = "l4per_clkdm",
 758         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 759         .main_clk       = "l3_iclk_div",
 760         .prcm = {
 761                 .omap4 = {
 762                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
 763                         .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
 764                         .modulemode   = MODULEMODE_HWCTRL,
 765                 },
 766         },
 767         .opt_clks       = gpio7_opt_clks,
 768         .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
 769         .dev_attr       = &gpio_dev_attr,
 770 };
 771
 772 /* gpio8 */
 773 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
 774         { .role = "dbclk", .clk = "gpio8_dbclk" },
 775 };
 776
 777 static struct omap_hwmod dra7xx_gpio8_hwmod = {
 778         .name           = "gpio8",
 779         .class          = &dra7xx_gpio_hwmod_class,
 780         .clkdm_name     = "l4per_clkdm",
 781         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 782         .main_clk       = "l3_iclk_div",
 783         .prcm = {
 784                 .omap4 = {
 785                         .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
 786                         .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
 787                         .modulemode   = MODULEMODE_HWCTRL,
 788                 },
 789         },
 790         .opt_clks       = gpio8_opt_clks,
 791         .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
 792         .dev_attr       = &gpio_dev_attr,
 793 };
 794
 795 /*
 796  * 'gpmc' class
 797  *
 798  */
 799
 800 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
 801         .rev_offs       = 0x0000,
 802         .sysc_offs      = 0x0010,
 803         .syss_offs      = 0x0014,
 804         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 805                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 806         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 807                            SIDLE_SMART_WKUP),
 808         .sysc_fields    = &omap_hwmod_sysc_type1,
 809 };
 810
 811 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
 812         .name   = "gpmc",
 813         .sysc   = &dra7xx_gpmc_sysc,
 814 };
 815
 816 /* gpmc */
 817
 818 static struct omap_hwmod dra7xx_gpmc_hwmod = {
 819         .name           = "gpmc",
 820         .class          = &dra7xx_gpmc_hwmod_class,
 821         .clkdm_name     = "l3main1_clkdm",
 822         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
 823                            HWMOD_SWSUP_SIDLE),
 824         .main_clk       = "l3_iclk_div",
 825         .prcm = {
 826                 .omap4 = {
 827                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
 828                         .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
 829                         .modulemode   = MODULEMODE_HWCTRL,
 830                 },
 831         },
 832 };
 833
 834 /*
 835  * 'hdq1w' class
 836  *
 837  */
 838
 839 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
 840         .rev_offs       = 0x0000,
 841         .sysc_offs      = 0x0014,
 842         .syss_offs      = 0x0018,
 843         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
 844                            SYSS_HAS_RESET_STATUS),
 845         .sysc_fields    = &omap_hwmod_sysc_type1,
 846 };
 847
 848 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
 849         .name   = "hdq1w",
 850         .sysc   = &dra7xx_hdq1w_sysc,
 851 };
 852
 853 /* hdq1w */
 854
 855 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
 856         .name           = "hdq1w",
 857         .class          = &dra7xx_hdq1w_hwmod_class,
 858         .clkdm_name     = "l4per_clkdm",
 859         .flags          = HWMOD_INIT_NO_RESET,
 860         .main_clk       = "func_12m_fclk",
 861         .prcm = {
 862                 .omap4 = {
 863                         .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
 864                         .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
 865                         .modulemode   = MODULEMODE_SWCTRL,
 866                 },
 867         },
 868 };
 869
 870 /*
 871  * 'i2c' class
 872  *
 873  */
 874
 875 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
 876         .sysc_offs      = 0x0010,
 877         .syss_offs      = 0x0090,
 878         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 879                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 880                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 881         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 882                            SIDLE_SMART_WKUP),
 883         .clockact       = CLOCKACT_TEST_ICLK,
 884         .sysc_fields    = &omap_hwmod_sysc_type1,
 885 };
 886
 887 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
 888         .name   = "i2c",
 889         .sysc   = &dra7xx_i2c_sysc,
 890         .reset  = &omap_i2c_reset,
 891         .rev    = OMAP_I2C_IP_VERSION_2,
 892 };
 893
 894 /* i2c dev_attr */
 895 static struct omap_i2c_dev_attr i2c_dev_attr = {
 896         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 897 };
 898
 899 /* i2c1 */
 900 static struct omap_hwmod dra7xx_i2c1_hwmod = {
 901         .name           = "i2c1",
 902         .class          = &dra7xx_i2c_hwmod_class,
 903         .clkdm_name     = "l4per_clkdm",
 904         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 905         .main_clk       = "func_96m_fclk",
 906         .prcm = {
 907                 .omap4 = {
 908                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
 909                         .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
 910                         .modulemode   = MODULEMODE_SWCTRL,
 911                 },
 912         },
 913         .dev_attr       = &i2c_dev_attr,
 914 };
 915
 916 /* i2c2 */
 917 static struct omap_hwmod dra7xx_i2c2_hwmod = {
 918         .name           = "i2c2",
 919         .class          = &dra7xx_i2c_hwmod_class,
 920         .clkdm_name     = "l4per_clkdm",
 921         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 922         .main_clk       = "func_96m_fclk",
 923         .prcm = {
 924                 .omap4 = {
 925                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
 926                         .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
 927                         .modulemode   = MODULEMODE_SWCTRL,
 928                 },
 929         },
 930         .dev_attr       = &i2c_dev_attr,
 931 };
 932
 933 /* i2c3 */
 934 static struct omap_hwmod dra7xx_i2c3_hwmod = {
 935         .name           = "i2c3",
 936         .class          = &dra7xx_i2c_hwmod_class,
 937         .clkdm_name     = "l4per_clkdm",
 938         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 939         .main_clk       = "func_96m_fclk",
 940         .prcm = {
 941                 .omap4 = {
 942                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
 943                         .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
 944                         .modulemode   = MODULEMODE_SWCTRL,
 945                 },
 946         },
 947         .dev_attr       = &i2c_dev_attr,
 948 };
 949
 950 /* i2c4 */
 951 static struct omap_hwmod dra7xx_i2c4_hwmod = {
 952         .name           = "i2c4",
 953         .class          = &dra7xx_i2c_hwmod_class,
 954         .clkdm_name     = "l4per_clkdm",
 955         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 956         .main_clk       = "func_96m_fclk",
 957         .prcm = {
 958                 .omap4 = {
 959                         .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
 960                         .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
 961                         .modulemode   = MODULEMODE_SWCTRL,
 962                 },
 963         },
 964         .dev_attr       = &i2c_dev_attr,
 965 };
 966
 967 /* i2c5 */
 968 static struct omap_hwmod dra7xx_i2c5_hwmod = {
 969         .name           = "i2c5",
 970         .class          = &dra7xx_i2c_hwmod_class,
 971         .clkdm_name     = "ipu_clkdm",
 972         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 973         .main_clk       = "func_96m_fclk",
 974         .prcm = {
 975                 .omap4 = {
 976                         .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
 977                         .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
 978                         .modulemode   = MODULEMODE_SWCTRL,
 979                 },
 980         },
 981         .dev_attr       = &i2c_dev_attr,
 982 };
 983
 984 /*
 985  * 'mailbox' class
 986  *
 987  */
 988
 989 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
 990         .rev_offs       = 0x0000,
 991         .sysc_offs      = 0x0010,
 992         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 993                            SYSC_HAS_SOFTRESET),
 994         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 995         .sysc_fields    = &omap_hwmod_sysc_type2,
 996 };
 997
 998 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
 999         .name   = "mailbox",
1000         .sysc   = &dra7xx_mailbox_sysc,
1001 };
1002
1003 /* mailbox1 */
1004 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1005         .name           = "mailbox1",
1006         .class          = &dra7xx_mailbox_hwmod_class,
1007         .clkdm_name     = "l4cfg_clkdm",
1008         .prcm = {
1009                 .omap4 = {
1010                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1011                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1012                 },
1013         },
1014 };
1015
1016 /* mailbox2 */
1017 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1018         .name           = "mailbox2",
1019         .class          = &dra7xx_mailbox_hwmod_class,
1020         .clkdm_name     = "l4cfg_clkdm",
1021         .prcm = {
1022                 .omap4 = {
1023                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1024                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1025                 },
1026         },
1027 };
1028
1029 /* mailbox3 */
1030 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1031         .name           = "mailbox3",
1032         .class          = &dra7xx_mailbox_hwmod_class,
1033         .clkdm_name     = "l4cfg_clkdm",
1034         .prcm = {
1035                 .omap4 = {
1036                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1037                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1038                 },
1039         },
1040 };
1041
1042 /* mailbox4 */
1043 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1044         .name           = "mailbox4",
1045         .class          = &dra7xx_mailbox_hwmod_class,
1046         .clkdm_name     = "l4cfg_clkdm",
1047         .prcm = {
1048                 .omap4 = {
1049                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1050                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1051                 },
1052         },
1053 };
1054
1055 /* mailbox5 */
1056 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1057         .name           = "mailbox5",
1058         .class          = &dra7xx_mailbox_hwmod_class,
1059         .clkdm_name     = "l4cfg_clkdm",
1060         .prcm = {
1061                 .omap4 = {
1062                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1063                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1064                 },
1065         },
1066 };
1067
1068 /* mailbox6 */
1069 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1070         .name           = "mailbox6",
1071         .class          = &dra7xx_mailbox_hwmod_class,
1072         .clkdm_name     = "l4cfg_clkdm",
1073         .prcm = {
1074                 .omap4 = {
1075                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1076                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1077                 },
1078         },
1079 };
1080
1081 /* mailbox7 */
1082 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1083         .name           = "mailbox7",
1084         .class          = &dra7xx_mailbox_hwmod_class,
1085         .clkdm_name     = "l4cfg_clkdm",
1086         .prcm = {
1087                 .omap4 = {
1088                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1089                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1090                 },
1091         },
1092 };
1093
1094 /* mailbox8 */
1095 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1096         .name           = "mailbox8",
1097         .class          = &dra7xx_mailbox_hwmod_class,
1098         .clkdm_name     = "l4cfg_clkdm",
1099         .prcm = {
1100                 .omap4 = {
1101                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1102                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1103                 },
1104         },
1105 };
1106
1107 /* mailbox9 */
1108 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1109         .name           = "mailbox9",
1110         .class          = &dra7xx_mailbox_hwmod_class,
1111         .clkdm_name     = "l4cfg_clkdm",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1115                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1116                 },
1117         },
1118 };
1119
1120 /* mailbox10 */
1121 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1122         .name           = "mailbox10",
1123         .class          = &dra7xx_mailbox_hwmod_class,
1124         .clkdm_name     = "l4cfg_clkdm",
1125         .prcm = {
1126                 .omap4 = {
1127                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1128                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1129                 },
1130         },
1131 };
1132
1133 /* mailbox11 */
1134 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1135         .name           = "mailbox11",
1136         .class          = &dra7xx_mailbox_hwmod_class,
1137         .clkdm_name     = "l4cfg_clkdm",
1138         .prcm = {
1139                 .omap4 = {
1140                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1141                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1142                 },
1143         },
1144 };
1145
1146 /* mailbox12 */
1147 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1148         .name           = "mailbox12",
1149         .class          = &dra7xx_mailbox_hwmod_class,
1150         .clkdm_name     = "l4cfg_clkdm",
1151         .prcm = {
1152                 .omap4 = {
1153                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1154                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1155                 },
1156         },
1157 };
1158
1159 /* mailbox13 */
1160 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1161         .name           = "mailbox13",
1162         .class          = &dra7xx_mailbox_hwmod_class,
1163         .clkdm_name     = "l4cfg_clkdm",
1164         .prcm = {
1165                 .omap4 = {
1166                         .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1167                         .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1168                 },
1169         },
1170 };
1171
1172 /*
1173  * 'mcspi' class
1174  *
1175  */
1176
1177 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1178         .rev_offs       = 0x0000,
1179         .sysc_offs      = 0x0010,
1180         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1181                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1182         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1183                            SIDLE_SMART_WKUP),
1184         .sysc_fields    = &omap_hwmod_sysc_type2,
1185 };
1186
1187 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1188         .name   = "mcspi",
1189         .sysc   = &dra7xx_mcspi_sysc,
1190         .rev    = OMAP4_MCSPI_REV,
1191 };
1192
1193 /* mcspi1 */
1194 /* mcspi1 dev_attr */
1195 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1196         .num_chipselect = 4,
1197 };
1198
1199 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1200         .name           = "mcspi1",
1201         .class          = &dra7xx_mcspi_hwmod_class,
1202         .clkdm_name     = "l4per_clkdm",
1203         .main_clk       = "func_48m_fclk",
1204         .prcm = {
1205                 .omap4 = {
1206                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1207                         .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1208                         .modulemode   = MODULEMODE_SWCTRL,
1209                 },
1210         },
1211         .dev_attr       = &mcspi1_dev_attr,
1212 };
1213
1214 /* mcspi2 */
1215 /* mcspi2 dev_attr */
1216 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1217         .num_chipselect = 2,
1218 };
1219
1220 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1221         .name           = "mcspi2",
1222         .class          = &dra7xx_mcspi_hwmod_class,
1223         .clkdm_name     = "l4per_clkdm",
1224         .main_clk       = "func_48m_fclk",
1225         .prcm = {
1226                 .omap4 = {
1227                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1228                         .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1229                         .modulemode   = MODULEMODE_SWCTRL,
1230                 },
1231         },
1232         .dev_attr       = &mcspi2_dev_attr,
1233 };
1234
1235 /* mcspi3 */
1236 /* mcspi3 dev_attr */
1237 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1238         .num_chipselect = 2,
1239 };
1240
1241 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1242         .name           = "mcspi3",
1243         .class          = &dra7xx_mcspi_hwmod_class,
1244         .clkdm_name     = "l4per_clkdm",
1245         .main_clk       = "func_48m_fclk",
1246         .prcm = {
1247                 .omap4 = {
1248                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1249                         .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1250                         .modulemode   = MODULEMODE_SWCTRL,
1251                 },
1252         },
1253         .dev_attr       = &mcspi3_dev_attr,
1254 };
1255
1256 /* mcspi4 */
1257 /* mcspi4 dev_attr */
1258 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1259         .num_chipselect = 1,
1260 };
1261
1262 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1263         .name           = "mcspi4",
1264         .class          = &dra7xx_mcspi_hwmod_class,
1265         .clkdm_name     = "l4per_clkdm",
1266         .main_clk       = "func_48m_fclk",
1267         .prcm = {
1268                 .omap4 = {
1269                         .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1270                         .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1271                         .modulemode   = MODULEMODE_SWCTRL,
1272                 },
1273         },
1274         .dev_attr       = &mcspi4_dev_attr,
1275 };
1276
1277 /*
1278  * 'mmc' class
1279  *
1280  */
1281
1282 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1283         .rev_offs       = 0x0000,
1284         .sysc_offs      = 0x0010,
1285         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1286                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1287                            SYSC_HAS_SOFTRESET),
1288         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1289                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1290                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1291         .sysc_fields    = &omap_hwmod_sysc_type2,
1292 };
1293
1294 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1295         .name   = "mmc",
1296         .sysc   = &dra7xx_mmc_sysc,
1297 };
1298
1299 /* mmc1 */
1300 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1301         { .role = "clk32k", .clk = "mmc1_clk32k" },
1302 };
1303
1304 /* mmc1 dev_attr */
1305 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1306         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1307 };
1308
1309 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1310         .name           = "mmc1",
1311         .class          = &dra7xx_mmc_hwmod_class,
1312         .clkdm_name     = "l3init_clkdm",
1313         .main_clk       = "mmc1_fclk_div",
1314         .prcm = {
1315                 .omap4 = {
1316                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1317                         .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1318                         .modulemode   = MODULEMODE_SWCTRL,
1319                 },
1320         },
1321         .opt_clks       = mmc1_opt_clks,
1322         .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
1323         .dev_attr       = &mmc1_dev_attr,
1324 };
1325
1326 /* mmc2 */
1327 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1328         { .role = "clk32k", .clk = "mmc2_clk32k" },
1329 };
1330
1331 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1332         .name           = "mmc2",
1333         .class          = &dra7xx_mmc_hwmod_class,
1334         .clkdm_name     = "l3init_clkdm",
1335         .main_clk       = "mmc2_fclk_div",
1336         .prcm = {
1337                 .omap4 = {
1338                         .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1339                         .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1340                         .modulemode   = MODULEMODE_SWCTRL,
1341                 },
1342         },
1343         .opt_clks       = mmc2_opt_clks,
1344         .opt_clks_cnt   = ARRAY_SIZE(mmc2_opt_clks),
1345 };
1346
1347 /* mmc3 */
1348 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1349         { .role = "clk32k", .clk = "mmc3_clk32k" },
1350 };
1351
1352 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1353         .name           = "mmc3",
1354         .class          = &dra7xx_mmc_hwmod_class,
1355         .clkdm_name     = "l4per_clkdm",
1356         .main_clk       = "mmc3_gfclk_div",
1357         .prcm = {
1358                 .omap4 = {
1359                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1360                         .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1361                         .modulemode   = MODULEMODE_SWCTRL,
1362                 },
1363         },
1364         .opt_clks       = mmc3_opt_clks,
1365         .opt_clks_cnt   = ARRAY_SIZE(mmc3_opt_clks),
1366 };
1367
1368 /* mmc4 */
1369 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1370         { .role = "clk32k", .clk = "mmc4_clk32k" },
1371 };
1372
1373 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1374         .name           = "mmc4",
1375         .class          = &dra7xx_mmc_hwmod_class,
1376         .clkdm_name     = "l4per_clkdm",
1377         .main_clk       = "mmc4_gfclk_div",
1378         .prcm = {
1379                 .omap4 = {
1380                         .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1381                         .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1382                         .modulemode   = MODULEMODE_SWCTRL,
1383                 },
1384         },
1385         .opt_clks       = mmc4_opt_clks,
1386         .opt_clks_cnt   = ARRAY_SIZE(mmc4_opt_clks),
1387 };
1388
1389 /*
1390  * 'mpu' class
1391  *
1392  */
1393
1394 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1395         .name   = "mpu",
1396 };
1397
1398 /* mpu */
1399 static struct omap_hwmod dra7xx_mpu_hwmod = {
1400         .name           = "mpu",
1401         .class          = &dra7xx_mpu_hwmod_class,
1402         .clkdm_name     = "mpu_clkdm",
1403         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1404         .main_clk       = "dpll_mpu_m2_ck",
1405         .prcm = {
1406                 .omap4 = {
1407                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1408                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1409                 },
1410         },
1411 };
1412
1413 /*
1414  * 'ocp2scp' class
1415  *
1416  */
1417
1418 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1419         .rev_offs       = 0x0000,
1420         .sysc_offs      = 0x0010,
1421         .syss_offs      = 0x0014,
1422         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1423                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1424         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1425                            SIDLE_SMART_WKUP),
1426         .sysc_fields    = &omap_hwmod_sysc_type1,
1427 };
1428
1429 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1430         .name   = "ocp2scp",
1431         .sysc   = &dra7xx_ocp2scp_sysc,
1432 };
1433
1434 /* ocp2scp1 */
1435 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1436         .name           = "ocp2scp1",
1437         .class          = &dra7xx_ocp2scp_hwmod_class,
1438         .clkdm_name     = "l3init_clkdm",
1439         .main_clk       = "l4_root_clk_div",
1440         .prcm = {
1441                 .omap4 = {
1442                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1443                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1444                         .modulemode   = MODULEMODE_HWCTRL,
1445                 },
1446         },
1447 };
1448
1449 /* ocp2scp3 */
1450 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1451         .name           = "ocp2scp3",
1452         .class          = &dra7xx_ocp2scp_hwmod_class,
1453         .clkdm_name     = "l3init_clkdm",
1454         .main_clk       = "l4_root_clk_div",
1455         .prcm = {
1456                 .omap4 = {
1457                         .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1458                         .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1459                         .modulemode   = MODULEMODE_HWCTRL,
1460                 },
1461         },
1462 };
1463
1464 /*
1465  * 'PCIE' class
1466  *
1467  */
1468
1469 static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
1470         .name   = "pcie",
1471 };
1472
1473 /* pcie1 */
1474 static struct omap_hwmod dra7xx_pcie1_hwmod = {
1475         .name           = "pcie1",
1476         .class          = &dra7xx_pcie_hwmod_class,
1477         .clkdm_name     = "pcie_clkdm",
1478         .main_clk       = "l4_root_clk_div",
1479         .prcm = {
1480                 .omap4 = {
1481                         .clkctrl_offs   = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1482                         .modulemode     = MODULEMODE_SWCTRL,
1483                 },
1484         },
1485 };
1486
1487 /* pcie2 */
1488 static struct omap_hwmod dra7xx_pcie2_hwmod = {
1489         .name           = "pcie2",
1490         .class          = &dra7xx_pcie_hwmod_class,
1491         .clkdm_name     = "pcie_clkdm",
1492         .main_clk       = "l4_root_clk_div",
1493         .prcm = {
1494                 .omap4 = {
1495                         .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
1496                         .modulemode   = MODULEMODE_SWCTRL,
1497                 },
1498         },
1499 };
1500
1501 /*
1502  * 'PCIE PHY' class
1503  *
1504  */
1505
1506 static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1507         .name   = "pcie-phy",
1508 };
1509
1510 /* pcie1 phy */
1511 static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1512         .name           = "pcie1-phy",
1513         .class          = &dra7xx_pcie_phy_hwmod_class,
1514         .clkdm_name     = "l3init_clkdm",
1515         .main_clk       = "l4_root_clk_div",
1516         .prcm = {
1517                 .omap4 = {
1518                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1519                         .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1520                         .modulemode   = MODULEMODE_SWCTRL,
1521                 },
1522         },
1523 };
1524
1525 /* pcie2 phy */
1526 static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1527         .name           = "pcie2-phy",
1528         .class          = &dra7xx_pcie_phy_hwmod_class,
1529         .clkdm_name     = "l3init_clkdm",
1530         .main_clk       = "l4_root_clk_div",
1531         .prcm = {
1532                 .omap4 = {
1533                         .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1534                         .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1535                         .modulemode   = MODULEMODE_SWCTRL,
1536                 },
1537         },
1538 };
1539
1540 /*
1541  * 'qspi' class
1542  *
1543  */
1544
1545 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1546         .sysc_offs      = 0x0010,
1547         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1549                            SIDLE_SMART_WKUP),
1550         .sysc_fields    = &omap_hwmod_sysc_type2,
1551 };
1552
1553 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1554         .name   = "qspi",
1555         .sysc   = &dra7xx_qspi_sysc,
1556 };
1557
1558 /* qspi */
1559 static struct omap_hwmod dra7xx_qspi_hwmod = {
1560         .name           = "qspi",
1561         .class          = &dra7xx_qspi_hwmod_class,
1562         .clkdm_name     = "l4per2_clkdm",
1563         .main_clk       = "qspi_gfclk_div",
1564         .prcm = {
1565                 .omap4 = {
1566                         .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1567                         .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1568                         .modulemode   = MODULEMODE_SWCTRL,
1569                 },
1570         },
1571 };
1572
1573 /*
1574  * 'rtcss' class
1575  *
1576  */
1577 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1578         .sysc_offs      = 0x0078,
1579         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1580         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1581                            SIDLE_SMART_WKUP),
1582         .sysc_fields    = &omap_hwmod_sysc_type3,
1583 };
1584
1585 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1586         .name   = "rtcss",
1587         .sysc   = &dra7xx_rtcss_sysc,
1588 };
1589
1590 /* rtcss */
1591 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1592         .name           = "rtcss",
1593         .class          = &dra7xx_rtcss_hwmod_class,
1594         .clkdm_name     = "rtc_clkdm",
1595         .main_clk       = "sys_32k_ck",
1596         .prcm = {
1597                 .omap4 = {
1598                         .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1599                         .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1600                         .modulemode   = MODULEMODE_SWCTRL,
1601                 },
1602         },
1603 };
1604
1605 /*
1606  * 'sata' class
1607  *
1608  */
1609
1610 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1611         .sysc_offs      = 0x0000,
1612         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1613         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1614                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1615                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1616         .sysc_fields    = &omap_hwmod_sysc_type2,
1617 };
1618
1619 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1620         .name   = "sata",
1621         .sysc   = &dra7xx_sata_sysc,
1622 };
1623
1624 /* sata */
1625
1626 static struct omap_hwmod dra7xx_sata_hwmod = {
1627         .name           = "sata",
1628         .class          = &dra7xx_sata_hwmod_class,
1629         .clkdm_name     = "l3init_clkdm",
1630         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1631         .main_clk       = "func_48m_fclk",
1632         .mpu_rt_idx     = 1,
1633         .prcm = {
1634                 .omap4 = {
1635                         .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1636                         .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1637                         .modulemode   = MODULEMODE_SWCTRL,
1638                 },
1639         },
1640 };
1641
1642 /*
1643  * 'smartreflex' class
1644  *
1645  */
1646
1647 /* The IP is not compliant to type1 / type2 scheme */
1648 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1649         .sidle_shift    = 24,
1650         .enwkup_shift   = 26,
1651 };
1652
1653 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1654         .sysc_offs      = 0x0038,
1655         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1656         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1657                            SIDLE_SMART_WKUP),
1658         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1659 };
1660
1661 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1662         .name   = "smartreflex",
1663         .sysc   = &dra7xx_smartreflex_sysc,
1664         .rev    = 2,
1665 };
1666
1667 /* smartreflex_core */
1668 /* smartreflex_core dev_attr */
1669 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1670         .sensor_voltdm_name     = "core",
1671 };
1672
1673 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1674         .name           = "smartreflex_core",
1675         .class          = &dra7xx_smartreflex_hwmod_class,
1676         .clkdm_name     = "coreaon_clkdm",
1677         .main_clk       = "wkupaon_iclk_mux",
1678         .prcm = {
1679                 .omap4 = {
1680                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1681                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1682                         .modulemode   = MODULEMODE_SWCTRL,
1683                 },
1684         },
1685         .dev_attr       = &smartreflex_core_dev_attr,
1686 };
1687
1688 /* smartreflex_mpu */
1689 /* smartreflex_mpu dev_attr */
1690 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1691         .sensor_voltdm_name     = "mpu",
1692 };
1693
1694 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1695         .name           = "smartreflex_mpu",
1696         .class          = &dra7xx_smartreflex_hwmod_class,
1697         .clkdm_name     = "coreaon_clkdm",
1698         .main_clk       = "wkupaon_iclk_mux",
1699         .prcm = {
1700                 .omap4 = {
1701                         .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1702                         .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1703                         .modulemode   = MODULEMODE_SWCTRL,
1704                 },
1705         },
1706         .dev_attr       = &smartreflex_mpu_dev_attr,
1707 };
1708
1709 /*
1710  * 'spinlock' class
1711  *
1712  */
1713
1714 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1715         .rev_offs       = 0x0000,
1716         .sysc_offs      = 0x0010,
1717         .syss_offs      = 0x0014,
1718         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1719                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1720                            SYSS_HAS_RESET_STATUS),
1721         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1722         .sysc_fields    = &omap_hwmod_sysc_type1,
1723 };
1724
1725 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1726         .name   = "spinlock",
1727         .sysc   = &dra7xx_spinlock_sysc,
1728 };
1729
1730 /* spinlock */
1731 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1732         .name           = "spinlock",
1733         .class          = &dra7xx_spinlock_hwmod_class,
1734         .clkdm_name     = "l4cfg_clkdm",
1735         .main_clk       = "l3_iclk_div",
1736         .prcm = {
1737                 .omap4 = {
1738                         .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1739                         .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1740                 },
1741         },
1742 };
1743
1744 /*
1745  * 'timer' class
1746  *
1747  * This class contains several variants: ['timer_1ms', 'timer_secure',
1748  * 'timer']
1749  */
1750
1751 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1752         .rev_offs       = 0x0000,
1753         .sysc_offs      = 0x0010,
1754         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1755                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1756         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1757                            SIDLE_SMART_WKUP),
1758         .sysc_fields    = &omap_hwmod_sysc_type2,
1759 };
1760
1761 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1762         .name   = "timer",
1763         .sysc   = &dra7xx_timer_1ms_sysc,
1764 };
1765
1766 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1767         .rev_offs       = 0x0000,
1768         .sysc_offs      = 0x0010,
1769         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1770                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1771         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1772                            SIDLE_SMART_WKUP),
1773         .sysc_fields    = &omap_hwmod_sysc_type2,
1774 };
1775
1776 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1777         .name   = "timer",
1778         .sysc   = &dra7xx_timer_secure_sysc,
1779 };
1780
1781 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1782         .rev_offs       = 0x0000,
1783         .sysc_offs      = 0x0010,
1784         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1785                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1786         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1787                            SIDLE_SMART_WKUP),
1788         .sysc_fields    = &omap_hwmod_sysc_type2,
1789 };
1790
1791 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1792         .name   = "timer",
1793         .sysc   = &dra7xx_timer_sysc,
1794 };
1795
1796 /* timer1 */
1797 static struct omap_hwmod dra7xx_timer1_hwmod = {
1798         .name           = "timer1",
1799         .class          = &dra7xx_timer_1ms_hwmod_class,
1800         .clkdm_name     = "wkupaon_clkdm",
1801         .main_clk       = "timer1_gfclk_mux",
1802         .prcm = {
1803                 .omap4 = {
1804                         .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1805                         .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1806                         .modulemode   = MODULEMODE_SWCTRL,
1807                 },
1808         },
1809 };
1810
1811 /* timer2 */
1812 static struct omap_hwmod dra7xx_timer2_hwmod = {
1813         .name           = "timer2",
1814         .class          = &dra7xx_timer_1ms_hwmod_class,
1815         .clkdm_name     = "l4per_clkdm",
1816         .main_clk       = "timer2_gfclk_mux",
1817         .prcm = {
1818                 .omap4 = {
1819                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1820                         .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1821                         .modulemode   = MODULEMODE_SWCTRL,
1822                 },
1823         },
1824 };
1825
1826 /* timer3 */
1827 static struct omap_hwmod dra7xx_timer3_hwmod = {
1828         .name           = "timer3",
1829         .class          = &dra7xx_timer_hwmod_class,
1830         .clkdm_name     = "l4per_clkdm",
1831         .main_clk       = "timer3_gfclk_mux",
1832         .prcm = {
1833                 .omap4 = {
1834                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1835                         .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1836                         .modulemode   = MODULEMODE_SWCTRL,
1837                 },
1838         },
1839 };
1840
1841 /* timer4 */
1842 static struct omap_hwmod dra7xx_timer4_hwmod = {
1843         .name           = "timer4",
1844         .class          = &dra7xx_timer_secure_hwmod_class,
1845         .clkdm_name     = "l4per_clkdm",
1846         .main_clk       = "timer4_gfclk_mux",
1847         .prcm = {
1848                 .omap4 = {
1849                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1850                         .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1851                         .modulemode   = MODULEMODE_SWCTRL,
1852                 },
1853         },
1854 };
1855
1856 /* timer5 */
1857 static struct omap_hwmod dra7xx_timer5_hwmod = {
1858         .name           = "timer5",
1859         .class          = &dra7xx_timer_hwmod_class,
1860         .clkdm_name     = "ipu_clkdm",
1861         .main_clk       = "timer5_gfclk_mux",
1862         .prcm = {
1863                 .omap4 = {
1864                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1865                         .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1866                         .modulemode   = MODULEMODE_SWCTRL,
1867                 },
1868         },
1869 };
1870
1871 /* timer6 */
1872 static struct omap_hwmod dra7xx_timer6_hwmod = {
1873         .name           = "timer6",
1874         .class          = &dra7xx_timer_hwmod_class,
1875         .clkdm_name     = "ipu_clkdm",
1876         .main_clk       = "timer6_gfclk_mux",
1877         .prcm = {
1878                 .omap4 = {
1879                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1880                         .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1881                         .modulemode   = MODULEMODE_SWCTRL,
1882                 },
1883         },
1884 };
1885
1886 /* timer7 */
1887 static struct omap_hwmod dra7xx_timer7_hwmod = {
1888         .name           = "timer7",
1889         .class          = &dra7xx_timer_hwmod_class,
1890         .clkdm_name     = "ipu_clkdm",
1891         .main_clk       = "timer7_gfclk_mux",
1892         .prcm = {
1893                 .omap4 = {
1894                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1895                         .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1896                         .modulemode   = MODULEMODE_SWCTRL,
1897                 },
1898         },
1899 };
1900
1901 /* timer8 */
1902 static struct omap_hwmod dra7xx_timer8_hwmod = {
1903         .name           = "timer8",
1904         .class          = &dra7xx_timer_hwmod_class,
1905         .clkdm_name     = "ipu_clkdm",
1906         .main_clk       = "timer8_gfclk_mux",
1907         .prcm = {
1908                 .omap4 = {
1909                         .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1910                         .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1911                         .modulemode   = MODULEMODE_SWCTRL,
1912                 },
1913         },
1914 };
1915
1916 /* timer9 */
1917 static struct omap_hwmod dra7xx_timer9_hwmod = {
1918         .name           = "timer9",
1919         .class          = &dra7xx_timer_hwmod_class,
1920         .clkdm_name     = "l4per_clkdm",
1921         .main_clk       = "timer9_gfclk_mux",
1922         .prcm = {
1923                 .omap4 = {
1924                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1925                         .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1926                         .modulemode   = MODULEMODE_SWCTRL,
1927                 },
1928         },
1929 };
1930
1931 /* timer10 */
1932 static struct omap_hwmod dra7xx_timer10_hwmod = {
1933         .name           = "timer10",
1934         .class          = &dra7xx_timer_1ms_hwmod_class,
1935         .clkdm_name     = "l4per_clkdm",
1936         .main_clk       = "timer10_gfclk_mux",
1937         .prcm = {
1938                 .omap4 = {
1939                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1940                         .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1941                         .modulemode   = MODULEMODE_SWCTRL,
1942                 },
1943         },
1944 };
1945
1946 /* timer11 */
1947 static struct omap_hwmod dra7xx_timer11_hwmod = {
1948         .name           = "timer11",
1949         .class          = &dra7xx_timer_hwmod_class,
1950         .clkdm_name     = "l4per_clkdm",
1951         .main_clk       = "timer11_gfclk_mux",
1952         .prcm = {
1953                 .omap4 = {
1954                         .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1955                         .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1956                         .modulemode   = MODULEMODE_SWCTRL,
1957                 },
1958         },
1959 };
1960
1961 /*
1962  * 'uart' class
1963  *
1964  */
1965
1966 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1967         .rev_offs       = 0x0050,
1968         .sysc_offs      = 0x0054,
1969         .syss_offs      = 0x0058,
1970         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1971                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1972                            SYSS_HAS_RESET_STATUS),
1973         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1974                            SIDLE_SMART_WKUP),
1975         .sysc_fields    = &omap_hwmod_sysc_type1,
1976 };
1977
1978 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1979         .name   = "uart",
1980         .sysc   = &dra7xx_uart_sysc,
1981 };
1982
1983 /* uart1 */
1984 static struct omap_hwmod dra7xx_uart1_hwmod = {
1985         .name           = "uart1",
1986         .class          = &dra7xx_uart_hwmod_class,
1987         .clkdm_name     = "l4per_clkdm",
1988         .main_clk       = "uart1_gfclk_mux",
1989         .flags          = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1990         .prcm = {
1991                 .omap4 = {
1992                         .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1993                         .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1994                         .modulemode   = MODULEMODE_SWCTRL,
1995                 },
1996         },
1997 };
1998
1999 /* uart2 */
2000 static struct omap_hwmod dra7xx_uart2_hwmod = {
2001         .name           = "uart2",
2002         .class          = &dra7xx_uart_hwmod_class,
2003         .clkdm_name     = "l4per_clkdm",
2004         .main_clk       = "uart2_gfclk_mux",
2005         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2006         .prcm = {
2007                 .omap4 = {
2008                         .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2009                         .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2010                         .modulemode   = MODULEMODE_SWCTRL,
2011                 },
2012         },
2013 };
2014
2015 /* uart3 */
2016 static struct omap_hwmod dra7xx_uart3_hwmod = {
2017         .name           = "uart3",
2018         .class          = &dra7xx_uart_hwmod_class,
2019         .clkdm_name     = "l4per_clkdm",
2020         .main_clk       = "uart3_gfclk_mux",
2021         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2022         .prcm = {
2023                 .omap4 = {
2024                         .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2025                         .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2026                         .modulemode   = MODULEMODE_SWCTRL,
2027                 },
2028         },
2029 };
2030
2031 /* uart4 */
2032 static struct omap_hwmod dra7xx_uart4_hwmod = {
2033         .name           = "uart4",
2034         .class          = &dra7xx_uart_hwmod_class,
2035         .clkdm_name     = "l4per_clkdm",
2036         .main_clk       = "uart4_gfclk_mux",
2037         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2038         .prcm = {
2039                 .omap4 = {
2040                         .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2041                         .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2042                         .modulemode   = MODULEMODE_SWCTRL,
2043                 },
2044         },
2045 };
2046
2047 /* uart5 */
2048 static struct omap_hwmod dra7xx_uart5_hwmod = {
2049         .name           = "uart5",
2050         .class          = &dra7xx_uart_hwmod_class,
2051         .clkdm_name     = "l4per_clkdm",
2052         .main_clk       = "uart5_gfclk_mux",
2053         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2054         .prcm = {
2055                 .omap4 = {
2056                         .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2057                         .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2058                         .modulemode   = MODULEMODE_SWCTRL,
2059                 },
2060         },
2061 };
2062
2063 /* uart6 */
2064 static struct omap_hwmod dra7xx_uart6_hwmod = {
2065         .name           = "uart6",
2066         .class          = &dra7xx_uart_hwmod_class,
2067         .clkdm_name     = "ipu_clkdm",
2068         .main_clk       = "uart6_gfclk_mux",
2069         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2070         .prcm = {
2071                 .omap4 = {
2072                         .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2073                         .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2074                         .modulemode   = MODULEMODE_SWCTRL,
2075                 },
2076         },
2077 };
2078
2079 /* uart7 */
2080 static struct omap_hwmod dra7xx_uart7_hwmod = {
2081         .name           = "uart7",
2082         .class          = &dra7xx_uart_hwmod_class,
2083         .clkdm_name     = "l4per2_clkdm",
2084         .main_clk       = "uart7_gfclk_mux",
2085         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2086         .prcm = {
2087                 .omap4 = {
2088                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2089                         .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2090                         .modulemode   = MODULEMODE_SWCTRL,
2091                 },
2092         },
2093 };
2094
2095 /* uart8 */
2096 static struct omap_hwmod dra7xx_uart8_hwmod = {
2097         .name           = "uart8",
2098         .class          = &dra7xx_uart_hwmod_class,
2099         .clkdm_name     = "l4per2_clkdm",
2100         .main_clk       = "uart8_gfclk_mux",
2101         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2102         .prcm = {
2103                 .omap4 = {
2104                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2105                         .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2106                         .modulemode   = MODULEMODE_SWCTRL,
2107                 },
2108         },
2109 };
2110
2111 /* uart9 */
2112 static struct omap_hwmod dra7xx_uart9_hwmod = {
2113         .name           = "uart9",
2114         .class          = &dra7xx_uart_hwmod_class,
2115         .clkdm_name     = "l4per2_clkdm",
2116         .main_clk       = "uart9_gfclk_mux",
2117         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2118         .prcm = {
2119                 .omap4 = {
2120                         .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2121                         .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2122                         .modulemode   = MODULEMODE_SWCTRL,
2123                 },
2124         },
2125 };
2126
2127 /* uart10 */
2128 static struct omap_hwmod dra7xx_uart10_hwmod = {
2129         .name           = "uart10",
2130         .class          = &dra7xx_uart_hwmod_class,
2131         .clkdm_name     = "wkupaon_clkdm",
2132         .main_clk       = "uart10_gfclk_mux",
2133         .flags          = HWMOD_SWSUP_SIDLE_ACT,
2134         .prcm = {
2135                 .omap4 = {
2136                         .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2137                         .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2138                         .modulemode   = MODULEMODE_SWCTRL,
2139                 },
2140         },
2141 };
2142
2143 /*
2144  * 'usb_otg_ss' class
2145  *
2146  */
2147
2148 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2149         .rev_offs       = 0x0000,
2150         .sysc_offs      = 0x0010,
2151         .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2152                            SYSC_HAS_SIDLEMODE),
2153         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2154                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2155                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2156         .sysc_fields    = &omap_hwmod_sysc_type2,
2157 };
2158
2159 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2160         .name   = "usb_otg_ss",
2161         .sysc   = &dra7xx_usb_otg_ss_sysc,
2162 };
2163
2164 /* usb_otg_ss1 */
2165 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2166         { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2167 };
2168
2169 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2170         .name           = "usb_otg_ss1",
2171         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2172         .clkdm_name     = "l3init_clkdm",
2173         .main_clk       = "dpll_core_h13x2_ck",
2174         .prcm = {
2175                 .omap4 = {
2176                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2177                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2178                         .modulemode   = MODULEMODE_HWCTRL,
2179                 },
2180         },
2181         .opt_clks       = usb_otg_ss1_opt_clks,
2182         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2183 };
2184
2185 /* usb_otg_ss2 */
2186 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2187         { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2188 };
2189
2190 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2191         .name           = "usb_otg_ss2",
2192         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2193         .clkdm_name     = "l3init_clkdm",
2194         .main_clk       = "dpll_core_h13x2_ck",
2195         .prcm = {
2196                 .omap4 = {
2197                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2198                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2199                         .modulemode   = MODULEMODE_HWCTRL,
2200                 },
2201         },
2202         .opt_clks       = usb_otg_ss2_opt_clks,
2203         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2204 };
2205
2206 /* usb_otg_ss3 */
2207 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2208         .name           = "usb_otg_ss3",
2209         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2210         .clkdm_name     = "l3init_clkdm",
2211         .main_clk       = "dpll_core_h13x2_ck",
2212         .prcm = {
2213                 .omap4 = {
2214                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2215                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2216                         .modulemode   = MODULEMODE_HWCTRL,
2217                 },
2218         },
2219 };
2220
2221 /* usb_otg_ss4 */
2222 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2223         .name           = "usb_otg_ss4",
2224         .class          = &dra7xx_usb_otg_ss_hwmod_class,
2225         .clkdm_name     = "l3init_clkdm",
2226         .main_clk       = "dpll_core_h13x2_ck",
2227         .prcm = {
2228                 .omap4 = {
2229                         .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2230                         .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2231                         .modulemode   = MODULEMODE_HWCTRL,
2232                 },
2233         },
2234 };
2235
2236 /*
2237  * 'vcp' class
2238  *
2239  */
2240
2241 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2242         .name   = "vcp",
2243 };
2244
2245 /* vcp1 */
2246 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2247         .name           = "vcp1",
2248         .class          = &dra7xx_vcp_hwmod_class,
2249         .clkdm_name     = "l3main1_clkdm",
2250         .main_clk       = "l3_iclk_div",
2251         .prcm = {
2252                 .omap4 = {
2253                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2254                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2255                 },
2256         },
2257 };
2258
2259 /* vcp2 */
2260 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2261         .name           = "vcp2",
2262         .class          = &dra7xx_vcp_hwmod_class,
2263         .clkdm_name     = "l3main1_clkdm",
2264         .main_clk       = "l3_iclk_div",
2265         .prcm = {
2266                 .omap4 = {
2267                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2268                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2269                 },
2270         },
2271 };
2272
2273 /*
2274  * 'wd_timer' class
2275  *
2276  */
2277
2278 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2279         .rev_offs       = 0x0000,
2280         .sysc_offs      = 0x0010,
2281         .syss_offs      = 0x0014,
2282         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2283                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2284         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2285                            SIDLE_SMART_WKUP),
2286         .sysc_fields    = &omap_hwmod_sysc_type1,
2287 };
2288
2289 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2290         .name           = "wd_timer",
2291         .sysc           = &dra7xx_wd_timer_sysc,
2292         .pre_shutdown   = &omap2_wd_timer_disable,
2293         .reset          = &omap2_wd_timer_reset,
2294 };
2295
2296 /* wd_timer2 */
2297 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2298         .name           = "wd_timer2",
2299         .class          = &dra7xx_wd_timer_hwmod_class,
2300         .clkdm_name     = "wkupaon_clkdm",
2301         .main_clk       = "sys_32k_ck",
2302         .prcm = {
2303                 .omap4 = {
2304                         .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2305                         .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2306                         .modulemode   = MODULEMODE_SWCTRL,
2307                 },
2308         },
2309 };
2310
2311
2312 /*
2313  * Interfaces
2314  */
2315
2316 /* l3_main_2 -> l3_instr */
2317 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2318         .master         = &dra7xx_l3_main_2_hwmod,
2319         .slave          = &dra7xx_l3_instr_hwmod,
2320         .clk            = "l3_iclk_div",
2321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2322 };
2323
2324 /* l4_cfg -> l3_main_1 */
2325 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2326         .master         = &dra7xx_l4_cfg_hwmod,
2327         .slave          = &dra7xx_l3_main_1_hwmod,
2328         .clk            = "l3_iclk_div",
2329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2330 };
2331
2332 /* mpu -> l3_main_1 */
2333 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2334         .master         = &dra7xx_mpu_hwmod,
2335         .slave          = &dra7xx_l3_main_1_hwmod,
2336         .clk            = "l3_iclk_div",
2337         .user           = OCP_USER_MPU,
2338 };
2339
2340 /* l3_main_1 -> l3_main_2 */
2341 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2342         .master         = &dra7xx_l3_main_1_hwmod,
2343         .slave          = &dra7xx_l3_main_2_hwmod,
2344         .clk            = "l3_iclk_div",
2345         .user           = OCP_USER_MPU,
2346 };
2347
2348 /* l4_cfg -> l3_main_2 */
2349 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2350         .master         = &dra7xx_l4_cfg_hwmod,
2351         .slave          = &dra7xx_l3_main_2_hwmod,
2352         .clk            = "l3_iclk_div",
2353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2354 };
2355
2356 /* l3_main_1 -> l4_cfg */
2357 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2358         .master         = &dra7xx_l3_main_1_hwmod,
2359         .slave          = &dra7xx_l4_cfg_hwmod,
2360         .clk            = "l3_iclk_div",
2361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2362 };
2363
2364 /* l3_main_1 -> l4_per1 */
2365 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2366         .master         = &dra7xx_l3_main_1_hwmod,
2367         .slave          = &dra7xx_l4_per1_hwmod,
2368         .clk            = "l3_iclk_div",
2369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2370 };
2371
2372 /* l3_main_1 -> l4_per2 */
2373 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2374         .master         = &dra7xx_l3_main_1_hwmod,
2375         .slave          = &dra7xx_l4_per2_hwmod,
2376         .clk            = "l3_iclk_div",
2377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2378 };
2379
2380 /* l3_main_1 -> l4_per3 */
2381 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2382         .master         = &dra7xx_l3_main_1_hwmod,
2383         .slave          = &dra7xx_l4_per3_hwmod,
2384         .clk            = "l3_iclk_div",
2385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2386 };
2387
2388 /* l3_main_1 -> l4_wkup */
2389 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2390         .master         = &dra7xx_l3_main_1_hwmod,
2391         .slave          = &dra7xx_l4_wkup_hwmod,
2392         .clk            = "wkupaon_iclk_mux",
2393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2394 };
2395
2396 /* l4_per2 -> atl */
2397 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2398         .master         = &dra7xx_l4_per2_hwmod,
2399         .slave          = &dra7xx_atl_hwmod,
2400         .clk            = "l3_iclk_div",
2401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2402 };
2403
2404 /* l3_main_1 -> bb2d */
2405 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2406         .master         = &dra7xx_l3_main_1_hwmod,
2407         .slave          = &dra7xx_bb2d_hwmod,
2408         .clk            = "l3_iclk_div",
2409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2410 };
2411
2412 /* l4_wkup -> counter_32k */
2413 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2414         .master         = &dra7xx_l4_wkup_hwmod,
2415         .slave          = &dra7xx_counter_32k_hwmod,
2416         .clk            = "wkupaon_iclk_mux",
2417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2418 };
2419
2420 /* l4_wkup -> ctrl_module_wkup */
2421 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2422         .master         = &dra7xx_l4_wkup_hwmod,
2423         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
2424         .clk            = "wkupaon_iclk_mux",
2425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2429         .master         = &dra7xx_l4_per2_hwmod,
2430         .slave          = &dra7xx_gmac_hwmod,
2431         .clk            = "dpll_gmac_ck",
2432         .user           = OCP_USER_MPU,
2433 };
2434
2435 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2436         .master         = &dra7xx_gmac_hwmod,
2437         .slave          = &dra7xx_mdio_hwmod,
2438         .user           = OCP_USER_MPU,
2439 };
2440
2441 /* l4_wkup -> dcan1 */
2442 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2443         .master         = &dra7xx_l4_wkup_hwmod,
2444         .slave          = &dra7xx_dcan1_hwmod,
2445         .clk            = "wkupaon_iclk_mux",
2446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2447 };
2448
2449 /* l4_per2 -> dcan2 */
2450 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2451         .master         = &dra7xx_l4_per2_hwmod,
2452         .slave          = &dra7xx_dcan2_hwmod,
2453         .clk            = "l3_iclk_div",
2454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2455 };
2456
2457 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2458         {
2459                 .pa_start       = 0x4a056000,
2460                 .pa_end         = 0x4a056fff,
2461                 .flags          = ADDR_TYPE_RT
2462         },
2463         { }
2464 };
2465
2466 /* l4_cfg -> dma_system */
2467 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2468         .master         = &dra7xx_l4_cfg_hwmod,
2469         .slave          = &dra7xx_dma_system_hwmod,
2470         .clk            = "l3_iclk_div",
2471         .addr           = dra7xx_dma_system_addrs,
2472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2473 };
2474
2475 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2476         {
2477                 .name           = "family",
2478                 .pa_start       = 0x58000000,
2479                 .pa_end         = 0x5800007f,
2480                 .flags          = ADDR_TYPE_RT
2481         },
2482 };
2483
2484 /* l3_main_1 -> dss */
2485 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2486         .master         = &dra7xx_l3_main_1_hwmod,
2487         .slave          = &dra7xx_dss_hwmod,
2488         .clk            = "l3_iclk_div",
2489         .addr           = dra7xx_dss_addrs,
2490         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2491 };
2492
2493 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2494         {
2495                 .name           = "dispc",
2496                 .pa_start       = 0x58001000,
2497                 .pa_end         = 0x58001fff,
2498                 .flags          = ADDR_TYPE_RT
2499         },
2500 };
2501
2502 /* l3_main_1 -> dispc */
2503 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2504         .master         = &dra7xx_l3_main_1_hwmod,
2505         .slave          = &dra7xx_dss_dispc_hwmod,
2506         .clk            = "l3_iclk_div",
2507         .addr           = dra7xx_dss_dispc_addrs,
2508         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2509 };
2510
2511 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2512         {
2513                 .name           = "hdmi_wp",
2514                 .pa_start       = 0x58040000,
2515                 .pa_end         = 0x580400ff,
2516                 .flags          = ADDR_TYPE_RT
2517         },
2518         { }
2519 };
2520
2521 /* l3_main_1 -> dispc */
2522 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2523         .master         = &dra7xx_l3_main_1_hwmod,
2524         .slave          = &dra7xx_dss_hdmi_hwmod,
2525         .clk            = "l3_iclk_div",
2526         .addr           = dra7xx_dss_hdmi_addrs,
2527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2528 };
2529
2530 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2531         {
2532                 .pa_start       = 0x48078000,
2533                 .pa_end         = 0x48078fff,
2534                 .flags          = ADDR_TYPE_RT
2535         },
2536         { }
2537 };
2538
2539 /* l4_per1 -> elm */
2540 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2541         .master         = &dra7xx_l4_per1_hwmod,
2542         .slave          = &dra7xx_elm_hwmod,
2543         .clk            = "l3_iclk_div",
2544         .addr           = dra7xx_elm_addrs,
2545         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2546 };
2547
2548 /* l4_wkup -> gpio1 */
2549 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2550         .master         = &dra7xx_l4_wkup_hwmod,
2551         .slave          = &dra7xx_gpio1_hwmod,
2552         .clk            = "wkupaon_iclk_mux",
2553         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2554 };
2555
2556 /* l4_per1 -> gpio2 */
2557 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2558         .master         = &dra7xx_l4_per1_hwmod,
2559         .slave          = &dra7xx_gpio2_hwmod,
2560         .clk            = "l3_iclk_div",
2561         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2562 };
2563
2564 /* l4_per1 -> gpio3 */
2565 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2566         .master         = &dra7xx_l4_per1_hwmod,
2567         .slave          = &dra7xx_gpio3_hwmod,
2568         .clk            = "l3_iclk_div",
2569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2571
2572 /* l4_per1 -> gpio4 */
2573 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2574         .master         = &dra7xx_l4_per1_hwmod,
2575         .slave          = &dra7xx_gpio4_hwmod,
2576         .clk            = "l3_iclk_div",
2577         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2578 };
2579
2580 /* l4_per1 -> gpio5 */
2581 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2582         .master         = &dra7xx_l4_per1_hwmod,
2583         .slave          = &dra7xx_gpio5_hwmod,
2584         .clk            = "l3_iclk_div",
2585         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2586 };
2587
2588 /* l4_per1 -> gpio6 */
2589 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2590         .master         = &dra7xx_l4_per1_hwmod,
2591         .slave          = &dra7xx_gpio6_hwmod,
2592         .clk            = "l3_iclk_div",
2593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2594 };
2595
2596 /* l4_per1 -> gpio7 */
2597 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2598         .master         = &dra7xx_l4_per1_hwmod,
2599         .slave          = &dra7xx_gpio7_hwmod,
2600         .clk            = "l3_iclk_div",
2601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2602 };
2603
2604 /* l4_per1 -> gpio8 */
2605 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2606         .master         = &dra7xx_l4_per1_hwmod,
2607         .slave          = &dra7xx_gpio8_hwmod,
2608         .clk            = "l3_iclk_div",
2609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2611
2612 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2613         {
2614                 .pa_start       = 0x50000000,
2615                 .pa_end         = 0x500003ff,
2616                 .flags          = ADDR_TYPE_RT
2617         },
2618         { }
2619 };
2620
2621 /* l3_main_1 -> gpmc */
2622 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2623         .master         = &dra7xx_l3_main_1_hwmod,
2624         .slave          = &dra7xx_gpmc_hwmod,
2625         .clk            = "l3_iclk_div",
2626         .addr           = dra7xx_gpmc_addrs,
2627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2628 };
2629
2630 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2631         {
2632                 .pa_start       = 0x480b2000,
2633                 .pa_end         = 0x480b201f,
2634                 .flags          = ADDR_TYPE_RT
2635         },
2636         { }
2637 };
2638
2639 /* l4_per1 -> hdq1w */
2640 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2641         .master         = &dra7xx_l4_per1_hwmod,
2642         .slave          = &dra7xx_hdq1w_hwmod,
2643         .clk            = "l3_iclk_div",
2644         .addr           = dra7xx_hdq1w_addrs,
2645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2646 };
2647
2648 /* l4_per1 -> i2c1 */
2649 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2650         .master         = &dra7xx_l4_per1_hwmod,
2651         .slave          = &dra7xx_i2c1_hwmod,
2652         .clk            = "l3_iclk_div",
2653         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2654 };
2655
2656 /* l4_per1 -> i2c2 */
2657 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2658         .master         = &dra7xx_l4_per1_hwmod,
2659         .slave          = &dra7xx_i2c2_hwmod,
2660         .clk            = "l3_iclk_div",
2661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2663
2664 /* l4_per1 -> i2c3 */
2665 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2666         .master         = &dra7xx_l4_per1_hwmod,
2667         .slave          = &dra7xx_i2c3_hwmod,
2668         .clk            = "l3_iclk_div",
2669         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2670 };
2671
2672 /* l4_per1 -> i2c4 */
2673 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2674         .master         = &dra7xx_l4_per1_hwmod,
2675         .slave          = &dra7xx_i2c4_hwmod,
2676         .clk            = "l3_iclk_div",
2677         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2678 };
2679
2680 /* l4_per1 -> i2c5 */
2681 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2682         .master         = &dra7xx_l4_per1_hwmod,
2683         .slave          = &dra7xx_i2c5_hwmod,
2684         .clk            = "l3_iclk_div",
2685         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2686 };
2687
2688 /* l4_cfg -> mailbox1 */
2689 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2690         .master         = &dra7xx_l4_cfg_hwmod,
2691         .slave          = &dra7xx_mailbox1_hwmod,
2692         .clk            = "l3_iclk_div",
2693         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2694 };
2695
2696 /* l4_per3 -> mailbox2 */
2697 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2698         .master         = &dra7xx_l4_per3_hwmod,
2699         .slave          = &dra7xx_mailbox2_hwmod,
2700         .clk            = "l3_iclk_div",
2701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 /* l4_per3 -> mailbox3 */
2705 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2706         .master         = &dra7xx_l4_per3_hwmod,
2707         .slave          = &dra7xx_mailbox3_hwmod,
2708         .clk            = "l3_iclk_div",
2709         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2710 };
2711
2712 /* l4_per3 -> mailbox4 */
2713 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2714         .master         = &dra7xx_l4_per3_hwmod,
2715         .slave          = &dra7xx_mailbox4_hwmod,
2716         .clk            = "l3_iclk_div",
2717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_per3 -> mailbox5 */
2721 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2722         .master         = &dra7xx_l4_per3_hwmod,
2723         .slave          = &dra7xx_mailbox5_hwmod,
2724         .clk            = "l3_iclk_div",
2725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2726 };
2727
2728 /* l4_per3 -> mailbox6 */
2729 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2730         .master         = &dra7xx_l4_per3_hwmod,
2731         .slave          = &dra7xx_mailbox6_hwmod,
2732         .clk            = "l3_iclk_div",
2733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 /* l4_per3 -> mailbox7 */
2737 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2738         .master         = &dra7xx_l4_per3_hwmod,
2739         .slave          = &dra7xx_mailbox7_hwmod,
2740         .clk            = "l3_iclk_div",
2741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2742 };
2743
2744 /* l4_per3 -> mailbox8 */
2745 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2746         .master         = &dra7xx_l4_per3_hwmod,
2747         .slave          = &dra7xx_mailbox8_hwmod,
2748         .clk            = "l3_iclk_div",
2749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2750 };
2751
2752 /* l4_per3 -> mailbox9 */
2753 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2754         .master         = &dra7xx_l4_per3_hwmod,
2755         .slave          = &dra7xx_mailbox9_hwmod,
2756         .clk            = "l3_iclk_div",
2757         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2758 };
2759
2760 /* l4_per3 -> mailbox10 */
2761 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2762         .master         = &dra7xx_l4_per3_hwmod,
2763         .slave          = &dra7xx_mailbox10_hwmod,
2764         .clk            = "l3_iclk_div",
2765         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2766 };
2767
2768 /* l4_per3 -> mailbox11 */
2769 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2770         .master         = &dra7xx_l4_per3_hwmod,
2771         .slave          = &dra7xx_mailbox11_hwmod,
2772         .clk            = "l3_iclk_div",
2773         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2774 };
2775
2776 /* l4_per3 -> mailbox12 */
2777 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2778         .master         = &dra7xx_l4_per3_hwmod,
2779         .slave          = &dra7xx_mailbox12_hwmod,
2780         .clk            = "l3_iclk_div",
2781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2782 };
2783
2784 /* l4_per3 -> mailbox13 */
2785 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2786         .master         = &dra7xx_l4_per3_hwmod,
2787         .slave          = &dra7xx_mailbox13_hwmod,
2788         .clk            = "l3_iclk_div",
2789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2790 };
2791
2792 /* l4_per1 -> mcspi1 */
2793 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2794         .master         = &dra7xx_l4_per1_hwmod,
2795         .slave          = &dra7xx_mcspi1_hwmod,
2796         .clk            = "l3_iclk_div",
2797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2798 };
2799
2800 /* l4_per1 -> mcspi2 */
2801 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2802         .master         = &dra7xx_l4_per1_hwmod,
2803         .slave          = &dra7xx_mcspi2_hwmod,
2804         .clk            = "l3_iclk_div",
2805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2806 };
2807
2808 /* l4_per1 -> mcspi3 */
2809 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2810         .master         = &dra7xx_l4_per1_hwmod,
2811         .slave          = &dra7xx_mcspi3_hwmod,
2812         .clk            = "l3_iclk_div",
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* l4_per1 -> mcspi4 */
2817 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2818         .master         = &dra7xx_l4_per1_hwmod,
2819         .slave          = &dra7xx_mcspi4_hwmod,
2820         .clk            = "l3_iclk_div",
2821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2822 };
2823
2824 /* l4_per1 -> mmc1 */
2825 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2826         .master         = &dra7xx_l4_per1_hwmod,
2827         .slave          = &dra7xx_mmc1_hwmod,
2828         .clk            = "l3_iclk_div",
2829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2830 };
2831
2832 /* l4_per1 -> mmc2 */
2833 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2834         .master         = &dra7xx_l4_per1_hwmod,
2835         .slave          = &dra7xx_mmc2_hwmod,
2836         .clk            = "l3_iclk_div",
2837         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2838 };
2839
2840 /* l4_per1 -> mmc3 */
2841 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2842         .master         = &dra7xx_l4_per1_hwmod,
2843         .slave          = &dra7xx_mmc3_hwmod,
2844         .clk            = "l3_iclk_div",
2845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2846 };
2847
2848 /* l4_per1 -> mmc4 */
2849 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2850         .master         = &dra7xx_l4_per1_hwmod,
2851         .slave          = &dra7xx_mmc4_hwmod,
2852         .clk            = "l3_iclk_div",
2853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2854 };
2855
2856 /* l4_cfg -> mpu */
2857 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2858         .master         = &dra7xx_l4_cfg_hwmod,
2859         .slave          = &dra7xx_mpu_hwmod,
2860         .clk            = "l3_iclk_div",
2861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2862 };
2863
2864 /* l4_cfg -> ocp2scp1 */
2865 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2866         .master         = &dra7xx_l4_cfg_hwmod,
2867         .slave          = &dra7xx_ocp2scp1_hwmod,
2868         .clk            = "l4_root_clk_div",
2869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2870 };
2871
2872 /* l4_cfg -> ocp2scp3 */
2873 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2874         .master         = &dra7xx_l4_cfg_hwmod,
2875         .slave          = &dra7xx_ocp2scp3_hwmod,
2876         .clk            = "l4_root_clk_div",
2877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2878 };
2879
2880 /* l3_main_1 -> pcie1 */
2881 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
2882         .master         = &dra7xx_l3_main_1_hwmod,
2883         .slave          = &dra7xx_pcie1_hwmod,
2884         .clk            = "l3_iclk_div",
2885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2886 };
2887
2888 /* l4_cfg -> pcie1 */
2889 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
2890         .master         = &dra7xx_l4_cfg_hwmod,
2891         .slave          = &dra7xx_pcie1_hwmod,
2892         .clk            = "l4_root_clk_div",
2893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2894 };
2895
2896 /* l3_main_1 -> pcie2 */
2897 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
2898         .master         = &dra7xx_l3_main_1_hwmod,
2899         .slave          = &dra7xx_pcie2_hwmod,
2900         .clk            = "l3_iclk_div",
2901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2902 };
2903
2904 /* l4_cfg -> pcie2 */
2905 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
2906         .master         = &dra7xx_l4_cfg_hwmod,
2907         .slave          = &dra7xx_pcie2_hwmod,
2908         .clk            = "l4_root_clk_div",
2909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2910 };
2911
2912 /* l4_cfg -> pcie1 phy */
2913 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2914         .master         = &dra7xx_l4_cfg_hwmod,
2915         .slave          = &dra7xx_pcie1_phy_hwmod,
2916         .clk            = "l4_root_clk_div",
2917         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2918 };
2919
2920 /* l4_cfg -> pcie2 phy */
2921 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2922         .master         = &dra7xx_l4_cfg_hwmod,
2923         .slave          = &dra7xx_pcie2_phy_hwmod,
2924         .clk            = "l4_root_clk_div",
2925         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2926 };
2927
2928 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2929         {
2930                 .pa_start       = 0x4b300000,
2931                 .pa_end         = 0x4b30007f,
2932                 .flags          = ADDR_TYPE_RT
2933         },
2934         { }
2935 };
2936
2937 /* l3_main_1 -> qspi */
2938 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2939         .master         = &dra7xx_l3_main_1_hwmod,
2940         .slave          = &dra7xx_qspi_hwmod,
2941         .clk            = "l3_iclk_div",
2942         .addr           = dra7xx_qspi_addrs,
2943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2944 };
2945
2946 /* l4_per3 -> rtcss */
2947 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2948         .master         = &dra7xx_l4_per3_hwmod,
2949         .slave          = &dra7xx_rtcss_hwmod,
2950         .clk            = "l4_root_clk_div",
2951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2952 };
2953
2954 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2955         {
2956                 .name           = "sysc",
2957                 .pa_start       = 0x4a141100,
2958                 .pa_end         = 0x4a141107,
2959                 .flags          = ADDR_TYPE_RT
2960         },
2961         { }
2962 };
2963
2964 /* l4_cfg -> sata */
2965 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2966         .master         = &dra7xx_l4_cfg_hwmod,
2967         .slave          = &dra7xx_sata_hwmod,
2968         .clk            = "l3_iclk_div",
2969         .addr           = dra7xx_sata_addrs,
2970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2971 };
2972
2973 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2974         {
2975                 .pa_start       = 0x4a0dd000,
2976                 .pa_end         = 0x4a0dd07f,
2977                 .flags          = ADDR_TYPE_RT
2978         },
2979         { }
2980 };
2981
2982 /* l4_cfg -> smartreflex_core */
2983 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2984         .master         = &dra7xx_l4_cfg_hwmod,
2985         .slave          = &dra7xx_smartreflex_core_hwmod,
2986         .clk            = "l4_root_clk_div",
2987         .addr           = dra7xx_smartreflex_core_addrs,
2988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2989 };
2990
2991 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2992         {
2993                 .pa_start       = 0x4a0d9000,
2994                 .pa_end         = 0x4a0d907f,
2995                 .flags          = ADDR_TYPE_RT
2996         },
2997         { }
2998 };
2999
3000 /* l4_cfg -> smartreflex_mpu */
3001 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3002         .master         = &dra7xx_l4_cfg_hwmod,
3003         .slave          = &dra7xx_smartreflex_mpu_hwmod,
3004         .clk            = "l4_root_clk_div",
3005         .addr           = dra7xx_smartreflex_mpu_addrs,
3006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3007 };
3008
3009 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
3010         {
3011                 .pa_start       = 0x4a0f6000,
3012                 .pa_end         = 0x4a0f6fff,
3013                 .flags          = ADDR_TYPE_RT
3014         },
3015         { }
3016 };
3017
3018 /* l4_cfg -> spinlock */
3019 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3020         .master         = &dra7xx_l4_cfg_hwmod,
3021         .slave          = &dra7xx_spinlock_hwmod,
3022         .clk            = "l3_iclk_div",
3023         .addr           = dra7xx_spinlock_addrs,
3024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3025 };
3026
3027 /* l4_wkup -> timer1 */
3028 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3029         .master         = &dra7xx_l4_wkup_hwmod,
3030         .slave          = &dra7xx_timer1_hwmod,
3031         .clk            = "wkupaon_iclk_mux",
3032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3033 };
3034
3035 /* l4_per1 -> timer2 */
3036 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3037         .master         = &dra7xx_l4_per1_hwmod,
3038         .slave          = &dra7xx_timer2_hwmod,
3039         .clk            = "l3_iclk_div",
3040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3041 };
3042
3043 /* l4_per1 -> timer3 */
3044 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3045         .master         = &dra7xx_l4_per1_hwmod,
3046         .slave          = &dra7xx_timer3_hwmod,
3047         .clk            = "l3_iclk_div",
3048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3049 };
3050
3051 /* l4_per1 -> timer4 */
3052 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3053         .master         = &dra7xx_l4_per1_hwmod,
3054         .slave          = &dra7xx_timer4_hwmod,
3055         .clk            = "l3_iclk_div",
3056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3057 };
3058
3059 /* l4_per3 -> timer5 */
3060 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3061         .master         = &dra7xx_l4_per3_hwmod,
3062         .slave          = &dra7xx_timer5_hwmod,
3063         .clk            = "l3_iclk_div",
3064         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3065 };
3066
3067 /* l4_per3 -> timer6 */
3068 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3069         .master         = &dra7xx_l4_per3_hwmod,
3070         .slave          = &dra7xx_timer6_hwmod,
3071         .clk            = "l3_iclk_div",
3072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3073 };
3074
3075 /* l4_per3 -> timer7 */
3076 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3077         .master         = &dra7xx_l4_per3_hwmod,
3078         .slave          = &dra7xx_timer7_hwmod,
3079         .clk            = "l3_iclk_div",
3080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3081 };
3082
3083 /* l4_per3 -> timer8 */
3084 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3085         .master         = &dra7xx_l4_per3_hwmod,
3086         .slave          = &dra7xx_timer8_hwmod,
3087         .clk            = "l3_iclk_div",
3088         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3089 };
3090
3091 /* l4_per1 -> timer9 */
3092 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3093         .master         = &dra7xx_l4_per1_hwmod,
3094         .slave          = &dra7xx_timer9_hwmod,
3095         .clk            = "l3_iclk_div",
3096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3097 };
3098
3099 /* l4_per1 -> timer10 */
3100 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3101         .master         = &dra7xx_l4_per1_hwmod,
3102         .slave          = &dra7xx_timer10_hwmod,
3103         .clk            = "l3_iclk_div",
3104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3105 };
3106
3107 /* l4_per1 -> timer11 */
3108 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3109         .master         = &dra7xx_l4_per1_hwmod,
3110         .slave          = &dra7xx_timer11_hwmod,
3111         .clk            = "l3_iclk_div",
3112         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3113 };
3114
3115 /* l4_per1 -> uart1 */
3116 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3117         .master         = &dra7xx_l4_per1_hwmod,
3118         .slave          = &dra7xx_uart1_hwmod,
3119         .clk            = "l3_iclk_div",
3120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3121 };
3122
3123 /* l4_per1 -> uart2 */
3124 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3125         .master         = &dra7xx_l4_per1_hwmod,
3126         .slave          = &dra7xx_uart2_hwmod,
3127         .clk            = "l3_iclk_div",
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* l4_per1 -> uart3 */
3132 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3133         .master         = &dra7xx_l4_per1_hwmod,
3134         .slave          = &dra7xx_uart3_hwmod,
3135         .clk            = "l3_iclk_div",
3136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 /* l4_per1 -> uart4 */
3140 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3141         .master         = &dra7xx_l4_per1_hwmod,
3142         .slave          = &dra7xx_uart4_hwmod,
3143         .clk            = "l3_iclk_div",
3144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3145 };
3146
3147 /* l4_per1 -> uart5 */
3148 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3149         .master         = &dra7xx_l4_per1_hwmod,
3150         .slave          = &dra7xx_uart5_hwmod,
3151         .clk            = "l3_iclk_div",
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 /* l4_per1 -> uart6 */
3156 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3157         .master         = &dra7xx_l4_per1_hwmod,
3158         .slave          = &dra7xx_uart6_hwmod,
3159         .clk            = "l3_iclk_div",
3160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3161 };
3162
3163 /* l4_per2 -> uart7 */
3164 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3165         .master         = &dra7xx_l4_per2_hwmod,
3166         .slave          = &dra7xx_uart7_hwmod,
3167         .clk            = "l3_iclk_div",
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 /* l4_per2 -> uart8 */
3172 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3173         .master         = &dra7xx_l4_per2_hwmod,
3174         .slave          = &dra7xx_uart8_hwmod,
3175         .clk            = "l3_iclk_div",
3176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3177 };
3178
3179 /* l4_per2 -> uart9 */
3180 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3181         .master         = &dra7xx_l4_per2_hwmod,
3182         .slave          = &dra7xx_uart9_hwmod,
3183         .clk            = "l3_iclk_div",
3184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3185 };
3186
3187 /* l4_wkup -> uart10 */
3188 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3189         .master         = &dra7xx_l4_wkup_hwmod,
3190         .slave          = &dra7xx_uart10_hwmod,
3191         .clk            = "wkupaon_iclk_mux",
3192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 /* l4_per3 -> usb_otg_ss1 */
3196 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3197         .master         = &dra7xx_l4_per3_hwmod,
3198         .slave          = &dra7xx_usb_otg_ss1_hwmod,
3199         .clk            = "dpll_core_h13x2_ck",
3200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3201 };
3202
3203 /* l4_per3 -> usb_otg_ss2 */
3204 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3205         .master         = &dra7xx_l4_per3_hwmod,
3206         .slave          = &dra7xx_usb_otg_ss2_hwmod,
3207         .clk            = "dpll_core_h13x2_ck",
3208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3209 };
3210
3211 /* l4_per3 -> usb_otg_ss3 */
3212 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3213         .master         = &dra7xx_l4_per3_hwmod,
3214         .slave          = &dra7xx_usb_otg_ss3_hwmod,
3215         .clk            = "dpll_core_h13x2_ck",
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* l4_per3 -> usb_otg_ss4 */
3220 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3221         .master         = &dra7xx_l4_per3_hwmod,
3222         .slave          = &dra7xx_usb_otg_ss4_hwmod,
3223         .clk            = "dpll_core_h13x2_ck",
3224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3225 };
3226
3227 /* l3_main_1 -> vcp1 */
3228 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3229         .master         = &dra7xx_l3_main_1_hwmod,
3230         .slave          = &dra7xx_vcp1_hwmod,
3231         .clk            = "l3_iclk_div",
3232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3233 };
3234
3235 /* l4_per2 -> vcp1 */
3236 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3237         .master         = &dra7xx_l4_per2_hwmod,
3238         .slave          = &dra7xx_vcp1_hwmod,
3239         .clk            = "l3_iclk_div",
3240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3241 };
3242
3243 /* l3_main_1 -> vcp2 */
3244 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3245         .master         = &dra7xx_l3_main_1_hwmod,
3246         .slave          = &dra7xx_vcp2_hwmod,
3247         .clk            = "l3_iclk_div",
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 /* l4_per2 -> vcp2 */
3252 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3253         .master         = &dra7xx_l4_per2_hwmod,
3254         .slave          = &dra7xx_vcp2_hwmod,
3255         .clk            = "l3_iclk_div",
3256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3257 };
3258
3259 /* l4_wkup -> wd_timer2 */
3260 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3261         .master         = &dra7xx_l4_wkup_hwmod,
3262         .slave          = &dra7xx_wd_timer2_hwmod,
3263         .clk            = "wkupaon_iclk_mux",
3264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3268         &dra7xx_l3_main_2__l3_instr,
3269         &dra7xx_l4_cfg__l3_main_1,
3270         &dra7xx_mpu__l3_main_1,
3271         &dra7xx_l3_main_1__l3_main_2,
3272         &dra7xx_l4_cfg__l3_main_2,
3273         &dra7xx_l3_main_1__l4_cfg,
3274         &dra7xx_l3_main_1__l4_per1,
3275         &dra7xx_l3_main_1__l4_per2,
3276         &dra7xx_l3_main_1__l4_per3,
3277         &dra7xx_l3_main_1__l4_wkup,
3278         &dra7xx_l4_per2__atl,
3279         &dra7xx_l3_main_1__bb2d,
3280         &dra7xx_l4_wkup__counter_32k,
3281         &dra7xx_l4_wkup__ctrl_module_wkup,
3282         &dra7xx_l4_wkup__dcan1,
3283         &dra7xx_l4_per2__dcan2,
3284         &dra7xx_l4_per2__cpgmac0,
3285         &dra7xx_gmac__mdio,
3286         &dra7xx_l4_cfg__dma_system,
3287         &dra7xx_l3_main_1__dss,
3288         &dra7xx_l3_main_1__dispc,
3289         &dra7xx_l3_main_1__hdmi,
3290         &dra7xx_l4_per1__elm,
3291         &dra7xx_l4_wkup__gpio1,
3292         &dra7xx_l4_per1__gpio2,
3293         &dra7xx_l4_per1__gpio3,
3294         &dra7xx_l4_per1__gpio4,
3295         &dra7xx_l4_per1__gpio5,
3296         &dra7xx_l4_per1__gpio6,
3297         &dra7xx_l4_per1__gpio7,
3298         &dra7xx_l4_per1__gpio8,
3299         &dra7xx_l3_main_1__gpmc,
3300         &dra7xx_l4_per1__hdq1w,
3301         &dra7xx_l4_per1__i2c1,
3302         &dra7xx_l4_per1__i2c2,
3303         &dra7xx_l4_per1__i2c3,
3304         &dra7xx_l4_per1__i2c4,
3305         &dra7xx_l4_per1__i2c5,
3306         &dra7xx_l4_cfg__mailbox1,
3307         &dra7xx_l4_per3__mailbox2,
3308         &dra7xx_l4_per3__mailbox3,
3309         &dra7xx_l4_per3__mailbox4,
3310         &dra7xx_l4_per3__mailbox5,
3311         &dra7xx_l4_per3__mailbox6,
3312         &dra7xx_l4_per3__mailbox7,
3313         &dra7xx_l4_per3__mailbox8,
3314         &dra7xx_l4_per3__mailbox9,
3315         &dra7xx_l4_per3__mailbox10,
3316         &dra7xx_l4_per3__mailbox11,
3317         &dra7xx_l4_per3__mailbox12,
3318         &dra7xx_l4_per3__mailbox13,
3319         &dra7xx_l4_per1__mcspi1,
3320         &dra7xx_l4_per1__mcspi2,
3321         &dra7xx_l4_per1__mcspi3,
3322         &dra7xx_l4_per1__mcspi4,
3323         &dra7xx_l4_per1__mmc1,
3324         &dra7xx_l4_per1__mmc2,
3325         &dra7xx_l4_per1__mmc3,
3326         &dra7xx_l4_per1__mmc4,
3327         &dra7xx_l4_cfg__mpu,
3328         &dra7xx_l4_cfg__ocp2scp1,
3329         &dra7xx_l4_cfg__ocp2scp3,
3330         &dra7xx_l3_main_1__pcie1,
3331         &dra7xx_l4_cfg__pcie1,
3332         &dra7xx_l3_main_1__pcie2,
3333         &dra7xx_l4_cfg__pcie2,
3334         &dra7xx_l4_cfg__pcie1_phy,
3335         &dra7xx_l4_cfg__pcie2_phy,
3336         &dra7xx_l3_main_1__qspi,
3337         &dra7xx_l4_per3__rtcss,
3338         &dra7xx_l4_cfg__sata,
3339         &dra7xx_l4_cfg__smartreflex_core,
3340         &dra7xx_l4_cfg__smartreflex_mpu,
3341         &dra7xx_l4_cfg__spinlock,
3342         &dra7xx_l4_wkup__timer1,
3343         &dra7xx_l4_per1__timer2,
3344         &dra7xx_l4_per1__timer3,
3345         &dra7xx_l4_per1__timer4,
3346         &dra7xx_l4_per3__timer5,
3347         &dra7xx_l4_per3__timer6,
3348         &dra7xx_l4_per3__timer7,
3349         &dra7xx_l4_per3__timer8,
3350         &dra7xx_l4_per1__timer9,
3351         &dra7xx_l4_per1__timer10,
3352         &dra7xx_l4_per1__timer11,
3353         &dra7xx_l4_per1__uart1,
3354         &dra7xx_l4_per1__uart2,
3355         &dra7xx_l4_per1__uart3,
3356         &dra7xx_l4_per1__uart4,
3357         &dra7xx_l4_per1__uart5,
3358         &dra7xx_l4_per1__uart6,
3359         &dra7xx_l4_per2__uart7,
3360         &dra7xx_l4_per2__uart8,
3361         &dra7xx_l4_per2__uart9,
3362         &dra7xx_l4_wkup__uart10,
3363         &dra7xx_l4_per3__usb_otg_ss1,
3364         &dra7xx_l4_per3__usb_otg_ss2,
3365         &dra7xx_l4_per3__usb_otg_ss3,
3366         &dra7xx_l3_main_1__vcp1,
3367         &dra7xx_l4_per2__vcp1,
3368         &dra7xx_l3_main_1__vcp2,
3369         &dra7xx_l4_per2__vcp2,
3370         &dra7xx_l4_wkup__wd_timer2,
3371         NULL,
3372 };
3373
3374 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3375         &dra7xx_l4_per3__usb_otg_ss4,
3376         NULL,
3377 };
3378
3379 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3380         NULL,
3381 };
3382
3383 int __init dra7xx_hwmod_init(void)
3384 {
3385         int ret;
3386
3387         omap_hwmod_init();
3388         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3389
3390         if (!ret && soc_is_dra74x())
3391                 return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3392         else if (!ret && soc_is_dra72x())
3393                 return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3394
3395         return ret;
3396 }