arch/arm/mach-realview/core.c

   1 /*
   2  *  linux/arch/arm/mach-realview/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/sysdev.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/amba/clcd.h>
  28 #include <linux/io.h>
  29 #include <linux/smsc911x.h>
  30 #include <linux/ata_platform.h>
  31 #include <linux/amba/mmci.h>
  32 #include <linux/gfp.h>
  33
  34 #include <asm/clkdev.h>
  35 #include <asm/system.h>
  36 #include <mach/hardware.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/mach-types.h>
  40 #include <asm/hardware/arm_timer.h>
  41 #include <asm/hardware/icst.h>
  42
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/flash.h>
  45 #include <asm/mach/irq.h>
  46 #include <asm/mach/map.h>
  47
  48 #include <asm/hardware/gic.h>
  49
  50 #include <mach/clkdev.h>
  51 #include <mach/platform.h>
  52 #include <mach/irqs.h>
  53 #include <asm/hardware/timer-sp.h>
  54
  55 #include "core.h"
  56
  57 #ifdef CONFIG_ZONE_DMA
  58 /*
  59  * Adjust the zones if there are restrictions for DMA access.
  60  */
  61 void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
  62 {
  63         unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
  64
  65         if (!machine_is_realview_pbx() || size[0] <= dma_size)
  66                 return;
  67
  68         size[ZONE_NORMAL] = size[0] - dma_size;
  69         size[ZONE_DMA] = dma_size;
  70         hole[ZONE_NORMAL] = hole[0];
  71         hole[ZONE_DMA] = 0;
  72 }
  73 #endif
  74
  75
  76 #define REALVIEW_FLASHCTRL    (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
  77
  78 static int realview_flash_init(void)
  79 {
  80         u32 val;
  81
  82         val = __raw_readl(REALVIEW_FLASHCTRL);
  83         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  84         __raw_writel(val, REALVIEW_FLASHCTRL);
  85
  86         return 0;
  87 }
  88
  89 static void realview_flash_exit(void)
  90 {
  91         u32 val;
  92
  93         val = __raw_readl(REALVIEW_FLASHCTRL);
  94         val &= ~REALVIEW_FLASHPROG_FLVPPEN;
  95         __raw_writel(val, REALVIEW_FLASHCTRL);
  96 }
  97
  98 static void realview_flash_set_vpp(int on)
  99 {
 100         u32 val;
 101
 102         val = __raw_readl(REALVIEW_FLASHCTRL);
 103         if (on)
 104                 val |= REALVIEW_FLASHPROG_FLVPPEN;
 105         else
 106                 val &= ~REALVIEW_FLASHPROG_FLVPPEN;
 107         __raw_writel(val, REALVIEW_FLASHCTRL);
 108 }
 109
 110 static struct flash_platform_data realview_flash_data = {
 111         .map_name               = "cfi_probe",
 112         .width                  = 4,
 113         .init                   = realview_flash_init,
 114         .exit                   = realview_flash_exit,
 115         .set_vpp                = realview_flash_set_vpp,
 116 };
 117
 118 struct platform_device realview_flash_device = {
 119         .name                   = "armflash",
 120         .id                     = 0,
 121         .dev                    = {
 122                 .platform_data  = &realview_flash_data,
 123         },
 124 };
 125
 126 int realview_flash_register(struct resource *res, u32 num)
 127 {
 128         realview_flash_device.resource = res;
 129         realview_flash_device.num_resources = num;
 130         return platform_device_register(&realview_flash_device);
 131 }
 132
 133 static struct smsc911x_platform_config smsc911x_config = {
 134         .flags          = SMSC911X_USE_32BIT,
 135         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
 136         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
 137         .phy_interface  = PHY_INTERFACE_MODE_MII,
 138 };
 139
 140 static struct platform_device realview_eth_device = {
 141         .name           = "smsc911x",
 142         .id             = 0,
 143         .num_resources  = 2,
 144 };
 145
 146 int realview_eth_register(const char *name, struct resource *res)
 147 {
 148         if (name)
 149                 realview_eth_device.name = name;
 150         realview_eth_device.resource = res;
 151         if (strcmp(realview_eth_device.name, "smsc911x") == 0)
 152                 realview_eth_device.dev.platform_data = &smsc911x_config;
 153
 154         return platform_device_register(&realview_eth_device);
 155 }
 156
 157 struct platform_device realview_usb_device = {
 158         .name                   = "isp1760",
 159         .num_resources          = 2,
 160 };
 161
 162 int realview_usb_register(struct resource *res)
 163 {
 164         realview_usb_device.resource = res;
 165         return platform_device_register(&realview_usb_device);
 166 }
 167
 168 static struct pata_platform_info pata_platform_data = {
 169         .ioport_shift           = 1,
 170 };
 171
 172 static struct resource pata_resources[] = {
 173         [0] = {
 174                 .start          = REALVIEW_CF_BASE,
 175                 .end            = REALVIEW_CF_BASE + 0xff,
 176                 .flags          = IORESOURCE_MEM,
 177         },
 178         [1] = {
 179                 .start          = REALVIEW_CF_BASE + 0x100,
 180                 .end            = REALVIEW_CF_BASE + SZ_4K - 1,
 181                 .flags          = IORESOURCE_MEM,
 182         },
 183 };
 184
 185 struct platform_device realview_cf_device = {
 186         .name                   = "pata_platform",
 187         .id                     = -1,
 188         .num_resources          = ARRAY_SIZE(pata_resources),
 189         .resource               = pata_resources,
 190         .dev                    = {
 191                 .platform_data  = &pata_platform_data,
 192         },
 193 };
 194
 195 static struct resource realview_i2c_resource = {
 196         .start          = REALVIEW_I2C_BASE,
 197         .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
 198         .flags          = IORESOURCE_MEM,
 199 };
 200
 201 struct platform_device realview_i2c_device = {
 202         .name           = "versatile-i2c",
 203         .id             = 0,
 204         .num_resources  = 1,
 205         .resource       = &realview_i2c_resource,
 206 };
 207
 208 static struct i2c_board_info realview_i2c_board_info[] = {
 209         {
 210                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 211         },
 212 };
 213
 214 static int __init realview_i2c_init(void)
 215 {
 216         return i2c_register_board_info(0, realview_i2c_board_info,
 217                                        ARRAY_SIZE(realview_i2c_board_info));
 218 }
 219 arch_initcall(realview_i2c_init);
 220
 221 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
 222
 223 /*
 224  * This is only used if GPIOLIB support is disabled
 225  */
 226 static unsigned int realview_mmc_status(struct device *dev)
 227 {
 228         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 229         u32 mask;
 230
 231         if (machine_is_realview_pb1176()) {
 232                 static bool inserted = false;
 233
 234                 /*
 235                  * The PB1176 does not have the status register,
 236                  * assume it is inserted at startup, then invert
 237                  * for each call so card insertion/removal will
 238                  * be detected anyway. This will not be called if
 239                  * GPIO on PL061 is active, which is the proper
 240                  * way to do this on the PB1176.
 241                  */
 242                 inserted = !inserted;
 243                 return inserted ? 0 : 1;
 244         }
 245
 246         if (adev->res.start == REALVIEW_MMCI0_BASE)
 247                 mask = 1;
 248         else
 249                 mask = 2;
 250
 251         return readl(REALVIEW_SYSMCI) & mask;
 252 }
 253
 254 struct mmci_platform_data realview_mmc0_plat_data = {
 255         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 256         .status         = realview_mmc_status,
 257         .gpio_wp        = 17,
 258         .gpio_cd        = 16,
 259         .cd_invert      = true,
 260 };
 261
 262 struct mmci_platform_data realview_mmc1_plat_data = {
 263         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 264         .status         = realview_mmc_status,
 265         .gpio_wp        = 19,
 266         .gpio_cd        = 18,
 267         .cd_invert      = true,
 268 };
 269
 270 /*
 271  * Clock handling
 272  */
 273 static const struct icst_params realview_oscvco_params = {
 274         .ref            = 24000000,
 275         .vco_max        = ICST307_VCO_MAX,
 276         .vco_min        = ICST307_VCO_MIN,
 277         .vd_min         = 4 + 8,
 278         .vd_max         = 511 + 8,
 279         .rd_min         = 1 + 2,
 280         .rd_max         = 127 + 2,
 281         .s2div          = icst307_s2div,
 282         .idx2s          = icst307_idx2s,
 283 };
 284
 285 static void realview_oscvco_set(struct clk *clk, struct icst_vco vco)
 286 {
 287         void __iomem *sys_lock = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LOCK_OFFSET;
 288         u32 val;
 289
 290         val = readl(clk->vcoreg) & ~0x7ffff;
 291         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 292
 293         writel(0xa05f, sys_lock);
 294         writel(val, clk->vcoreg);
 295         writel(0, sys_lock);
 296 }
 297
 298 static const struct clk_ops oscvco_clk_ops = {
 299         .round  = icst_clk_round,
 300         .set    = icst_clk_set,
 301         .setvco = realview_oscvco_set,
 302 };
 303
 304 static struct clk oscvco_clk = {
 305         .ops    = &oscvco_clk_ops,
 306         .params = &realview_oscvco_params,
 307 };
 308
 309 /*
 310  * These are fixed clocks.
 311  */
 312 static struct clk ref24_clk = {
 313         .rate   = 24000000,
 314 };
 315
 316 static struct clk dummy_apb_pclk;
 317
 318 static struct clk_lookup lookups[] = {
 319         {       /* Bus clock */
 320                 .con_id         = "apb_pclk",
 321                 .clk            = &dummy_apb_pclk,
 322         }, {    /* UART0 */
 323                 .dev_id         = "dev:uart0",
 324                 .clk            = &ref24_clk,
 325         }, {    /* UART1 */
 326                 .dev_id         = "dev:uart1",
 327                 .clk            = &ref24_clk,
 328         }, {    /* UART2 */
 329                 .dev_id         = "dev:uart2",
 330                 .clk            = &ref24_clk,
 331         }, {    /* UART3 */
 332                 .dev_id         = "fpga:uart3",
 333                 .clk            = &ref24_clk,
 334         }, {    /* UART3 is on the dev chip in PB1176 */
 335                 .dev_id         = "dev:uart3",
 336                 .clk            = &ref24_clk,
 337         }, {    /* UART4 only exists in PB1176 */
 338                 .dev_id         = "fpga:uart4",
 339                 .clk            = &ref24_clk,
 340         }, {    /* KMI0 */
 341                 .dev_id         = "fpga:kmi0",
 342                 .clk            = &ref24_clk,
 343         }, {    /* KMI1 */
 344                 .dev_id         = "fpga:kmi1",
 345                 .clk            = &ref24_clk,
 346         }, {    /* MMC0 */
 347                 .dev_id         = "fpga:mmc0",
 348                 .clk            = &ref24_clk,
 349         }, {    /* CLCD is in the PB1176 and EB DevChip */
 350                 .dev_id         = "dev:clcd",
 351                 .clk            = &oscvco_clk,
 352         }, {    /* PB:CLCD */
 353                 .dev_id         = "issp:clcd",
 354                 .clk            = &oscvco_clk,
 355         }, {    /* SSP */
 356                 .dev_id         = "dev:ssp0",
 357                 .clk            = &ref24_clk,
 358         }
 359 };
 360
 361 static int __init clk_init(void)
 362 {
 363         if (machine_is_realview_pb1176())
 364                 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC0_OFFSET;
 365         else
 366                 oscvco_clk.vcoreg = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_OSC4_OFFSET;
 367
 368         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 369
 370         return 0;
 371 }
 372 core_initcall(clk_init);
 373
 374 /*
 375  * CLCD support.
 376  */
 377 #define SYS_CLCD_NLCDIOON       (1 << 2)
 378 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 379 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 380 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 381 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 382 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 383 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 384 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 385 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 386
 387 static struct clcd_panel vga = {
 388         .mode           = {
 389                 .name           = "VGA",
 390                 .refresh        = 60,
 391                 .xres           = 640,
 392                 .yres           = 480,
 393                 .pixclock       = 39721,
 394                 .left_margin    = 40,
 395                 .right_margin   = 24,
 396                 .upper_margin   = 32,
 397                 .lower_margin   = 11,
 398                 .hsync_len      = 96,
 399                 .vsync_len      = 2,
 400                 .sync           = 0,
 401                 .vmode          = FB_VMODE_NONINTERLACED,
 402         },
 403         .width          = -1,
 404         .height         = -1,
 405         .tim2           = TIM2_BCD | TIM2_IPC,
 406         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 407         .bpp            = 16,
 408 };
 409
 410 static struct clcd_panel xvga = {
 411         .mode           = {
 412                 .name           = "XVGA",
 413                 .refresh        = 60,
 414                 .xres           = 1024,
 415                 .yres           = 768,
 416                 .pixclock       = 15748,
 417                 .left_margin    = 152,
 418                 .right_margin   = 48,
 419                 .upper_margin   = 23,
 420                 .lower_margin   = 3,
 421                 .hsync_len      = 104,
 422                 .vsync_len      = 4,
 423                 .sync           = 0,
 424                 .vmode          = FB_VMODE_NONINTERLACED,
 425         },
 426         .width          = -1,
 427         .height         = -1,
 428         .tim2           = TIM2_BCD | TIM2_IPC,
 429         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 430         .bpp            = 16,
 431 };
 432
 433 static struct clcd_panel sanyo_3_8_in = {
 434         .mode           = {
 435                 .name           = "Sanyo QVGA",
 436                 .refresh        = 116,
 437                 .xres           = 320,
 438                 .yres           = 240,
 439                 .pixclock       = 100000,
 440                 .left_margin    = 6,
 441                 .right_margin   = 6,
 442                 .upper_margin   = 5,
 443                 .lower_margin   = 5,
 444                 .hsync_len      = 6,
 445                 .vsync_len      = 6,
 446                 .sync           = 0,
 447                 .vmode          = FB_VMODE_NONINTERLACED,
 448         },
 449         .width          = -1,
 450         .height         = -1,
 451         .tim2           = TIM2_BCD,
 452         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 453         .bpp            = 16,
 454 };
 455
 456 static struct clcd_panel sanyo_2_5_in = {
 457         .mode           = {
 458                 .name           = "Sanyo QVGA Portrait",
 459                 .refresh        = 116,
 460                 .xres           = 240,
 461                 .yres           = 320,
 462                 .pixclock       = 100000,
 463                 .left_margin    = 20,
 464                 .right_margin   = 10,
 465                 .upper_margin   = 2,
 466                 .lower_margin   = 2,
 467                 .hsync_len      = 10,
 468                 .vsync_len      = 2,
 469                 .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 470                 .vmode          = FB_VMODE_NONINTERLACED,
 471         },
 472         .width          = -1,
 473         .height         = -1,
 474         .tim2           = TIM2_IVS | TIM2_IHS | TIM2_IPC,
 475         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 476         .bpp            = 16,
 477 };
 478
 479 static struct clcd_panel epson_2_2_in = {
 480         .mode           = {
 481                 .name           = "Epson QCIF",
 482                 .refresh        = 390,
 483                 .xres           = 176,
 484                 .yres           = 220,
 485                 .pixclock       = 62500,
 486                 .left_margin    = 3,
 487                 .right_margin   = 2,
 488                 .upper_margin   = 1,
 489                 .lower_margin   = 0,
 490                 .hsync_len      = 3,
 491                 .vsync_len      = 2,
 492                 .sync           = 0,
 493                 .vmode          = FB_VMODE_NONINTERLACED,
 494         },
 495         .width          = -1,
 496         .height         = -1,
 497         .tim2           = TIM2_BCD | TIM2_IPC,
 498         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 499         .bpp            = 16,
 500 };
 501
 502 /*
 503  * Detect which LCD panel is connected, and return the appropriate
 504  * clcd_panel structure.  Note: we do not have any information on
 505  * the required timings for the 8.4in panel, so we presently assume
 506  * VGA timings.
 507  */
 508 static struct clcd_panel *realview_clcd_panel(void)
 509 {
 510         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 511         struct clcd_panel *vga_panel;
 512         struct clcd_panel *panel;
 513         u32 val;
 514
 515         if (machine_is_realview_eb())
 516                 vga_panel = &vga;
 517         else
 518                 vga_panel = &xvga;
 519
 520         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 521         if (val == SYS_CLCD_ID_SANYO_3_8)
 522                 panel = &sanyo_3_8_in;
 523         else if (val == SYS_CLCD_ID_SANYO_2_5)
 524                 panel = &sanyo_2_5_in;
 525         else if (val == SYS_CLCD_ID_EPSON_2_2)
 526                 panel = &epson_2_2_in;
 527         else if (val == SYS_CLCD_ID_VGA)
 528                 panel = vga_panel;
 529         else {
 530                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 531                         val);
 532                 panel = vga_panel;
 533         }
 534
 535         return panel;
 536 }
 537
 538 /*
 539  * Disable all display connectors on the interface module.
 540  */
 541 static void realview_clcd_disable(struct clcd_fb *fb)
 542 {
 543         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 544         u32 val;
 545
 546         val = readl(sys_clcd);
 547         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 548         writel(val, sys_clcd);
 549 }
 550
 551 /*
 552  * Enable the relevant connector on the interface module.
 553  */
 554 static void realview_clcd_enable(struct clcd_fb *fb)
 555 {
 556         void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET;
 557         u32 val;
 558
 559         /*
 560          * Enable the PSUs
 561          */
 562         val = readl(sys_clcd);
 563         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 564         writel(val, sys_clcd);
 565 }
 566
 567 static int realview_clcd_setup(struct clcd_fb *fb)
 568 {
 569         unsigned long framesize;
 570         dma_addr_t dma;
 571
 572         if (machine_is_realview_eb())
 573                 /* VGA, 16bpp */
 574                 framesize = 640 * 480 * 2;
 575         else
 576                 /* XVGA, 16bpp */
 577                 framesize = 1024 * 768 * 2;
 578
 579         fb->panel               = realview_clcd_panel();
 580
 581         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 582                                                     &dma, GFP_KERNEL | GFP_DMA);
 583         if (!fb->fb.screen_base) {
 584                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 585                 return -ENOMEM;
 586         }
 587
 588         fb->fb.fix.smem_start   = dma;
 589         fb->fb.fix.smem_len     = framesize;
 590
 591         return 0;
 592 }
 593
 594 static int realview_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 595 {
 596         return dma_mmap_writecombine(&fb->dev->dev, vma,
 597                                      fb->fb.screen_base,
 598                                      fb->fb.fix.smem_start,
 599                                      fb->fb.fix.smem_len);
 600 }
 601
 602 static void realview_clcd_remove(struct clcd_fb *fb)
 603 {
 604         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 605                               fb->fb.screen_base, fb->fb.fix.smem_start);
 606 }
 607
 608 struct clcd_board clcd_plat_data = {
 609         .name           = "RealView",
 610         .check          = clcdfb_check,
 611         .decode         = clcdfb_decode,
 612         .disable        = realview_clcd_disable,
 613         .enable         = realview_clcd_enable,
 614         .setup          = realview_clcd_setup,
 615         .mmap           = realview_clcd_mmap,
 616         .remove         = realview_clcd_remove,
 617 };
 618
 619 #ifdef CONFIG_LEDS
 620 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 621
 622 void realview_leds_event(led_event_t ledevt)
 623 {
 624         unsigned long flags;
 625         u32 val;
 626         u32 led = 1 << smp_processor_id();
 627
 628         local_irq_save(flags);
 629         val = readl(VA_LEDS_BASE);
 630
 631         switch (ledevt) {
 632         case led_idle_start:
 633                 val = val & ~led;
 634                 break;
 635
 636         case led_idle_end:
 637                 val = val | led;
 638                 break;
 639
 640         case led_timer:
 641                 val = val ^ REALVIEW_SYS_LED7;
 642                 break;
 643
 644         case led_halted:
 645                 val = 0;
 646                 break;
 647
 648         default:
 649                 break;
 650         }
 651
 652         writel(val, VA_LEDS_BASE);
 653         local_irq_restore(flags);
 654 }
 655 #endif  /* CONFIG_LEDS */
 656
 657 /*
 658  * Where is the timer (VA)?
 659  */
 660 void __iomem *timer0_va_base;
 661 void __iomem *timer1_va_base;
 662 void __iomem *timer2_va_base;
 663 void __iomem *timer3_va_base;
 664
 665 /*
 666  * Set up the clock source and clock events devices
 667  */
 668 void __init realview_timer_init(unsigned int timer_irq)
 669 {
 670         u32 val;
 671
 672         /*
 673          * set clock frequency:
 674          *      REALVIEW_REFCLK is 32KHz
 675          *      REALVIEW_TIMCLK is 1MHz
 676          */
 677         val = readl(__io_address(REALVIEW_SCTL_BASE));
 678         writel((REALVIEW_TIMCLK << REALVIEW_TIMER1_EnSel) |
 679                (REALVIEW_TIMCLK << REALVIEW_TIMER2_EnSel) |
 680                (REALVIEW_TIMCLK << REALVIEW_TIMER3_EnSel) |
 681                (REALVIEW_TIMCLK << REALVIEW_TIMER4_EnSel) | val,
 682                __io_address(REALVIEW_SCTL_BASE));
 683
 684         /*
 685          * Initialise to a known state (all timers off)
 686          */
 687         writel(0, timer0_va_base + TIMER_CTRL);
 688         writel(0, timer1_va_base + TIMER_CTRL);
 689         writel(0, timer2_va_base + TIMER_CTRL);
 690         writel(0, timer3_va_base + TIMER_CTRL);
 691
 692         sp804_clocksource_init(timer3_va_base);
 693         sp804_clockevents_init(timer0_va_base, timer_irq);
 694 }
 695
 696 /*
 697  * Setup the memory banks.
 698  */
 699 void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 700                     struct meminfo *meminfo)
 701 {
 702         /*
 703          * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
 704          * Half of this is mirrored at 0.
 705          */
 706 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
 707         meminfo->bank[0].start = 0x70000000;
 708         meminfo->bank[0].size = SZ_512M;
 709         meminfo->nr_banks = 1;
 710 #else
 711         meminfo->bank[0].start = 0;
 712         meminfo->bank[0].size = SZ_256M;
 713         meminfo->nr_banks = 1;
 714 #endif
 715 }