1 /* linux/arch/arm/mach-s3c2440/dma.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2440 DMA selection
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/serial_core.h>
23 #include <plat/dma-s3c24xx.h>
26 #include <plat/regs-serial.h>
27 #include <mach/regs-gpio.h>
28 #include <plat/regs-ac97.h>
29 #include <plat/regs-dma.h>
30 #include <mach/regs-lcd.h>
31 #include <plat/regs-iis.h>
32 #include <plat/regs-spi.h>
34 static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
37 .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
41 .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
45 .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
46 .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
47 .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
48 .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
52 .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
56 .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
60 .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
64 .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
68 .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
72 .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
73 .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
74 .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
78 .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
79 .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
83 .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
84 .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
88 .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
89 .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
93 .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
94 .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
98 .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
99 .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
103 .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
107 .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
111 .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
115 .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
119 static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
120 struct s3c24xx_dma_map *map)
122 chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
125 static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
126 .select = s3c2440_dma_select,
127 .dcon_mask = 7 << 24,
128 .map = s3c2440_dma_mappings,
129 .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
132 static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
136 [0] = 3 | DMA_CH_VALID,
137 [1] = 2 | DMA_CH_VALID,
138 [2] = 1 | DMA_CH_VALID,
139 [3] = 0 | DMA_CH_VALID,
144 [0] = 1 | DMA_CH_VALID,
145 [1] = 2 | DMA_CH_VALID,
150 [0] = 2 | DMA_CH_VALID,
151 [1] = 1 | DMA_CH_VALID,
156 [0] = 2 | DMA_CH_VALID,
157 [1] = 1 | DMA_CH_VALID,
162 [0] = 1 | DMA_CH_VALID,
163 [1] = 3 | DMA_CH_VALID,
168 [0] = 3 | DMA_CH_VALID,
169 [1] = 2 | DMA_CH_VALID,
175 static int __init s3c2440_dma_add(struct device *dev,
176 struct subsys_interface *sif)
179 s3c24xx_dma_order_set(&s3c2440_dma_order);
180 return s3c24xx_dma_init_map(&s3c2440_dma_sel);
183 static struct subsys_interface s3c2440_dma_interface = {
184 .name = "s3c2440_dma",
185 .subsys = &s3c2440_subsys,
186 .add_dev = s3c2440_dma_add,
189 static int __init s3c2440_dma_init(void)
191 return subsys_interface_register(&s3c2440_dma_interface);
194 arch_initcall(s3c2440_dma_init);