1 /* linux/arch/arm/mach-s5pc100/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PC100 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30 #include <plat/s5pc100.h>
32 static struct clk s5p_clk_otgphy = {
36 static struct clk dummy_apb_pclk = {
41 static struct clk *clk_src_mout_href_list[] = {
46 static struct clksrc_sources clk_src_mout_href = {
47 .sources = clk_src_mout_href_list,
48 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
51 static struct clksrc_clk clk_mout_href = {
55 .sources = &clk_src_mout_href,
56 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
59 static struct clk *clk_src_mout_48m_list[] = {
61 [1] = &s5p_clk_otgphy,
64 static struct clksrc_sources clk_src_mout_48m = {
65 .sources = clk_src_mout_48m_list,
66 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
69 static struct clksrc_clk clk_mout_48m = {
73 .sources = &clk_src_mout_48m,
74 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
77 static struct clksrc_clk clk_mout_mpll = {
81 .sources = &clk_src_mpll,
82 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
86 static struct clksrc_clk clk_mout_apll = {
90 .sources = &clk_src_apll,
91 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
94 static struct clksrc_clk clk_mout_epll = {
98 .sources = &clk_src_epll,
99 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
102 static struct clk *clk_src_mout_hpll_list[] = {
106 static struct clksrc_sources clk_src_mout_hpll = {
107 .sources = clk_src_mout_hpll_list,
108 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
111 static struct clksrc_clk clk_mout_hpll = {
115 .sources = &clk_src_mout_hpll,
116 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
119 static struct clksrc_clk clk_div_apll = {
122 .parent = &clk_mout_apll.clk,
124 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
127 static struct clksrc_clk clk_div_arm = {
130 .parent = &clk_div_apll.clk,
132 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
135 static struct clksrc_clk clk_div_d0_bus = {
137 .name = "div_d0_bus",
138 .parent = &clk_div_arm.clk,
140 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
143 static struct clksrc_clk clk_div_pclkd0 = {
145 .name = "div_pclkd0",
146 .parent = &clk_div_d0_bus.clk,
148 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
151 static struct clksrc_clk clk_div_secss = {
154 .parent = &clk_div_d0_bus.clk,
156 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
159 static struct clksrc_clk clk_div_apll2 = {
162 .parent = &clk_mout_apll.clk,
164 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
167 static struct clk *clk_src_mout_am_list[] = {
168 [0] = &clk_mout_mpll.clk,
169 [1] = &clk_div_apll2.clk,
172 struct clksrc_sources clk_src_mout_am = {
173 .sources = clk_src_mout_am_list,
174 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
177 static struct clksrc_clk clk_mout_am = {
181 .sources = &clk_src_mout_am,
182 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
185 static struct clksrc_clk clk_div_d1_bus = {
187 .name = "div_d1_bus",
188 .parent = &clk_mout_am.clk,
190 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
193 static struct clksrc_clk clk_div_mpll2 = {
196 .parent = &clk_mout_am.clk,
198 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
201 static struct clksrc_clk clk_div_mpll = {
204 .parent = &clk_mout_am.clk,
206 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
209 static struct clk *clk_src_mout_onenand_list[] = {
210 [0] = &clk_div_d0_bus.clk,
211 [1] = &clk_div_d1_bus.clk,
214 struct clksrc_sources clk_src_mout_onenand = {
215 .sources = clk_src_mout_onenand_list,
216 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
219 static struct clksrc_clk clk_mout_onenand = {
221 .name = "mout_onenand",
223 .sources = &clk_src_mout_onenand,
224 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
227 static struct clksrc_clk clk_div_onenand = {
229 .name = "div_onenand",
230 .parent = &clk_mout_onenand.clk,
232 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
235 static struct clksrc_clk clk_div_pclkd1 = {
237 .name = "div_pclkd1",
238 .parent = &clk_div_d1_bus.clk,
240 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
243 static struct clksrc_clk clk_div_cam = {
246 .parent = &clk_div_mpll2.clk,
248 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
251 static struct clksrc_clk clk_div_hdmi = {
254 .parent = &clk_mout_hpll.clk,
256 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
259 static u32 epll_div[][4] = {
260 { 32750000, 131, 3, 4 },
261 { 32768000, 131, 3, 4 },
262 { 36000000, 72, 3, 3 },
263 { 45000000, 90, 3, 3 },
264 { 45158000, 90, 3, 3 },
265 { 45158400, 90, 3, 3 },
266 { 48000000, 96, 3, 3 },
267 { 49125000, 131, 4, 3 },
268 { 49152000, 131, 4, 3 },
269 { 60000000, 120, 3, 3 },
270 { 67737600, 226, 5, 3 },
271 { 67738000, 226, 5, 3 },
272 { 73800000, 246, 5, 3 },
273 { 73728000, 246, 5, 3 },
274 { 72000000, 144, 3, 3 },
275 { 84000000, 168, 3, 3 },
276 { 96000000, 96, 3, 2 },
277 { 144000000, 144, 3, 2 },
278 { 192000000, 96, 3, 1 }
281 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
283 unsigned int epll_con;
286 if (clk->rate == rate) /* Return if nothing changed */
289 epll_con = __raw_readl(S5P_EPLL_CON);
291 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
293 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
294 if (epll_div[i][0] == rate) {
295 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
296 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
297 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
302 if (i == ARRAY_SIZE(epll_div)) {
303 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
307 __raw_writel(epll_con, S5P_EPLL_CON);
309 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
317 static struct clk_ops s5pc100_epll_ops = {
318 .get_rate = s5p_epll_get_rate,
319 .set_rate = s5pc100_epll_set_rate,
322 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
324 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
327 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
329 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
332 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
334 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
337 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
339 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
342 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
344 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
347 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
349 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
352 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
354 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
357 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
359 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
362 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
364 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
367 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
369 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
372 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
374 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
378 * The following clocks will be disabled during clock initialization. It is
379 * recommended to keep the following clocks disabled until the driver requests
380 * for enabling the clock.
382 static struct clk init_clocks_off[] = {
385 .parent = &clk_div_d0_bus.clk,
386 .enable = s5pc100_d0_0_ctrl,
390 .parent = &clk_div_d0_bus.clk,
391 .enable = s5pc100_d0_0_ctrl,
395 .parent = &clk_div_d0_bus.clk,
396 .enable = s5pc100_d0_0_ctrl,
400 .parent = &clk_div_d0_bus.clk,
401 .enable = s5pc100_d0_0_ctrl,
405 .parent = &clk_div_d0_bus.clk,
406 .enable = s5pc100_d0_0_ctrl,
410 .parent = &clk_div_d0_bus.clk,
411 .enable = s5pc100_d0_1_ctrl,
415 .parent = &clk_div_d0_bus.clk,
416 .enable = s5pc100_d0_1_ctrl,
420 .parent = &clk_div_d0_bus.clk,
421 .enable = s5pc100_d0_2_ctrl,
425 .parent = &clk_div_d0_bus.clk,
426 .enable = s5pc100_d0_2_ctrl,
430 .devname = "s3c-sdhci.2",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
436 .devname = "s3c-sdhci.1",
437 .parent = &clk_div_d1_bus.clk,
438 .enable = s5pc100_d1_0_ctrl,
442 .devname = "s3c-sdhci.0",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
448 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl,
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
458 .parent = &clk_div_d1_bus.clk,
459 .enable = s5pc100_d1_0_ctrl,
463 .devname = "dma-pl330.1",
464 .parent = &clk_div_d1_bus.clk,
465 .enable = s5pc100_d1_0_ctrl,
469 .devname = "dma-pl330.0",
470 .parent = &clk_div_d1_bus.clk,
471 .enable = s5pc100_d1_0_ctrl,
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
480 .parent = &clk_div_d1_bus.clk,
481 .enable = s5pc100_d1_1_ctrl,
485 .devname = "s5p-fimc.0",
486 .parent = &clk_div_d1_bus.clk,
487 .enable = s5pc100_d1_1_ctrl,
491 .devname = "s5p-fimc.1",
492 .parent = &clk_div_d1_bus.clk,
493 .enable = s5pc100_d1_1_ctrl,
497 .devname = "s5p-fimc.2",
498 .enable = s5pc100_d1_1_ctrl,
502 .parent = &clk_div_d1_bus.clk,
503 .enable = s5pc100_d1_1_ctrl,
507 .parent = &clk_div_d1_bus.clk,
508 .enable = s5pc100_d1_1_ctrl,
512 .parent = &clk_div_d1_bus.clk,
513 .enable = s5pc100_d1_1_ctrl,
517 .parent = &clk_div_d1_bus.clk,
518 .enable = s5pc100_d1_0_ctrl,
522 .parent = &clk_div_d1_bus.clk,
523 .enable = s5pc100_d1_2_ctrl,
527 .parent = &clk_div_d1_bus.clk,
528 .enable = s5pc100_d1_2_ctrl,
532 .parent = &clk_div_d1_bus.clk,
533 .enable = s5pc100_d1_2_ctrl,
537 .parent = &clk_div_d1_bus.clk,
538 .enable = s5pc100_d1_2_ctrl,
542 .parent = &clk_div_d1_bus.clk,
543 .enable = s5pc100_d1_2_ctrl,
547 .parent = &clk_div_d1_bus.clk,
548 .enable = s5pc100_d1_3_ctrl,
552 .parent = &clk_div_d1_bus.clk,
553 .enable = s5pc100_d1_3_ctrl,
557 .parent = &clk_div_d1_bus.clk,
558 .enable = s5pc100_d1_3_ctrl,
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_3_ctrl,
567 .parent = &clk_div_d1_bus.clk,
568 .enable = s5pc100_d1_3_ctrl,
572 .devname = "s3c2440-i2c.0",
573 .parent = &clk_div_d1_bus.clk,
574 .enable = s5pc100_d1_4_ctrl,
578 .devname = "s3c2440-i2c.1",
579 .parent = &clk_div_d1_bus.clk,
580 .enable = s5pc100_d1_4_ctrl,
584 .devname = "s3c64xx-spi.0",
585 .parent = &clk_div_d1_bus.clk,
586 .enable = s5pc100_d1_4_ctrl,
590 .devname = "s3c64xx-spi.1",
591 .parent = &clk_div_d1_bus.clk,
592 .enable = s5pc100_d1_4_ctrl,
596 .devname = "s3c64xx-spi.2",
597 .parent = &clk_div_d1_bus.clk,
598 .enable = s5pc100_d1_4_ctrl,
602 .parent = &clk_div_d1_bus.clk,
603 .enable = s5pc100_d1_4_ctrl,
607 .parent = &clk_div_d1_bus.clk,
608 .enable = s5pc100_d1_4_ctrl,
609 .ctrlbit = (1 << 10),
612 .parent = &clk_div_d1_bus.clk,
613 .enable = s5pc100_d1_4_ctrl,
614 .ctrlbit = (1 << 11),
617 .parent = &clk_div_d1_bus.clk,
618 .enable = s5pc100_d1_4_ctrl,
619 .ctrlbit = (1 << 12),
622 .parent = &clk_div_d1_bus.clk,
623 .enable = s5pc100_d1_4_ctrl,
624 .ctrlbit = (1 << 13),
627 .devname = "samsung-i2s.0",
628 .parent = &clk_div_pclkd1.clk,
629 .enable = s5pc100_d1_5_ctrl,
633 .devname = "samsung-i2s.1",
634 .parent = &clk_div_pclkd1.clk,
635 .enable = s5pc100_d1_5_ctrl,
639 .devname = "samsung-i2s.2",
640 .parent = &clk_div_pclkd1.clk,
641 .enable = s5pc100_d1_5_ctrl,
645 .parent = &clk_div_pclkd1.clk,
646 .enable = s5pc100_d1_5_ctrl,
650 .devname = "samsung-pcm.0",
651 .parent = &clk_div_pclkd1.clk,
652 .enable = s5pc100_d1_5_ctrl,
656 .devname = "samsung-pcm.1",
657 .parent = &clk_div_pclkd1.clk,
658 .enable = s5pc100_d1_5_ctrl,
662 .parent = &clk_div_pclkd1.clk,
663 .enable = s5pc100_d1_5_ctrl,
667 .parent = &clk_div_pclkd1.clk,
668 .enable = s5pc100_d1_5_ctrl,
672 .parent = &clk_div_pclkd1.clk,
673 .enable = s5pc100_d1_5_ctrl,
677 .devname = "s3c64xx-spi.0",
678 .parent = &clk_mout_48m.clk,
679 .enable = s5pc100_sclk0_ctrl,
683 .devname = "s3c64xx-spi.1",
684 .parent = &clk_mout_48m.clk,
685 .enable = s5pc100_sclk0_ctrl,
689 .devname = "s3c64xx-spi.2",
690 .parent = &clk_mout_48m.clk,
691 .enable = s5pc100_sclk0_ctrl,
695 .devname = "s3c-sdhci.0",
696 .parent = &clk_mout_48m.clk,
697 .enable = s5pc100_sclk0_ctrl,
698 .ctrlbit = (1 << 15),
701 .devname = "s3c-sdhci.1",
702 .parent = &clk_mout_48m.clk,
703 .enable = s5pc100_sclk0_ctrl,
704 .ctrlbit = (1 << 16),
707 .devname = "s3c-sdhci.2",
708 .parent = &clk_mout_48m.clk,
709 .enable = s5pc100_sclk0_ctrl,
710 .ctrlbit = (1 << 17),
714 static struct clk clk_vclk54m = {
719 static struct clk clk_i2scdclk0 = {
720 .name = "i2s_cdclk0",
723 static struct clk clk_i2scdclk1 = {
724 .name = "i2s_cdclk1",
727 static struct clk clk_i2scdclk2 = {
728 .name = "i2s_cdclk2",
731 static struct clk clk_pcmcdclk0 = {
732 .name = "pcm_cdclk0",
735 static struct clk clk_pcmcdclk1 = {
736 .name = "pcm_cdclk1",
739 static struct clk *clk_src_group1_list[] = {
740 [0] = &clk_mout_epll.clk,
741 [1] = &clk_div_mpll2.clk,
743 [3] = &clk_mout_hpll.clk,
746 struct clksrc_sources clk_src_group1 = {
747 .sources = clk_src_group1_list,
748 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
751 static struct clk *clk_src_group2_list[] = {
752 [0] = &clk_mout_epll.clk,
753 [1] = &clk_div_mpll.clk,
756 struct clksrc_sources clk_src_group2 = {
757 .sources = clk_src_group2_list,
758 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
761 static struct clk *clk_src_group3_list[] = {
762 [0] = &clk_mout_epll.clk,
763 [1] = &clk_div_mpll.clk,
765 [3] = &clk_i2scdclk0,
766 [4] = &clk_pcmcdclk0,
767 [5] = &clk_mout_hpll.clk,
770 struct clksrc_sources clk_src_group3 = {
771 .sources = clk_src_group3_list,
772 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
775 static struct clksrc_clk clk_sclk_audio0 = {
777 .name = "sclk_audio",
778 .devname = "samsung-pcm.0",
780 .enable = s5pc100_sclk1_ctrl,
782 .sources = &clk_src_group3,
783 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
784 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
787 static struct clk *clk_src_group4_list[] = {
788 [0] = &clk_mout_epll.clk,
789 [1] = &clk_div_mpll.clk,
791 [3] = &clk_i2scdclk1,
792 [4] = &clk_pcmcdclk1,
793 [5] = &clk_mout_hpll.clk,
796 struct clksrc_sources clk_src_group4 = {
797 .sources = clk_src_group4_list,
798 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
801 static struct clksrc_clk clk_sclk_audio1 = {
803 .name = "sclk_audio",
804 .devname = "samsung-pcm.1",
806 .enable = s5pc100_sclk1_ctrl,
808 .sources = &clk_src_group4,
809 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
810 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
813 static struct clk *clk_src_group5_list[] = {
814 [0] = &clk_mout_epll.clk,
815 [1] = &clk_div_mpll.clk,
817 [3] = &clk_i2scdclk2,
818 [4] = &clk_mout_hpll.clk,
821 struct clksrc_sources clk_src_group5 = {
822 .sources = clk_src_group5_list,
823 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
826 static struct clksrc_clk clk_sclk_audio2 = {
828 .name = "sclk_audio",
829 .devname = "samsung-pcm.2",
830 .ctrlbit = (1 << 10),
831 .enable = s5pc100_sclk1_ctrl,
833 .sources = &clk_src_group5,
834 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
835 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
838 static struct clk *clk_src_group6_list[] = {
841 [2] = &clk_div_hdmi.clk,
844 struct clksrc_sources clk_src_group6 = {
845 .sources = clk_src_group6_list,
846 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
849 static struct clk *clk_src_group7_list[] = {
850 [0] = &clk_mout_epll.clk,
851 [1] = &clk_div_mpll.clk,
852 [2] = &clk_mout_hpll.clk,
856 struct clksrc_sources clk_src_group7 = {
857 .sources = clk_src_group7_list,
858 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
861 static struct clk *clk_src_mmc0_list[] = {
862 [0] = &clk_mout_epll.clk,
863 [1] = &clk_div_mpll.clk,
867 struct clksrc_sources clk_src_mmc0 = {
868 .sources = clk_src_mmc0_list,
869 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
872 static struct clk *clk_src_mmc12_list[] = {
873 [0] = &clk_mout_epll.clk,
874 [1] = &clk_div_mpll.clk,
876 [3] = &clk_mout_hpll.clk,
879 struct clksrc_sources clk_src_mmc12 = {
880 .sources = clk_src_mmc12_list,
881 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
884 static struct clk *clk_src_irda_usb_list[] = {
885 [0] = &clk_mout_epll.clk,
886 [1] = &clk_div_mpll.clk,
888 [3] = &clk_mout_hpll.clk,
891 struct clksrc_sources clk_src_irda_usb = {
892 .sources = clk_src_irda_usb_list,
893 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
896 static struct clk *clk_src_pwi_list[] = {
898 [1] = &clk_mout_epll.clk,
899 [2] = &clk_div_mpll.clk,
902 struct clksrc_sources clk_src_pwi = {
903 .sources = clk_src_pwi_list,
904 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
907 static struct clk *clk_sclk_spdif_list[] = {
908 [0] = &clk_sclk_audio0.clk,
909 [1] = &clk_sclk_audio1.clk,
910 [2] = &clk_sclk_audio2.clk,
913 struct clksrc_sources clk_src_sclk_spdif = {
914 .sources = clk_sclk_spdif_list,
915 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
918 static struct clksrc_clk clk_sclk_spdif = {
920 .name = "sclk_spdif",
921 .ctrlbit = (1 << 11),
922 .enable = s5pc100_sclk1_ctrl,
923 .ops = &s5p_sclk_spdif_ops,
925 .sources = &clk_src_sclk_spdif,
926 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
929 static struct clksrc_clk clksrcs[] = {
933 .devname = "s3c64xx-spi.0",
935 .enable = s5pc100_sclk0_ctrl,
938 .sources = &clk_src_group1,
939 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
940 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
944 .devname = "s3c64xx-spi.1",
946 .enable = s5pc100_sclk0_ctrl,
949 .sources = &clk_src_group1,
950 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
951 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
955 .devname = "s3c64xx-spi.2",
957 .enable = s5pc100_sclk0_ctrl,
960 .sources = &clk_src_group1,
961 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
962 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
967 .enable = s5pc100_sclk0_ctrl,
970 .sources = &clk_src_group2,
971 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
972 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
975 .name = "sclk_mixer",
977 .enable = s5pc100_sclk0_ctrl,
980 .sources = &clk_src_group6,
981 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
986 .enable = s5pc100_sclk1_ctrl,
989 .sources = &clk_src_group7,
990 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
991 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
995 .devname = "s5p-fimc.0",
997 .enable = s5pc100_sclk1_ctrl,
1000 .sources = &clk_src_group7,
1001 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
1002 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
1005 .name = "sclk_fimc",
1006 .devname = "s5p-fimc.1",
1007 .ctrlbit = (1 << 2),
1008 .enable = s5pc100_sclk1_ctrl,
1011 .sources = &clk_src_group7,
1012 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
1013 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
1016 .name = "sclk_fimc",
1017 .devname = "s5p-fimc.2",
1018 .ctrlbit = (1 << 3),
1019 .enable = s5pc100_sclk1_ctrl,
1022 .sources = &clk_src_group7,
1023 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1024 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1028 .devname = "s3c-sdhci.0",
1029 .ctrlbit = (1 << 12),
1030 .enable = s5pc100_sclk1_ctrl,
1033 .sources = &clk_src_mmc0,
1034 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1035 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1039 .devname = "s3c-sdhci.1",
1040 .ctrlbit = (1 << 13),
1041 .enable = s5pc100_sclk1_ctrl,
1044 .sources = &clk_src_mmc12,
1045 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1046 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1050 .devname = "s3c-sdhci.2",
1051 .ctrlbit = (1 << 14),
1052 .enable = s5pc100_sclk1_ctrl,
1055 .sources = &clk_src_mmc12,
1056 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1057 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1060 .name = "sclk_irda",
1061 .ctrlbit = (1 << 10),
1062 .enable = s5pc100_sclk0_ctrl,
1065 .sources = &clk_src_irda_usb,
1066 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1067 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1070 .name = "sclk_irda",
1071 .ctrlbit = (1 << 10),
1072 .enable = s5pc100_sclk0_ctrl,
1075 .sources = &clk_src_mmc12,
1076 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1077 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1081 .ctrlbit = (1 << 1),
1082 .enable = s5pc100_sclk0_ctrl,
1085 .sources = &clk_src_pwi,
1086 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1087 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1090 .name = "sclk_uhost",
1091 .ctrlbit = (1 << 11),
1092 .enable = s5pc100_sclk0_ctrl,
1095 .sources = &clk_src_irda_usb,
1096 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1097 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1101 /* Clock initialisation code */
1102 static struct clksrc_clk *sysclks[] = {
1130 void __init_or_cpufreq s5pc100_setup_clocks(void)
1134 unsigned long hclkd0;
1135 unsigned long hclkd1;
1136 unsigned long pclkd0;
1137 unsigned long pclkd1;
1144 /* Set S5PC100 functions for clk_fout_epll */
1145 clk_fout_epll.enable = s5p_epll_enable;
1146 clk_fout_epll.ops = &s5pc100_epll_ops;
1148 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1150 xtal = clk_get_rate(&clk_xtal);
1152 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1154 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1155 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1156 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1157 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1159 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1160 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1162 clk_fout_apll.rate = apll;
1163 clk_fout_mpll.rate = mpll;
1164 clk_fout_epll.rate = epll;
1165 clk_mout_hpll.clk.rate = hpll;
1167 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1168 s3c_set_clksrc(&clksrcs[ptr], true);
1170 arm = clk_get_rate(&clk_div_arm.clk);
1171 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1172 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1173 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1174 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1176 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1177 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1180 clk_h.rate = hclkd1;
1181 clk_p.rate = pclkd1;
1185 * The following clocks will be enabled during clock initialization.
1187 static struct clk init_clocks[] = {
1190 .parent = &clk_div_d0_bus.clk,
1191 .enable = s5pc100_d0_0_ctrl,
1192 .ctrlbit = (1 << 1),
1195 .parent = &clk_div_d0_bus.clk,
1196 .enable = s5pc100_d0_0_ctrl,
1197 .ctrlbit = (1 << 0),
1200 .parent = &clk_div_d0_bus.clk,
1201 .enable = s5pc100_d0_1_ctrl,
1202 .ctrlbit = (1 << 5),
1205 .parent = &clk_div_d0_bus.clk,
1206 .enable = s5pc100_d0_1_ctrl,
1207 .ctrlbit = (1 << 4),
1210 .parent = &clk_div_d0_bus.clk,
1211 .enable = s5pc100_d0_1_ctrl,
1212 .ctrlbit = (1 << 1),
1215 .parent = &clk_div_d0_bus.clk,
1216 .enable = s5pc100_d0_1_ctrl,
1217 .ctrlbit = (1 << 0),
1220 .parent = &clk_div_d0_bus.clk,
1221 .enable = s5pc100_d0_1_ctrl,
1222 .ctrlbit = (1 << 0),
1225 .parent = &clk_div_d1_bus.clk,
1226 .enable = s5pc100_d1_3_ctrl,
1227 .ctrlbit = (1 << 1),
1230 .devname = "s3c6400-uart.0",
1231 .parent = &clk_div_d1_bus.clk,
1232 .enable = s5pc100_d1_4_ctrl,
1233 .ctrlbit = (1 << 0),
1236 .devname = "s3c6400-uart.1",
1237 .parent = &clk_div_d1_bus.clk,
1238 .enable = s5pc100_d1_4_ctrl,
1239 .ctrlbit = (1 << 1),
1242 .devname = "s3c6400-uart.2",
1243 .parent = &clk_div_d1_bus.clk,
1244 .enable = s5pc100_d1_4_ctrl,
1245 .ctrlbit = (1 << 2),
1248 .devname = "s3c6400-uart.3",
1249 .parent = &clk_div_d1_bus.clk,
1250 .enable = s5pc100_d1_4_ctrl,
1251 .ctrlbit = (1 << 3),
1254 .parent = &clk_div_d1_bus.clk,
1255 .enable = s5pc100_d1_3_ctrl,
1256 .ctrlbit = (1 << 6),
1260 static struct clk *clks[] __initdata = {
1269 void __init s5pc100_register_clocks(void)
1273 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1275 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1276 s3c_register_clksrc(sysclks[ptr], 1);
1278 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1279 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1281 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1282 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1284 s3c24xx_register_clock(&dummy_apb_pclk);