arch/arm/mach-shmobile/board-bockw.c

   1 /*
   2  * Bock-W board support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/mfd/tmio.h>
  22 #include <linux/mmc/host.h>
  23 #include <linux/mmc/sh_mobile_sdhi.h>
  24 #include <linux/mmc/sh_mmcif.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/pinctrl/machine.h>
  27 #include <linux/platform_data/usb-rcar-phy.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/fixed.h>
  30 #include <linux/regulator/machine.h>
  31 #include <linux/smsc911x.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/spi/flash.h>
  34 #include <mach/common.h>
  35 #include <mach/irqs.h>
  36 #include <mach/r8a7778.h>
  37 #include <asm/mach/arch.h>
  38
  39 /*
  40  *      CN9(Upper side) SCIF/RCAN selection
  41  *
  42  *              1,4     3,6
  43  * SW40         SCIF    RCAN
  44  * SW41         SCIF    RCAN
  45  */
  46
  47 /*
  48  * MMC (CN26) pin
  49  *
  50  * SW6  (D2)    3 pin
  51  * SW7  (D5)    ON
  52  * SW8  (D3)    3 pin
  53  * SW10 (D4)    1 pin
  54  * SW12 (CLK)   1 pin
  55  * SW13 (D6)    3 pin
  56  * SW14 (CMD)   ON
  57  * SW15 (D6)    1 pin
  58  * SW16 (D0)    ON
  59  * SW17 (D1)    ON
  60  * SW18 (D7)    3 pin
  61  * SW19 (MMC)   1 pin
  62  */
  63
  64 /* Dummy supplies, where voltage doesn't matter */
  65 static struct regulator_consumer_supply dummy_supplies[] = {
  66         REGULATOR_SUPPLY("vddvario", "smsc911x"),
  67         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
  68 };
  69
  70 static struct smsc911x_platform_config smsc911x_data __initdata = {
  71         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
  72         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
  73         .flags          = SMSC911X_USE_32BIT,
  74         .phy_interface  = PHY_INTERFACE_MODE_MII,
  75 };
  76
  77 static struct resource smsc911x_resources[] __initdata = {
  78         DEFINE_RES_MEM(0x18300000, 0x1000),
  79         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
  80 };
  81
  82 /* USB */
  83 static struct resource usb_phy_resources[] __initdata = {
  84         DEFINE_RES_MEM(0xffe70800, 0x100),
  85         DEFINE_RES_MEM(0xffe76000, 0x100),
  86 };
  87
  88 static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
  89
  90 /* SDHI */
  91 static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
  92         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
  93         .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
  94         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
  95 };
  96
  97 static struct resource sdhi0_resources[] __initdata = {
  98         DEFINE_RES_MEM(0xFFE4C000, 0x100),
  99         DEFINE_RES_IRQ(gic_iid(0x77)),
 100 };
 101
 102 static struct sh_eth_plat_data ether_platform_data __initdata = {
 103         .phy            = 0x01,
 104         .edmac_endian   = EDMAC_LITTLE_ENDIAN,
 105         .register_type  = SH_ETH_REG_FAST_RCAR,
 106         .phy_interface  = PHY_INTERFACE_MODE_RMII,
 107         /*
 108          * Although the LINK signal is available on the board, it's connected to
 109          * the link/activity LED output of the PHY, thus the link disappears and
 110          * reappears after each packet.  We'd be better off ignoring such signal
 111          * and getting the link state from the PHY indirectly.
 112          */
 113         .no_ether_link  = 1,
 114 };
 115
 116 /* I2C */
 117 static struct i2c_board_info i2c0_devices[] = {
 118         {
 119                 I2C_BOARD_INFO("rx8581", 0x51),
 120         },
 121 };
 122
 123 /* HSPI*/
 124 static struct mtd_partition m25p80_spi_flash_partitions[] = {
 125         {
 126                 .name   = "data(spi)",
 127                 .size   = 0x0100000,
 128                 .offset = 0,
 129         },
 130 };
 131
 132 static struct flash_platform_data spi_flash_data = {
 133         .name           = "m25p80",
 134         .type           = "s25fl008k",
 135         .parts          = m25p80_spi_flash_partitions,
 136         .nr_parts       = ARRAY_SIZE(m25p80_spi_flash_partitions),
 137 };
 138
 139 static struct spi_board_info spi_board_info[] __initdata = {
 140         {
 141                 .modalias       = "m25p80",
 142                 .max_speed_hz   = 104000000,
 143                 .chip_select    = 0,
 144                 .bus_num        = 0,
 145                 .mode           = SPI_MODE_0,
 146                 .platform_data  = &spi_flash_data,
 147         },
 148 };
 149
 150 /* MMC */
 151 static struct resource mmc_resources[] __initdata = {
 152         DEFINE_RES_MEM(0xffe4e000, 0x100),
 153         DEFINE_RES_IRQ(gic_iid(0x5d)),
 154 };
 155
 156 static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = {
 157         .sup_pclk       = 0,
 158         .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
 159         .caps           = MMC_CAP_4_BIT_DATA |
 160                           MMC_CAP_8_BIT_DATA |
 161                           MMC_CAP_NEEDS_POLL,
 162 };
 163
 164 static const struct pinctrl_map bockw_pinctrl_map[] = {
 165         /* Ether */
 166         PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
 167                                   "ether_rmii", "ether"),
 168         /* HSPI0 */
 169         PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
 170                                   "hspi0_a", "hspi0"),
 171         /* MMC */
 172         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
 173                                   "mmc_data8", "mmc"),
 174         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
 175                                   "mmc_ctrl", "mmc"),
 176         /* SCIF0 */
 177         PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 178                                   "scif0_data_a", "scif0"),
 179         PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
 180                                   "scif0_ctrl", "scif0"),
 181         /* USB */
 182         PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
 183                                   "usb0", "usb0"),
 184         PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
 185                                   "usb1", "usb1"),
 186         /* SDHI0 */
 187         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 188                                   "sdhi0_data4", "sdhi0"),
 189         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 190                                   "sdhi0_ctrl", "sdhi0"),
 191         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 192                                   "sdhi0_cd", "sdhi0"),
 193         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
 194                                   "sdhi0_wp", "sdhi0"),
 195 };
 196
 197 #define FPGA    0x18200000
 198 #define IRQ0MR  0x30
 199 #define PFC     0xfffc0000
 200 #define PUPR4   0x110
 201 static void __init bockw_init(void)
 202 {
 203         void __iomem *base;
 204
 205         r8a7778_clock_init();
 206         r8a7778_init_irq_extpin(1);
 207         r8a7778_add_standard_devices();
 208         r8a7778_add_ether_device(&ether_platform_data);
 209
 210         i2c_register_board_info(0, i2c0_devices,
 211                                 ARRAY_SIZE(i2c0_devices));
 212         spi_register_board_info(spi_board_info,
 213                                 ARRAY_SIZE(spi_board_info));
 214         pinctrl_register_mappings(bockw_pinctrl_map,
 215                                   ARRAY_SIZE(bockw_pinctrl_map));
 216         r8a7778_pinmux_init();
 217
 218         platform_device_register_resndata(
 219                 &platform_bus, "sh_mmcif", -1,
 220                 mmc_resources, ARRAY_SIZE(mmc_resources),
 221                 &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data));
 222
 223         platform_device_register_resndata(
 224                 &platform_bus, "rcar_usb_phy", -1,
 225                 usb_phy_resources,
 226                 ARRAY_SIZE(usb_phy_resources),
 227                 &usb_phy_platform_data,
 228                 sizeof(struct rcar_phy_platform_data));
 229
 230
 231         /* for SMSC */
 232         base = ioremap_nocache(FPGA, SZ_1M);
 233         if (base) {
 234                 /*
 235                  * CAUTION
 236                  *
 237                  * IRQ0/1 is cascaded interrupt from FPGA.
 238                  * it should be cared in the future
 239                  * Now, it is assuming IRQ0 was used only from SMSC.
 240                  */
 241                 u16 val = ioread16(base + IRQ0MR);
 242                 val &= ~(1 << 4); /* enable SMSC911x */
 243                 iowrite16(val, base + IRQ0MR);
 244                 iounmap(base);
 245
 246                 regulator_register_fixed(0, dummy_supplies,
 247                                          ARRAY_SIZE(dummy_supplies));
 248
 249                 platform_device_register_resndata(
 250                         &platform_bus, "smsc911x", -1,
 251                         smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
 252                         &smsc911x_data, sizeof(smsc911x_data));
 253         }
 254
 255         /* for SDHI */
 256         base = ioremap_nocache(PFC, 0x200);
 257         if (base) {
 258                 /*
 259                  * FIXME
 260                  *
 261                  * SDHI CD/WP pin needs pull-up
 262                  */
 263                 iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
 264                 iounmap(base);
 265
 266                 platform_device_register_resndata(
 267                         &platform_bus, "sh_mobile_sdhi", 0,
 268                         sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
 269                         &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
 270         }
 271 }
 272
 273 static const char *bockw_boards_compat_dt[] __initdata = {
 274         "renesas,bockw",
 275         NULL,
 276 };
 277
 278 DT_MACHINE_START(BOCKW_DT, "bockw")
 279         .init_early     = r8a7778_init_delay,
 280         .init_irq       = r8a7778_init_irq_dt,
 281         .init_machine   = bockw_init,
 282         .dt_compat      = bockw_boards_compat_dt,
 283         .init_late      = r8a7778_init_late,
 284 MACHINE_END