4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <linux/kernel.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/platform_device.h>
28 #include <linux/gpio.h>
29 #include <linux/regulator/fixed.h>
30 #include <linux/regulator/machine.h>
31 #include <linux/smsc911x.h>
32 #include <linux/videodev2.h>
33 #include <mach/common.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/time.h>
38 #include <asm/hardware/cache-l2x0.h>
39 #include <mach/r8a7740.h>
40 #include <mach/irqs.h>
41 #include <video/sh_mobile_lcdc.h>
44 * CS Address device note
45 *----------------------------------------------------------------
46 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
47 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
50 * 5B 0x1600_0000 SRAM (8MB)
51 * 6 0x1800_0000 FPGA (64K)
52 * 0x1801_0000 Ether (4KB)
53 * 0x1801_1000 USB (4KB)
60 *----------------------------------------------------------------------------
61 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
62 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
80 /* Dummy supplies, where voltage doesn't matter */
81 static struct regulator_consumer_supply dummy_supplies[] = {
82 REGULATOR_SUPPLY("vddvario", "smsc911x"),
83 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
93 #define BUSSWMR1 0x0070
94 #define BUSSWMR2 0x0072
95 #define BUSSWMR3 0x0074
96 #define BUSSWMR4 0x0076
99 #define DEVRSTCR1 0x10D0
100 #define DEVRSTCR2 0x10D2
101 #define A1MDSR 0x10E0
105 #define FPGA_IRQ_BASE (512)
106 #define FPGA_IRQ0 (FPGA_IRQ_BASE)
107 #define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
108 #define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
109 static u16 bonito_fpga_read(u32 offset)
111 return __raw_readw(IOMEM(0xf0003000) + offset);
114 static void bonito_fpga_write(u32 offset, u16 val)
116 __raw_writew(val, IOMEM(0xf0003000) + offset);
119 static void bonito_fpga_irq_disable(struct irq_data *data)
121 unsigned int irq = data->irq;
122 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
123 int shift = irq % 16;
125 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
128 static void bonito_fpga_irq_enable(struct irq_data *data)
130 unsigned int irq = data->irq;
131 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
132 int shift = irq % 16;
134 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
137 static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
138 .name = "bonito FPGA",
139 .irq_mask = bonito_fpga_irq_disable,
140 .irq_unmask = bonito_fpga_irq_enable,
143 static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
145 u32 val = bonito_fpga_read(IRQSR1) << 16 |
146 bonito_fpga_read(IRQSR0);
147 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
148 bonito_fpga_read(IRQMR0);
154 for (i = 0; i < 32; i++) {
155 if (!(val & (1 << i)))
158 generic_handle_irq(FPGA_IRQ_BASE + i);
162 static void bonito_fpga_init(void)
166 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
167 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
170 bonito_fpga_write(DEVRSTCR1,
173 /* FPGA irq require special handling */
174 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
175 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
176 handle_level_irq, "level");
177 set_irq_flags(i, IRQF_VALID); /* yuck */
180 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
181 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
189 * bonito board needs some settings by pmic which use i2c access.
190 * pmic settings use device_initcall() here for use it.
192 static __u8 *pmic_settings = NULL;
193 static __u8 pmic_do_2A[] = {
199 static int __init pmic_init(void)
201 struct i2c_adapter *a = i2c_get_adapter(0);
216 for (i = 0; ; i += 2) {
217 buf[0] = pmic_settings[i + 0];
218 buf[1] = pmic_settings[i + 1];
220 if ((0xff == buf[0]) && (0xff == buf[1]))
223 ret = i2c_transfer(a, &msg, 1);
225 pr_err("i2c transfer fail\n");
232 device_initcall(pmic_init);
237 static const struct fb_videomode lcdc0_mode = {
238 .name = "WVGA Panel",
250 static struct sh_mobile_lcdc_info lcdc0_info = {
251 .clock_source = LCDC_CLK_BUS,
253 .chan = LCDC_CHAN_MAINLCD,
254 .fourcc = V4L2_PIX_FMT_RGB565,
255 .interface_type = RGB24,
258 .lcd_modes = &lcdc0_mode,
267 static struct resource lcdc0_resources[] = {
272 .flags = IORESOURCE_MEM,
275 .start = intcs_evt2irq(0x0580),
276 .flags = IORESOURCE_IRQ,
280 static struct platform_device lcdc0_device = {
281 .name = "sh_mobile_lcdc_fb",
283 .resource = lcdc0_resources,
284 .num_resources = ARRAY_SIZE(lcdc0_resources),
286 .platform_data = &lcdc0_info,
287 .coherent_dma_mask = ~0,
294 static struct resource smsc_resources[] = {
297 .end = 0x18011000 - 1,
298 .flags = IORESOURCE_MEM,
301 .start = FPGA_ETH_IRQ,
302 .flags = IORESOURCE_IRQ,
306 static struct smsc911x_platform_config smsc_platdata = {
307 .flags = SMSC911X_USE_16BIT,
308 .phy_interface = PHY_INTERFACE_MODE_MII,
309 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
310 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
313 static struct platform_device smsc_device = {
316 .platform_data = &smsc_platdata,
318 .resource = smsc_resources,
319 .num_resources = ARRAY_SIZE(smsc_resources),
325 static struct platform_device *bonito_core_devices[] __initdata = {
331 static struct platform_device *bonito_base_devices[] __initdata = {
339 static struct map_desc bonito_io_desc[] __initdata = {
341 * for FPGA (0x1800000-0x19ffffff)
342 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
345 .virtual = 0xf0003000,
346 .pfn = __phys_to_pfn(0x18000000),
347 .length = PAGE_SIZE * 2,
348 .type = MT_DEVICE_NONSHARED
352 static void __init bonito_map_io(void)
355 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
361 #define BIT_ON(sw, bit) (sw & (1 << bit))
362 #define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
364 #define VCCQ1CR IOMEM(0xE6058140)
365 #define VCCQ1LCDCR IOMEM(0xE6058186)
367 static void __init bonito_init(void)
371 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
373 r8a7740_pinmux_init();
376 pmic_settings = pmic_do_2A;
379 * core board settings
382 #ifdef CONFIG_CACHE_L2X0
383 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
384 l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
387 r8a7740_add_standard_devices();
389 platform_add_devices(bonito_core_devices,
390 ARRAY_SIZE(bonito_core_devices));
393 * base board settings
395 gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
396 if (!gpio_get_value(GPIO_PORT176)) {
404 gpio_request(GPIO_FN_CS5B, NULL);
405 gpio_request(GPIO_FN_CS6A, NULL);
406 gpio_request(GPIO_FN_CS5A_PORT105, NULL);
407 gpio_request(GPIO_FN_IRQ10, NULL);
409 val = bonito_fpga_read(BVERR);
410 pr_info("bonito version: cpu %02x, base %02x\n",
412 ((val >> 0) & 0xFF));
414 bsw2 = bonito_fpga_read(BUSSWMR2);
415 bsw3 = bonito_fpga_read(BUSSWMR3);
416 bsw4 = bonito_fpga_read(BUSSWMR4);
421 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
422 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
423 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
424 gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
425 gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
431 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
432 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
433 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
434 gpio_request(GPIO_FN_LCD0_D0, NULL);
435 gpio_request(GPIO_FN_LCD0_D1, NULL);
436 gpio_request(GPIO_FN_LCD0_D2, NULL);
437 gpio_request(GPIO_FN_LCD0_D3, NULL);
438 gpio_request(GPIO_FN_LCD0_D4, NULL);
439 gpio_request(GPIO_FN_LCD0_D5, NULL);
440 gpio_request(GPIO_FN_LCD0_D6, NULL);
441 gpio_request(GPIO_FN_LCD0_D7, NULL);
442 gpio_request(GPIO_FN_LCD0_D8, NULL);
443 gpio_request(GPIO_FN_LCD0_D9, NULL);
444 gpio_request(GPIO_FN_LCD0_D10, NULL);
445 gpio_request(GPIO_FN_LCD0_D11, NULL);
446 gpio_request(GPIO_FN_LCD0_D12, NULL);
447 gpio_request(GPIO_FN_LCD0_D13, NULL);
448 gpio_request(GPIO_FN_LCD0_D14, NULL);
449 gpio_request(GPIO_FN_LCD0_D15, NULL);
450 gpio_request(GPIO_FN_LCD0_D16, NULL);
451 gpio_request(GPIO_FN_LCD0_D17, NULL);
452 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
453 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
454 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
455 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
456 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
457 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
458 gpio_request(GPIO_FN_LCD0_DCK, NULL);
459 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
460 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
461 gpio_request(GPIO_FN_LCD0_DISP, NULL);
462 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
464 gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
468 bonito_fpga_write(LCDCR, 1);
470 /* drivability Max */
471 __raw_writew(0x00FF , VCCQ1LCDCR);
472 __raw_writew(0xFFFF , VCCQ1CR);
475 platform_add_devices(bonito_base_devices,
476 ARRAY_SIZE(bonito_base_devices));
480 static void __init bonito_earlytimer_init(void)
485 /* read MD_CK value */
486 val = bonito_fpga_read(A1MDSR);
494 r8a7740_clock_init(md_ck);
495 shmobile_earlytimer_init();
498 static void __init bonito_add_early_devices(void)
500 r8a7740_add_early_devices();
503 MACHINE_START(BONITO, "bonito")
504 .map_io = bonito_map_io,
505 .init_early = bonito_add_early_devices,
506 .init_irq = r8a7740_init_irq,
507 .handle_irq = shmobile_handle_irq_intc,
508 .init_machine = bonito_init,
509 .init_late = shmobile_init_late,
510 .init_time = bonito_earlytimer_init,