2 * R8A7740 processor support
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/serial_sci.h>
28 #include <linux/sh_dma.h>
29 #include <linux/sh_timer.h>
30 #include <linux/dma-mapping.h>
31 #include <mach/dma-register.h>
32 #include <mach/r8a7740.h>
33 #include <mach/pm-rmobile.h>
34 #include <mach/common.h>
35 #include <mach/irqs.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/arch.h>
39 #include <asm/mach/time.h>
41 static struct map_desc r8a7740_io_desc[] __initdata = {
44 * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
47 .virtual = 0xe6000000,
48 .pfn = __phys_to_pfn(0xe6000000),
50 .type = MT_DEVICE_NONSHARED
52 #ifdef CONFIG_CACHE_L2X0
55 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
58 .virtual = 0xf0002000,
59 .pfn = __phys_to_pfn(0xf0100000),
61 .type = MT_DEVICE_NONSHARED
66 void __init r8a7740_map_io(void)
68 iotable_init(r8a7740_io_desc, ARRAY_SIZE(r8a7740_io_desc));
72 static struct resource r8a7740_pfc_resources[] = {
76 .flags = IORESOURCE_MEM,
81 .flags = IORESOURCE_MEM,
85 static struct platform_device r8a7740_pfc_device = {
86 .name = "pfc-r8a7740",
88 .resource = r8a7740_pfc_resources,
89 .num_resources = ARRAY_SIZE(r8a7740_pfc_resources),
92 void __init r8a7740_pinmux_init(void)
94 platform_device_register(&r8a7740_pfc_device);
98 static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000,
100 .flags = UPF_BOOT_AUTOCONF,
101 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4,
104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)),
107 static struct platform_device scif0_device = {
111 .platform_data = &scif0_platform_data,
116 static struct plat_sci_port scif1_platform_data = {
117 .mapbase = 0xe6c50000,
118 .flags = UPF_BOOT_AUTOCONF,
119 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4,
122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)),
125 static struct platform_device scif1_device = {
129 .platform_data = &scif1_platform_data,
134 static struct plat_sci_port scif2_platform_data = {
135 .mapbase = 0xe6c60000,
136 .flags = UPF_BOOT_AUTOCONF,
137 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4,
140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)),
143 static struct platform_device scif2_device = {
147 .platform_data = &scif2_platform_data,
152 static struct plat_sci_port scif3_platform_data = {
153 .mapbase = 0xe6c70000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)),
161 static struct platform_device scif3_device = {
165 .platform_data = &scif3_platform_data,
170 static struct plat_sci_port scif4_platform_data = {
171 .mapbase = 0xe6c80000,
172 .flags = UPF_BOOT_AUTOCONF,
173 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4,
176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)),
179 static struct platform_device scif4_device = {
183 .platform_data = &scif4_platform_data,
188 static struct plat_sci_port scif5_platform_data = {
189 .mapbase = 0xe6cb0000,
190 .flags = UPF_BOOT_AUTOCONF,
191 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4,
194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)),
197 static struct platform_device scif5_device = {
201 .platform_data = &scif5_platform_data,
206 static struct plat_sci_port scif6_platform_data = {
207 .mapbase = 0xe6cc0000,
208 .flags = UPF_BOOT_AUTOCONF,
209 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4,
212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)),
215 static struct platform_device scif6_device = {
219 .platform_data = &scif6_platform_data,
224 static struct plat_sci_port scif7_platform_data = {
225 .mapbase = 0xe6cd0000,
226 .flags = UPF_BOOT_AUTOCONF,
227 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4,
230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)),
233 static struct platform_device scif7_device = {
237 .platform_data = &scif7_platform_data,
242 static struct plat_sci_port scifb_platform_data = {
243 .mapbase = 0xe6c30000,
244 .flags = UPF_BOOT_AUTOCONF,
245 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4,
248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)),
251 static struct platform_device scifb_device = {
255 .platform_data = &scifb_platform_data,
260 static struct sh_timer_config cmt10_platform_data = {
262 .channel_offset = 0x10,
264 .clockevent_rating = 125,
265 .clocksource_rating = 125,
268 static struct resource cmt10_resources[] = {
273 .flags = IORESOURCE_MEM,
276 .start = evt2irq(0x0b00),
277 .flags = IORESOURCE_IRQ,
281 static struct platform_device cmt10_device = {
285 .platform_data = &cmt10_platform_data,
287 .resource = cmt10_resources,
288 .num_resources = ARRAY_SIZE(cmt10_resources),
291 static struct platform_device *r8a7740_early_devices[] __initdata = {
305 static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
307 .slave_id = SHDMA_SLAVE_SDHI0_TX,
309 .chcr = CHCR_TX(XMIT_SZ_16BIT),
312 .slave_id = SHDMA_SLAVE_SDHI0_RX,
314 .chcr = CHCR_RX(XMIT_SZ_16BIT),
317 .slave_id = SHDMA_SLAVE_SDHI1_TX,
319 .chcr = CHCR_TX(XMIT_SZ_16BIT),
322 .slave_id = SHDMA_SLAVE_SDHI1_RX,
324 .chcr = CHCR_RX(XMIT_SZ_16BIT),
327 .slave_id = SHDMA_SLAVE_SDHI2_TX,
329 .chcr = CHCR_TX(XMIT_SZ_16BIT),
332 .slave_id = SHDMA_SLAVE_SDHI2_RX,
334 .chcr = CHCR_RX(XMIT_SZ_16BIT),
337 .slave_id = SHDMA_SLAVE_FSIA_TX,
339 .chcr = CHCR_TX(XMIT_SZ_32BIT),
342 .slave_id = SHDMA_SLAVE_FSIA_RX,
344 .chcr = CHCR_RX(XMIT_SZ_32BIT),
347 .slave_id = SHDMA_SLAVE_FSIB_TX,
349 .chcr = CHCR_TX(XMIT_SZ_32BIT),
354 #define DMA_CHANNEL(a, b, c) \
359 .chclr_offset = (0x220 - 0x20) + a \
362 static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
363 DMA_CHANNEL(0x00, 0, 0),
364 DMA_CHANNEL(0x10, 0, 8),
365 DMA_CHANNEL(0x20, 4, 0),
366 DMA_CHANNEL(0x30, 4, 8),
367 DMA_CHANNEL(0x50, 8, 0),
368 DMA_CHANNEL(0x60, 8, 8),
371 static struct sh_dmae_pdata dma_platform_data = {
372 .slave = r8a7740_dmae_slaves,
373 .slave_num = ARRAY_SIZE(r8a7740_dmae_slaves),
374 .channel = r8a7740_dmae_channels,
375 .channel_num = ARRAY_SIZE(r8a7740_dmae_channels),
376 .ts_low_shift = TS_LOW_SHIFT,
377 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
378 .ts_high_shift = TS_HI_SHIFT,
379 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
380 .ts_shift = dma_ts_shift,
381 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
382 .dmaor_init = DMAOR_DME,
386 /* Resource order important! */
387 static struct resource r8a7740_dmae0_resources[] = {
389 /* Channel registers and DMAOR */
392 .flags = IORESOURCE_MEM,
398 .flags = IORESOURCE_MEM,
402 .start = evt2irq(0x20c0),
403 .end = evt2irq(0x20c0),
404 .flags = IORESOURCE_IRQ,
407 /* IRQ for channels 0-5 */
408 .start = evt2irq(0x2000),
409 .end = evt2irq(0x20a0),
410 .flags = IORESOURCE_IRQ,
414 /* Resource order important! */
415 static struct resource r8a7740_dmae1_resources[] = {
417 /* Channel registers and DMAOR */
420 .flags = IORESOURCE_MEM,
426 .flags = IORESOURCE_MEM,
430 .start = evt2irq(0x21c0),
431 .end = evt2irq(0x21c0),
432 .flags = IORESOURCE_IRQ,
435 /* IRQ for channels 0-5 */
436 .start = evt2irq(0x2100),
437 .end = evt2irq(0x21a0),
438 .flags = IORESOURCE_IRQ,
442 /* Resource order important! */
443 static struct resource r8a7740_dmae2_resources[] = {
445 /* Channel registers and DMAOR */
448 .flags = IORESOURCE_MEM,
454 .flags = IORESOURCE_MEM,
458 .start = evt2irq(0x22c0),
459 .end = evt2irq(0x22c0),
460 .flags = IORESOURCE_IRQ,
463 /* IRQ for channels 0-5 */
464 .start = evt2irq(0x2200),
465 .end = evt2irq(0x22a0),
466 .flags = IORESOURCE_IRQ,
470 static struct platform_device dma0_device = {
471 .name = "sh-dma-engine",
473 .resource = r8a7740_dmae0_resources,
474 .num_resources = ARRAY_SIZE(r8a7740_dmae0_resources),
476 .platform_data = &dma_platform_data,
480 static struct platform_device dma1_device = {
481 .name = "sh-dma-engine",
483 .resource = r8a7740_dmae1_resources,
484 .num_resources = ARRAY_SIZE(r8a7740_dmae1_resources),
486 .platform_data = &dma_platform_data,
490 static struct platform_device dma2_device = {
491 .name = "sh-dma-engine",
493 .resource = r8a7740_dmae2_resources,
494 .num_resources = ARRAY_SIZE(r8a7740_dmae2_resources),
496 .platform_data = &dma_platform_data,
501 static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
509 static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
511 .slave_id = SHDMA_SLAVE_USBHS_TX,
512 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
514 .slave_id = SHDMA_SLAVE_USBHS_RX,
515 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
519 static struct sh_dmae_pdata usb_dma_platform_data = {
520 .slave = r8a7740_usb_dma_slaves,
521 .slave_num = ARRAY_SIZE(r8a7740_usb_dma_slaves),
522 .channel = r8a7740_usb_dma_channels,
523 .channel_num = ARRAY_SIZE(r8a7740_usb_dma_channels),
524 .ts_low_shift = USBTS_LOW_SHIFT,
525 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
526 .ts_high_shift = USBTS_HI_SHIFT,
527 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
528 .ts_shift = dma_usbts_shift,
529 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
530 .dmaor_init = DMAOR_DME,
532 .chcr_ie_bit = 1 << 5,
539 static struct resource r8a7740_usb_dma_resources[] = {
541 /* Channel registers and DMAOR */
543 .end = 0xe68a0064 - 1,
544 .flags = IORESOURCE_MEM,
549 .end = 0xe68a0014 - 1,
550 .flags = IORESOURCE_MEM,
553 /* IRQ for channels */
554 .start = evt2irq(0x0a00),
555 .end = evt2irq(0x0a00),
556 .flags = IORESOURCE_IRQ,
560 static struct platform_device usb_dma_device = {
561 .name = "sh-dma-engine",
563 .resource = r8a7740_usb_dma_resources,
564 .num_resources = ARRAY_SIZE(r8a7740_usb_dma_resources),
566 .platform_data = &usb_dma_platform_data,
571 static struct resource i2c0_resources[] = {
575 .end = 0xfff20425 - 1,
576 .flags = IORESOURCE_MEM,
579 .start = intcs_evt2irq(0xe00),
580 .end = intcs_evt2irq(0xe60),
581 .flags = IORESOURCE_IRQ,
585 static struct resource i2c1_resources[] = {
589 .end = 0xe6c20425 - 1,
590 .flags = IORESOURCE_MEM,
593 .start = evt2irq(0x780), /* IIC1_ALI1 */
594 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
595 .flags = IORESOURCE_IRQ,
599 static struct platform_device i2c0_device = {
600 .name = "i2c-sh_mobile",
602 .resource = i2c0_resources,
603 .num_resources = ARRAY_SIZE(i2c0_resources),
606 static struct platform_device i2c1_device = {
607 .name = "i2c-sh_mobile",
609 .resource = i2c1_resources,
610 .num_resources = ARRAY_SIZE(i2c1_resources),
613 static struct resource pmu_resources[] = {
615 .start = evt2irq(0x19a0),
616 .end = evt2irq(0x19a0),
617 .flags = IORESOURCE_IRQ,
621 static struct platform_device pmu_device = {
624 .num_resources = ARRAY_SIZE(pmu_resources),
625 .resource = pmu_resources,
628 static struct platform_device *r8a7740_late_devices[] __initdata = {
639 * r8a7740 chip has lasting errata on MERAM buffer.
640 * this is work-around for it.
642 * "Media RAM (MERAM)" on r8a7740 documentation
644 #define MEBUFCNTR 0xFE950098
645 void r8a7740_meram_workaround(void)
649 reg = ioremap_nocache(MEBUFCNTR, 4);
651 iowrite32(0x01600164, reg);
657 #define ICSTART 0x0070
659 #define i2c_read(reg, offset) ioread8(reg + offset)
660 #define i2c_write(reg, offset, data) iowrite8(data, reg + offset)
663 * r8a7740 chip has lasting errata on I2C I/O pad reset.
664 * this is work-around for it.
666 static void r8a7740_i2c_workaround(struct platform_device *pdev)
668 struct resource *res;
671 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
672 if (unlikely(!res)) {
673 pr_err("r8a7740 i2c workaround fail (cannot find resource)\n");
677 reg = ioremap(res->start, resource_size(res));
678 if (unlikely(!reg)) {
679 pr_err("r8a7740 i2c workaround fail (cannot map IO)\n");
683 i2c_write(reg, ICCR, i2c_read(reg, ICCR) | 0x80);
684 i2c_read(reg, ICCR); /* dummy read */
686 i2c_write(reg, ICSTART, i2c_read(reg, ICSTART) | 0x10);
687 i2c_read(reg, ICSTART); /* dummy read */
691 i2c_write(reg, ICCR, 0x01);
692 i2c_write(reg, ICSTART, 0x00);
696 i2c_write(reg, ICCR, 0x10);
698 i2c_write(reg, ICCR, 0x00);
700 i2c_write(reg, ICCR, 0x10);
706 void __init r8a7740_add_standard_devices(void)
708 /* I2C work-around */
709 r8a7740_i2c_workaround(&i2c0_device);
710 r8a7740_i2c_workaround(&i2c1_device);
712 r8a7740_init_pm_domains();
715 platform_add_devices(r8a7740_early_devices,
716 ARRAY_SIZE(r8a7740_early_devices));
717 platform_add_devices(r8a7740_late_devices,
718 ARRAY_SIZE(r8a7740_late_devices));
720 /* add devices to PM domain */
722 rmobile_add_device_to_domain("A3SP", &scif0_device);
723 rmobile_add_device_to_domain("A3SP", &scif1_device);
724 rmobile_add_device_to_domain("A3SP", &scif2_device);
725 rmobile_add_device_to_domain("A3SP", &scif3_device);
726 rmobile_add_device_to_domain("A3SP", &scif4_device);
727 rmobile_add_device_to_domain("A3SP", &scif5_device);
728 rmobile_add_device_to_domain("A3SP", &scif6_device);
729 rmobile_add_device_to_domain("A3SP", &scif7_device);
730 rmobile_add_device_to_domain("A3SP", &scifb_device);
731 rmobile_add_device_to_domain("A3SP", &i2c1_device);
734 void __init r8a7740_add_early_devices(void)
736 early_platform_add_devices(r8a7740_early_devices,
737 ARRAY_SIZE(r8a7740_early_devices));
739 /* setup early console here as well */
740 shmobile_setup_console();
745 void __init r8a7740_add_early_devices_dt(void)
747 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
749 early_platform_add_devices(r8a7740_early_devices,
750 ARRAY_SIZE(r8a7740_early_devices));
752 /* setup early console here as well */
753 shmobile_setup_console();
756 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
760 void __init r8a7740_add_standard_devices_dt(void)
762 /* clocks are setup late during boot in the case of DT */
763 r8a7740_clock_init(0);
765 platform_add_devices(r8a7740_early_devices,
766 ARRAY_SIZE(r8a7740_early_devices));
768 of_platform_populate(NULL, of_default_bus_match_table,
769 r8a7740_auxdata_lookup, NULL);
772 static const char *r8a7740_boards_compat_dt[] __initdata = {
777 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
778 .map_io = r8a7740_map_io,
779 .init_early = r8a7740_add_early_devices_dt,
780 .init_irq = r8a7740_init_irq,
781 .handle_irq = shmobile_handle_irq_intc,
782 .init_machine = r8a7740_add_standard_devices_dt,
783 .init_time = shmobile_timer_init,
784 .dt_compat = r8a7740_boards_compat_dt,
787 #endif /* CONFIG_USE_OF */