arch/arm/mach-socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20 #include <asm/arch/scu.h>
  21 #include <asm/arch/nic301.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static struct pl310_regs *const pl310 =
  26         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  27 static struct scu_registers *scu_regs =
  28         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  29 static struct nic301_registers *nic301_regs =
  30         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  31
  32 u32 spl_boot_device(void)
  33 {
  34 #ifdef CONFIG_SPL_SPI_SUPPORT
  35         socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
  36         return BOOT_DEVICE_SPI;
  37 #elif CONFIG_SPL_MMC_SUPPORT
  38         socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
  39         socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
  40         return BOOT_DEVICE_MMC1;
  41 #else
  42         return BOOT_DEVICE_RAM;
  43 #endif
  44 }
  45
  46 #ifdef CONFIG_SPL_MMC_SUPPORT
  47 u32 spl_boot_mode(void)
  48 {
  49 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
  50         return MMCSD_MODE_FS;
  51 #else
  52         return MMCSD_MODE_RAW;
  53 #endif
  54 }
  55 #endif
  56
  57 static void socfpga_nic301_slave_ns(void)
  58 {
  59         writel(0x1, &nic301_regs->lwhps2fpgaregs);
  60         writel(0x1, &nic301_regs->hps2fpgaregs);
  61         writel(0x1, &nic301_regs->acp);
  62         writel(0x1, &nic301_regs->rom);
  63         writel(0x1, &nic301_regs->ocram);
  64         writel(0x1, &nic301_regs->sdrdata);
  65 }
  66
  67 void board_init_f(ulong dummy)
  68 {
  69 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  70         const struct cm_config *cm_default_cfg = cm_get_default_config();
  71 #endif
  72         struct socfpga_system_manager *sysmgr_regs =
  73                 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  74         unsigned long sdram_size;
  75         unsigned long reg;
  76
  77         /*
  78          * First C code to run. Clear fake OCRAM ECC first as SBE
  79          * and DBE might triggered during power on
  80          */
  81         reg = readl(&sysmgr_regs->eccgrp_ocram);
  82         if (reg & SYSMGR_ECC_OCRAM_SERR)
  83                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  84                        &sysmgr_regs->eccgrp_ocram);
  85         if (reg & SYSMGR_ECC_OCRAM_DERR)
  86                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  87                        &sysmgr_regs->eccgrp_ocram);
  88
  89         memset(__bss_start, 0, __bss_end - __bss_start);
  90
  91         socfpga_nic301_slave_ns();
  92
  93         /* Configure ARM MPU SNSAC register. */
  94         setbits_le32(&scu_regs->sacr, 0xfff);
  95
  96         /* Remap SDRAM to 0x0 */
  97         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
  98         writel(0x1, &pl310->pl310_addr_filter_start);
  99
 100 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
 101         debug("Freezing all I/O banks\n");
 102         /* freeze all IO banks */
 103         sys_mgr_frzctrl_freeze_req();
 104
 105         /* Put everything into reset but L4WD0. */
 106         socfpga_per_reset_all();
 107         /* Put FPGA bridges into reset too. */
 108         socfpga_bridges_reset(1);
 109
 110         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 111         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 112         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 113
 114         timer_init();
 115
 116         debug("Reconfigure Clock Manager\n");
 117         /* reconfigure the PLLs */
 118         cm_basic_init(cm_default_cfg);
 119
 120         /* Enable bootrom to configure IOs. */
 121         sysmgr_config_warmrstcfgio(1);
 122
 123         /* configure the IOCSR / IO buffer settings */
 124         if (scan_mgr_configure_iocsr())
 125                 hang();
 126
 127         sysmgr_config_warmrstcfgio(0);
 128
 129         /* configure the pin muxing through system manager */
 130         sysmgr_config_warmrstcfgio(1);
 131         sysmgr_pinmux_init();
 132         sysmgr_config_warmrstcfgio(0);
 133
 134 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
 135
 136         /* De-assert reset for peripherals and bridges based on handoff */
 137         reset_deassert_peripherals_handoff();
 138         socfpga_bridges_reset(0);
 139
 140         debug("Unfreezing/Thaw all I/O banks\n");
 141         /* unfreeze / thaw all IO banks */
 142         sys_mgr_frzctrl_thaw_req();
 143
 144         /* enable console uart printing */
 145         preloader_console_init();
 146
 147         if (sdram_mmr_init_full(0xffffffff) != 0) {
 148                 puts("SDRAM init failed.\n");
 149                 hang();
 150         }
 151
 152         debug("SDRAM: Calibrating PHY\n");
 153         /* SDRAM calibration */
 154         if (sdram_calibration_full() == 0) {
 155                 puts("SDRAM calibration failed.\n");
 156                 hang();
 157         }
 158
 159         sdram_size = sdram_calculate_size();
 160         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 161
 162         /* Sanity check ensure correct SDRAM size specified */
 163         if (get_ram_size(0, sdram_size) != sdram_size) {
 164                 puts("SDRAM size check failed!\n");
 165                 hang();
 166         }
 167
 168         socfpga_bridges_reset(1);
 169
 170         board_init_r(NULL, 0);
 171 }