2 * Copyright (C) 2008-2009 ST-Ericsson SA
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
11 #include <linux/types.h>
12 #include <linux/init.h>
13 #include <linux/device.h>
14 #include <linux/amba/bus.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/platform_device.h>
20 #include <asm/mach/map.h>
22 #include <plat/gpio-nomadik.h>
23 #include <mach/hardware.h>
24 #include <mach/setup.h>
25 #include <mach/devices.h>
27 #include <mach/db8500-regs.h>
29 #include "devices-db8500.h"
30 #include "ste-dma40-db8500.h"
32 /* minimum static i/o mapping required to boot U8500 platforms */
33 static struct map_desc u8500_uart_io_desc[] __initdata = {
34 __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
35 __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
38 static struct map_desc u8500_io_desc[] __initdata = {
39 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
40 __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
42 __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
43 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
44 __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
46 __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
47 __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
48 __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
49 __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
50 __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
52 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
53 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
54 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
55 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
56 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
57 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
60 void __init u8500_map_io(void)
63 * Map the UARTs early so that the DEBUG_LL stuff continues to work.
65 iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
69 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
71 _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
74 static struct resource db8500_pmu_resources[] = {
76 .start = IRQ_DB8500_PMU,
77 .end = IRQ_DB8500_PMU,
78 .flags = IORESOURCE_IRQ,
83 * The PMU IRQ lines of two cores are wired together into a single interrupt.
84 * Bounce the interrupt to the other core if it's not ours.
86 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
88 irqreturn_t ret = handler(irq, dev);
89 int other = !smp_processor_id();
91 if (ret == IRQ_NONE && cpu_online(other))
92 irq_set_affinity(irq, cpumask_of(other));
95 * We should be able to get away with the amount of IRQ_NONEs we give,
96 * while still having the spurious IRQ detection code kick in if the
97 * interrupt really starts hitting spuriously.
102 static struct arm_pmu_platdata db8500_pmu_platdata = {
103 .handle_irq = db8500_pmu_handler,
106 static struct platform_device db8500_pmu_device = {
108 .id = ARM_PMU_DEVICE_CPU,
109 .num_resources = ARRAY_SIZE(db8500_pmu_resources),
110 .resource = db8500_pmu_resources,
111 .dev.platform_data = &db8500_pmu_platdata,
114 static struct platform_device db8500_prcmu_device = {
115 .name = "db8500-prcmu",
118 static struct platform_device *platform_devs[] __initdata = {
121 &db8500_prcmu_device,
124 static struct platform_device *of_platform_devs[] __initdata = {
127 &db8500_prcmu_device,
130 static resource_size_t __initdata db8500_gpio_base[] = {
131 U8500_GPIOBANK0_BASE,
132 U8500_GPIOBANK1_BASE,
133 U8500_GPIOBANK2_BASE,
134 U8500_GPIOBANK3_BASE,
135 U8500_GPIOBANK4_BASE,
136 U8500_GPIOBANK5_BASE,
137 U8500_GPIOBANK6_BASE,
138 U8500_GPIOBANK7_BASE,
139 U8500_GPIOBANK8_BASE,
142 static void __init db8500_add_gpios(struct device *parent)
144 struct nmk_gpio_platform_data pdata = {
145 .supports_sleepmode = true,
148 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
149 IRQ_DB8500_GPIO0, &pdata);
152 static int usb_db8500_rx_dma_cfg[] = {
153 DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
154 DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
155 DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
156 DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
157 DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
158 DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
159 DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
160 DB8500_DMA_DEV39_USB_OTG_IEP_8
163 static int usb_db8500_tx_dma_cfg[] = {
164 DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
165 DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
166 DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
167 DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
168 DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
169 DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
170 DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
171 DB8500_DMA_DEV39_USB_OTG_OEP_8
174 static const char *db8500_read_soc_id(void)
176 void __iomem *uid = __io_address(U8500_BB_UID_BASE);
178 return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
180 readl((u32 *)uid+1), readl((u32 *)uid+2),
181 readl((u32 *)uid+3), readl((u32 *)uid+4));
184 static struct device * __init db8500_soc_device_init(void)
186 const char *soc_id = db8500_read_soc_id();
188 return ux500_soc_device_init(soc_id);
192 * This function is called from the board init
194 struct device * __init u8500_init_devices(void)
196 struct device *parent;
199 parent = db8500_soc_device_init();
201 db8500_add_rtc(parent);
202 db8500_add_gpios(parent);
203 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
205 platform_device_register_data(parent,
206 "cpufreq-u8500", -1, NULL, 0);
208 for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++)
209 of_platform_devs[i]->dev.parent = parent;
212 * Devices to be DT:ed:
213 * u8500_dma40_device = todo
214 * db8500_pmu_device = todo
215 * db8500_prcmu_device = todo
217 platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));