2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/bootmem.h>
13 #include <linux/module.h>
15 #include <linux/gfp.h>
16 #include <linux/errno.h>
17 #include <linux/list.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dma-contiguous.h>
22 #include <linux/highmem.h>
23 #include <linux/memblock.h>
24 #include <linux/slab.h>
25 #include <linux/iommu.h>
27 #include <linux/vmalloc.h>
28 #include <linux/sizes.h>
29 #include <linux/cma.h>
31 #include <asm/memory.h>
32 #include <asm/highmem.h>
33 #include <asm/cacheflush.h>
34 #include <asm/tlbflush.h>
35 #include <asm/mach/arch.h>
36 #include <asm/dma-iommu.h>
37 #include <asm/mach/map.h>
38 #include <asm/system_info.h>
39 #include <asm/dma-contiguous.h>
44 * The DMA API is built upon the notion of "buffer ownership". A buffer
45 * is either exclusively owned by the CPU (and therefore may be accessed
46 * by it) or exclusively owned by the DMA device. These helper functions
47 * represent the transitions between these two ownership states.
49 * Note, however, that on later ARMs, this notion does not work due to
50 * speculative prefetches. We model our approach on the assumption that
51 * the CPU does do speculative prefetches, which means we clean caches
52 * before transfers and delay cache invalidation until transfer completion.
55 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
56 size_t, enum dma_data_direction);
57 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
58 size_t, enum dma_data_direction);
61 * arm_dma_map_page - map a portion of a page for streaming DMA
62 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
63 * @page: page that buffer resides in
64 * @offset: offset into page for start of buffer
65 * @size: size of buffer to map
66 * @dir: DMA transfer direction
68 * Ensure that any data held in the cache is appropriately discarded
71 * The device owns this memory once this call has completed. The CPU
72 * can regain ownership by calling dma_unmap_page().
74 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
75 unsigned long offset, size_t size, enum dma_data_direction dir,
76 struct dma_attrs *attrs)
78 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
79 __dma_page_cpu_to_dev(page, offset, size, dir);
80 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
83 static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
84 unsigned long offset, size_t size, enum dma_data_direction dir,
85 struct dma_attrs *attrs)
87 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
91 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
92 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
93 * @handle: DMA address of buffer
94 * @size: size of buffer (same as passed to dma_map_page)
95 * @dir: DMA transfer direction (same as passed to dma_map_page)
97 * Unmap a page streaming mode DMA translation. The handle and size
98 * must match what was provided in the previous dma_map_page() call.
99 * All other usages are undefined.
101 * After this call, reads by the CPU to the buffer are guaranteed to see
102 * whatever the device wrote there.
104 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
105 size_t size, enum dma_data_direction dir,
106 struct dma_attrs *attrs)
108 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
109 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
110 handle & ~PAGE_MASK, size, dir);
113 static void arm_dma_sync_single_for_cpu(struct device *dev,
114 dma_addr_t handle, size_t size, enum dma_data_direction dir)
116 unsigned int offset = handle & (PAGE_SIZE - 1);
117 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
118 __dma_page_dev_to_cpu(page, offset, size, dir);
121 static void arm_dma_sync_single_for_device(struct device *dev,
122 dma_addr_t handle, size_t size, enum dma_data_direction dir)
124 unsigned int offset = handle & (PAGE_SIZE - 1);
125 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
126 __dma_page_cpu_to_dev(page, offset, size, dir);
129 struct dma_map_ops arm_dma_ops = {
130 .alloc = arm_dma_alloc,
131 .free = arm_dma_free,
132 .mmap = arm_dma_mmap,
133 .get_sgtable = arm_dma_get_sgtable,
134 .map_page = arm_dma_map_page,
135 .unmap_page = arm_dma_unmap_page,
136 .map_sg = arm_dma_map_sg,
137 .unmap_sg = arm_dma_unmap_sg,
138 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
139 .sync_single_for_device = arm_dma_sync_single_for_device,
140 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
141 .sync_sg_for_device = arm_dma_sync_sg_for_device,
142 .set_dma_mask = arm_dma_set_mask,
144 EXPORT_SYMBOL(arm_dma_ops);
146 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
147 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
148 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
149 dma_addr_t handle, struct dma_attrs *attrs);
151 struct dma_map_ops arm_coherent_dma_ops = {
152 .alloc = arm_coherent_dma_alloc,
153 .free = arm_coherent_dma_free,
154 .mmap = arm_dma_mmap,
155 .get_sgtable = arm_dma_get_sgtable,
156 .map_page = arm_coherent_dma_map_page,
157 .map_sg = arm_dma_map_sg,
158 .set_dma_mask = arm_dma_set_mask,
160 EXPORT_SYMBOL(arm_coherent_dma_ops);
162 static int __dma_supported(struct device *dev, u64 mask, bool warn)
164 unsigned long max_dma_pfn;
167 * If the mask allows for more memory than we can address,
168 * and we actually have that much memory, then we must
169 * indicate that DMA to this device is not supported.
171 if (sizeof(mask) != sizeof(dma_addr_t) &&
172 mask > (dma_addr_t)~0 &&
173 dma_to_pfn(dev, ~0) < max_pfn) {
175 dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n",
177 dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n");
182 max_dma_pfn = min(max_pfn, arm_dma_pfn_limit);
185 * Translate the device's DMA mask to a PFN limit. This
186 * PFN number includes the page which we can DMA to.
188 if (dma_to_pfn(dev, mask) < max_dma_pfn) {
190 dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n",
192 dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1,
200 static u64 get_coherent_dma_mask(struct device *dev)
202 u64 mask = (u64)DMA_BIT_MASK(32);
205 mask = dev->coherent_dma_mask;
208 * Sanity check the DMA mask - it must be non-zero, and
209 * must be able to be satisfied by a DMA allocation.
212 dev_warn(dev, "coherent DMA mask is unset\n");
216 if (!__dma_supported(dev, mask, true))
223 static void __dma_clear_buffer(struct page *page, size_t size)
226 * Ensure that the allocated pages are zeroed, and that any data
227 * lurking in the kernel direct-mapped region is invalidated.
229 if (PageHighMem(page)) {
230 phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
231 phys_addr_t end = base + size;
233 void *ptr = kmap_atomic(page);
234 memset(ptr, 0, PAGE_SIZE);
235 dmac_flush_range(ptr, ptr + PAGE_SIZE);
240 outer_flush_range(base, end);
242 void *ptr = page_address(page);
243 memset(ptr, 0, size);
244 dmac_flush_range(ptr, ptr + size);
245 outer_flush_range(__pa(ptr), __pa(ptr) + size);
250 * Allocate a DMA buffer for 'dev' of size 'size' using the
251 * specified gfp mask. Note that 'size' must be page aligned.
253 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
255 unsigned long order = get_order(size);
256 struct page *page, *p, *e;
258 page = alloc_pages(gfp, order);
263 * Now split the huge page and free the excess pages
265 split_page(page, order);
266 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
269 __dma_clear_buffer(page, size);
275 * Free a DMA buffer. 'size' must be page aligned.
277 static void __dma_free_buffer(struct page *page, size_t size)
279 struct page *e = page + (size >> PAGE_SHIFT);
289 static void *__alloc_from_contiguous(struct device *dev, size_t size,
290 pgprot_t prot, struct page **ret_page,
293 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
294 pgprot_t prot, struct page **ret_page,
298 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
302 * DMA allocation can be mapped to user space, so lets
303 * set VM_USERMAP flags too.
305 return dma_common_contiguous_remap(page, size,
306 VM_ARM_DMA_CONSISTENT | VM_USERMAP,
310 static void __dma_free_remap(void *cpu_addr, size_t size)
312 dma_common_free_remap(cpu_addr, size,
313 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
316 #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
321 unsigned long *bitmap;
322 unsigned long nr_pages;
327 static struct dma_pool atomic_pool = {
328 .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
331 static int __init early_coherent_pool(char *p)
333 atomic_pool.size = memparse(p, &p);
336 early_param("coherent_pool", early_coherent_pool);
338 void __init init_dma_coherent_pool_size(unsigned long size)
341 * Catch any attempt to set the pool size too late.
343 BUG_ON(atomic_pool.vaddr);
346 * Set architecture specific coherent pool size only if
347 * it has not been changed by kernel command line parameter.
349 if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
350 atomic_pool.size = size;
354 * Initialise the coherent pool for atomic allocations.
356 static int __init atomic_pool_init(void)
358 struct dma_pool *pool = &atomic_pool;
359 pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL);
360 gfp_t gfp = GFP_KERNEL | GFP_DMA;
361 unsigned long nr_pages = pool->size >> PAGE_SHIFT;
362 unsigned long *bitmap;
366 int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
368 bitmap = kzalloc(bitmap_size, GFP_KERNEL);
372 pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
376 if (dev_get_cma_area(NULL))
377 ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
380 ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
385 for (i = 0; i < nr_pages; i++)
388 spin_lock_init(&pool->lock);
391 pool->bitmap = bitmap;
392 pool->nr_pages = nr_pages;
393 pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
394 (unsigned)pool->size / 1024);
402 pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
403 (unsigned)pool->size / 1024);
407 * CMA is activated by core_initcall, so we must be called after it.
409 postcore_initcall(atomic_pool_init);
411 struct dma_contig_early_reserve {
416 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
418 static int dma_mmu_remap_num __initdata;
420 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
422 dma_mmu_remap[dma_mmu_remap_num].base = base;
423 dma_mmu_remap[dma_mmu_remap_num].size = size;
427 void __init dma_contiguous_remap(void)
430 for (i = 0; i < dma_mmu_remap_num; i++) {
431 phys_addr_t start = dma_mmu_remap[i].base;
432 phys_addr_t end = start + dma_mmu_remap[i].size;
436 if (end > arm_lowmem_limit)
437 end = arm_lowmem_limit;
441 map.pfn = __phys_to_pfn(start);
442 map.virtual = __phys_to_virt(start);
443 map.length = end - start;
444 map.type = MT_MEMORY_DMA_READY;
447 * Clear previous low-memory mapping to ensure that the
448 * TLB does not see any conflicting entries, then flush
449 * the TLB of the old entries before creating new mappings.
451 * This ensures that any speculatively loaded TLB entries
452 * (even though they may be rare) can not cause any problems,
453 * and ensures that this code is architecturally compliant.
455 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
457 pmd_clear(pmd_off_k(addr));
459 flush_tlb_kernel_range(__phys_to_virt(start),
460 __phys_to_virt(end));
462 iotable_init(&map, 1);
466 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
469 struct page *page = virt_to_page(addr);
470 pgprot_t prot = *(pgprot_t *)data;
472 set_pte_ext(pte, mk_pte(page, prot), 0);
476 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
478 unsigned long start = (unsigned long) page_address(page);
479 unsigned end = start + size;
481 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
482 flush_tlb_kernel_range(start, end);
485 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
486 pgprot_t prot, struct page **ret_page,
491 page = __dma_alloc_buffer(dev, size, gfp);
495 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
497 __dma_free_buffer(page, size);
505 static void *__alloc_from_pool(size_t size, struct page **ret_page)
507 struct dma_pool *pool = &atomic_pool;
508 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
512 unsigned long align_mask;
515 WARN(1, "coherent pool not initialised!\n");
520 * Align the region allocation - allocations from pool are rather
521 * small, so align them to their order in pages, minimum is a page
522 * size. This helps reduce fragmentation of the DMA space.
524 align_mask = (1 << get_order(size)) - 1;
526 spin_lock_irqsave(&pool->lock, flags);
527 pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
528 0, count, align_mask);
529 if (pageno < pool->nr_pages) {
530 bitmap_set(pool->bitmap, pageno, count);
531 ptr = pool->vaddr + PAGE_SIZE * pageno;
532 *ret_page = pool->pages[pageno];
534 pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
535 "Please increase it with coherent_pool= kernel parameter!\n",
536 (unsigned)pool->size / 1024);
538 spin_unlock_irqrestore(&pool->lock, flags);
543 static bool __in_atomic_pool(void *start, size_t size)
545 struct dma_pool *pool = &atomic_pool;
546 void *end = start + size;
547 void *pool_start = pool->vaddr;
548 void *pool_end = pool->vaddr + pool->size;
550 if (start < pool_start || start >= pool_end)
556 WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
557 start, end - 1, pool_start, pool_end - 1);
562 static int __free_from_pool(void *start, size_t size)
564 struct dma_pool *pool = &atomic_pool;
565 unsigned long pageno, count;
568 if (!__in_atomic_pool(start, size))
571 pageno = (start - pool->vaddr) >> PAGE_SHIFT;
572 count = size >> PAGE_SHIFT;
574 spin_lock_irqsave(&pool->lock, flags);
575 bitmap_clear(pool->bitmap, pageno, count);
576 spin_unlock_irqrestore(&pool->lock, flags);
581 static void *__alloc_from_contiguous(struct device *dev, size_t size,
582 pgprot_t prot, struct page **ret_page,
585 unsigned long order = get_order(size);
586 size_t count = size >> PAGE_SHIFT;
590 page = dma_alloc_from_contiguous(dev, count, order);
594 __dma_clear_buffer(page, size);
596 if (PageHighMem(page)) {
597 ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
599 dma_release_from_contiguous(dev, page, count);
603 __dma_remap(page, size, prot);
604 ptr = page_address(page);
610 static void __free_from_contiguous(struct device *dev, struct page *page,
611 void *cpu_addr, size_t size)
613 if (PageHighMem(page))
614 __dma_free_remap(cpu_addr, size);
616 __dma_remap(page, size, PAGE_KERNEL);
617 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
620 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
622 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
623 pgprot_writecombine(prot) :
624 pgprot_dmacoherent(prot);
630 #else /* !CONFIG_MMU */
634 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
635 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
636 #define __alloc_from_pool(size, ret_page) NULL
637 #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
638 #define __free_from_pool(cpu_addr, size) 0
639 #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
640 #define __dma_free_remap(cpu_addr, size) do { } while (0)
642 #endif /* CONFIG_MMU */
644 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
645 struct page **ret_page)
648 page = __dma_alloc_buffer(dev, size, gfp);
653 return page_address(page);
658 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
659 gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
661 u64 mask = get_coherent_dma_mask(dev);
662 struct page *page = NULL;
665 #ifdef CONFIG_DMA_API_DEBUG
666 u64 limit = (mask + 1) & ~mask;
667 if (limit && size >= limit) {
668 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
677 if (mask < 0xffffffffULL)
681 * Following is a work-around (a.k.a. hack) to prevent pages
682 * with __GFP_COMP being passed to split_page() which cannot
683 * handle them. The real problem is that this flag probably
684 * should be 0 on ARM as it is not supported on this
685 * platform; see CONFIG_HUGETLBFS.
687 gfp &= ~(__GFP_COMP);
689 *handle = DMA_ERROR_CODE;
690 size = PAGE_ALIGN(size);
692 if (is_coherent || nommu())
693 addr = __alloc_simple_buffer(dev, size, gfp, &page);
694 else if (!(gfp & __GFP_WAIT))
695 addr = __alloc_from_pool(size, &page);
696 else if (!dev_get_cma_area(dev))
697 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
699 addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
702 *handle = pfn_to_dma(dev, page_to_pfn(page));
708 * Allocate DMA-coherent memory space and return both the kernel remapped
709 * virtual and bus address for that space.
711 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
712 gfp_t gfp, struct dma_attrs *attrs)
714 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
717 if (dma_alloc_from_coherent(dev, size, handle, &memory))
720 return __dma_alloc(dev, size, handle, gfp, prot, false,
721 __builtin_return_address(0));
724 static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
725 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
727 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
730 if (dma_alloc_from_coherent(dev, size, handle, &memory))
733 return __dma_alloc(dev, size, handle, gfp, prot, true,
734 __builtin_return_address(0));
738 * Create userspace mapping for the DMA-coherent memory.
740 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
741 void *cpu_addr, dma_addr_t dma_addr, size_t size,
742 struct dma_attrs *attrs)
746 unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
747 unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
748 unsigned long pfn = dma_to_pfn(dev, dma_addr);
749 unsigned long off = vma->vm_pgoff;
751 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
753 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
756 if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
757 ret = remap_pfn_range(vma, vma->vm_start,
759 vma->vm_end - vma->vm_start,
762 #endif /* CONFIG_MMU */
768 * Free a buffer as defined by the above mapping.
770 static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
771 dma_addr_t handle, struct dma_attrs *attrs,
774 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
776 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
779 size = PAGE_ALIGN(size);
781 if (is_coherent || nommu()) {
782 __dma_free_buffer(page, size);
783 } else if (__free_from_pool(cpu_addr, size)) {
785 } else if (!dev_get_cma_area(dev)) {
786 __dma_free_remap(cpu_addr, size);
787 __dma_free_buffer(page, size);
790 * Non-atomic allocations cannot be freed with IRQs disabled
792 WARN_ON(irqs_disabled());
793 __free_from_contiguous(dev, page, cpu_addr, size);
797 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
798 dma_addr_t handle, struct dma_attrs *attrs)
800 __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
803 static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
804 dma_addr_t handle, struct dma_attrs *attrs)
806 __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
809 int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
810 void *cpu_addr, dma_addr_t handle, size_t size,
811 struct dma_attrs *attrs)
813 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
816 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
820 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
824 static void dma_cache_maint_page(struct page *page, unsigned long offset,
825 size_t size, enum dma_data_direction dir,
826 void (*op)(const void *, size_t, int))
831 pfn = page_to_pfn(page) + offset / PAGE_SIZE;
835 * A single sg entry may refer to multiple physically contiguous
836 * pages. But we still need to process highmem pages individually.
837 * If highmem is not configured then the bulk of this loop gets
844 page = pfn_to_page(pfn);
846 if (PageHighMem(page)) {
847 if (len + offset > PAGE_SIZE)
848 len = PAGE_SIZE - offset;
850 if (cache_is_vipt_nonaliasing()) {
851 vaddr = kmap_atomic(page);
852 op(vaddr + offset, len, dir);
853 kunmap_atomic(vaddr);
855 vaddr = kmap_high_get(page);
857 op(vaddr + offset, len, dir);
862 vaddr = page_address(page) + offset;
872 * Make an area consistent for devices.
873 * Note: Drivers should NOT use this function directly, as it will break
874 * platforms with CONFIG_DMABOUNCE.
875 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
877 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
878 size_t size, enum dma_data_direction dir)
882 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
884 paddr = page_to_phys(page) + off;
885 if (dir == DMA_FROM_DEVICE) {
886 outer_inv_range(paddr, paddr + size);
888 outer_clean_range(paddr, paddr + size);
890 /* FIXME: non-speculating: flush on bidirectional mappings? */
893 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
894 size_t size, enum dma_data_direction dir)
896 phys_addr_t paddr = page_to_phys(page) + off;
898 /* FIXME: non-speculating: not required */
899 /* in any case, don't bother invalidating if DMA to device */
900 if (dir != DMA_TO_DEVICE) {
901 outer_inv_range(paddr, paddr + size);
903 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
907 * Mark the D-cache clean for these pages to avoid extra flushing.
909 if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
913 pfn = page_to_pfn(page) + off / PAGE_SIZE;
917 left -= PAGE_SIZE - off;
919 while (left >= PAGE_SIZE) {
920 page = pfn_to_page(pfn++);
921 set_bit(PG_dcache_clean, &page->flags);
928 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
929 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
930 * @sg: list of buffers
931 * @nents: number of buffers to map
932 * @dir: DMA transfer direction
934 * Map a set of buffers described by scatterlist in streaming mode for DMA.
935 * This is the scatter-gather version of the dma_map_single interface.
936 * Here the scatter gather list elements are each tagged with the
937 * appropriate dma address and length. They are obtained via
938 * sg_dma_{address,length}.
940 * Device ownership issues as mentioned for dma_map_single are the same
943 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
944 enum dma_data_direction dir, struct dma_attrs *attrs)
946 struct dma_map_ops *ops = get_dma_ops(dev);
947 struct scatterlist *s;
950 for_each_sg(sg, s, nents, i) {
951 #ifdef CONFIG_NEED_SG_DMA_LENGTH
952 s->dma_length = s->length;
954 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
955 s->length, dir, attrs);
956 if (dma_mapping_error(dev, s->dma_address))
962 for_each_sg(sg, s, i, j)
963 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
968 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
969 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
970 * @sg: list of buffers
971 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
972 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
974 * Unmap a set of streaming mode DMA translations. Again, CPU access
975 * rules concerning calls here are the same as for dma_unmap_single().
977 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
978 enum dma_data_direction dir, struct dma_attrs *attrs)
980 struct dma_map_ops *ops = get_dma_ops(dev);
981 struct scatterlist *s;
985 for_each_sg(sg, s, nents, i)
986 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
990 * arm_dma_sync_sg_for_cpu
991 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
992 * @sg: list of buffers
993 * @nents: number of buffers to map (returned from dma_map_sg)
994 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
996 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
997 int nents, enum dma_data_direction dir)
999 struct dma_map_ops *ops = get_dma_ops(dev);
1000 struct scatterlist *s;
1003 for_each_sg(sg, s, nents, i)
1004 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
1009 * arm_dma_sync_sg_for_device
1010 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
1011 * @sg: list of buffers
1012 * @nents: number of buffers to map (returned from dma_map_sg)
1013 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1015 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1016 int nents, enum dma_data_direction dir)
1018 struct dma_map_ops *ops = get_dma_ops(dev);
1019 struct scatterlist *s;
1022 for_each_sg(sg, s, nents, i)
1023 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
1028 * Return whether the given device DMA address mask can be supported
1029 * properly. For example, if your device can only drive the low 24-bits
1030 * during bus mastering, then you would pass 0x00ffffff as the mask
1033 int dma_supported(struct device *dev, u64 mask)
1035 return __dma_supported(dev, mask, false);
1037 EXPORT_SYMBOL(dma_supported);
1039 int arm_dma_set_mask(struct device *dev, u64 dma_mask)
1041 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
1044 *dev->dma_mask = dma_mask;
1049 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1051 static int __init dma_debug_do_init(void)
1053 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1056 fs_initcall(dma_debug_do_init);
1058 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1062 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping);
1064 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1067 unsigned int order = get_order(size);
1068 unsigned int align = 0;
1069 unsigned int count, start;
1070 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1071 unsigned long flags;
1075 if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
1076 order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
1078 count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1079 align = (1 << order) - 1;
1081 spin_lock_irqsave(&mapping->lock, flags);
1082 for (i = 0; i < mapping->nr_bitmaps; i++) {
1083 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1084 mapping->bits, 0, count, align);
1086 if (start > mapping->bits)
1089 bitmap_set(mapping->bitmaps[i], start, count);
1094 * No unused range found. Try to extend the existing mapping
1095 * and perform a second attempt to reserve an IO virtual
1096 * address range of size bytes.
1098 if (i == mapping->nr_bitmaps) {
1099 if (extend_iommu_mapping(mapping)) {
1100 spin_unlock_irqrestore(&mapping->lock, flags);
1101 return DMA_ERROR_CODE;
1104 start = bitmap_find_next_zero_area(mapping->bitmaps[i],
1105 mapping->bits, 0, count, align);
1107 if (start > mapping->bits) {
1108 spin_unlock_irqrestore(&mapping->lock, flags);
1109 return DMA_ERROR_CODE;
1112 bitmap_set(mapping->bitmaps[i], start, count);
1114 spin_unlock_irqrestore(&mapping->lock, flags);
1116 iova = mapping->base + (mapping_size * i);
1117 iova += start << PAGE_SHIFT;
1122 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1123 dma_addr_t addr, size_t size)
1125 unsigned int start, count;
1126 size_t mapping_size = mapping->bits << PAGE_SHIFT;
1127 unsigned long flags;
1128 dma_addr_t bitmap_base;
1134 bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
1135 BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
1137 bitmap_base = mapping->base + mapping_size * bitmap_index;
1139 start = (addr - bitmap_base) >> PAGE_SHIFT;
1141 if (addr + size > bitmap_base + mapping_size) {
1143 * The address range to be freed reaches into the iova
1144 * range of the next bitmap. This should not happen as
1145 * we don't allow this in __alloc_iova (at the
1150 count = size >> PAGE_SHIFT;
1152 spin_lock_irqsave(&mapping->lock, flags);
1153 bitmap_clear(mapping->bitmaps[bitmap_index], start, count);
1154 spin_unlock_irqrestore(&mapping->lock, flags);
1157 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
1158 gfp_t gfp, struct dma_attrs *attrs)
1160 struct page **pages;
1161 int count = size >> PAGE_SHIFT;
1162 int array_size = count * sizeof(struct page *);
1165 if (array_size <= PAGE_SIZE)
1166 pages = kzalloc(array_size, gfp);
1168 pages = vzalloc(array_size);
1172 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
1174 unsigned long order = get_order(size);
1177 page = dma_alloc_from_contiguous(dev, count, order);
1181 __dma_clear_buffer(page, size);
1183 for (i = 0; i < count; i++)
1184 pages[i] = page + i;
1190 * IOMMU can map any pages, so himem can also be used here
1192 gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
1195 int j, order = __fls(count);
1197 pages[i] = alloc_pages(gfp, order);
1198 while (!pages[i] && order)
1199 pages[i] = alloc_pages(gfp, --order);
1204 split_page(pages[i], order);
1207 pages[i + j] = pages[i] + j;
1210 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1212 count -= 1 << order;
1219 __free_pages(pages[i], 0);
1220 if (array_size <= PAGE_SIZE)
1227 static int __iommu_free_buffer(struct device *dev, struct page **pages,
1228 size_t size, struct dma_attrs *attrs)
1230 int count = size >> PAGE_SHIFT;
1231 int array_size = count * sizeof(struct page *);
1234 if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
1235 dma_release_from_contiguous(dev, pages[0], count);
1237 for (i = 0; i < count; i++)
1239 __free_pages(pages[i], 0);
1242 if (array_size <= PAGE_SIZE)
1250 * Create a CPU mapping for a specified pages
1253 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
1256 return dma_common_pages_remap(pages, size,
1257 VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller);
1262 * Create a mapping in device IO address space for specified pages
1265 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1267 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1268 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1269 dma_addr_t dma_addr, iova;
1270 int i, ret = DMA_ERROR_CODE;
1272 dma_addr = __alloc_iova(mapping, size);
1273 if (dma_addr == DMA_ERROR_CODE)
1277 for (i = 0; i < count; ) {
1278 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1279 phys_addr_t phys = page_to_phys(pages[i]);
1280 unsigned int len, j;
1282 for (j = i + 1; j < count; j++, next_pfn++)
1283 if (page_to_pfn(pages[j]) != next_pfn)
1286 len = (j - i) << PAGE_SHIFT;
1287 ret = iommu_map(mapping->domain, iova, phys, len,
1288 IOMMU_READ|IOMMU_WRITE);
1296 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1297 __free_iova(mapping, dma_addr, size);
1298 return DMA_ERROR_CODE;
1301 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1303 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1306 * add optional in-page offset from iova to size and align
1307 * result to page size
1309 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1312 iommu_unmap(mapping->domain, iova, size);
1313 __free_iova(mapping, iova, size);
1317 static struct page **__atomic_get_pages(void *addr)
1319 struct dma_pool *pool = &atomic_pool;
1320 struct page **pages = pool->pages;
1321 int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
1323 return pages + offs;
1326 static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
1328 struct vm_struct *area;
1330 if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
1331 return __atomic_get_pages(cpu_addr);
1333 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1336 area = find_vm_area(cpu_addr);
1337 if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
1342 static void *__iommu_alloc_atomic(struct device *dev, size_t size,
1348 addr = __alloc_from_pool(size, &page);
1352 *handle = __iommu_create_mapping(dev, &page, size);
1353 if (*handle == DMA_ERROR_CODE)
1359 __free_from_pool(addr, size);
1363 static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
1364 dma_addr_t handle, size_t size)
1366 __iommu_remove_mapping(dev, handle, size);
1367 __free_from_pool(cpu_addr, size);
1370 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1371 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1373 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL);
1374 struct page **pages;
1377 *handle = DMA_ERROR_CODE;
1378 size = PAGE_ALIGN(size);
1380 if (!(gfp & __GFP_WAIT))
1381 return __iommu_alloc_atomic(dev, size, handle);
1384 * Following is a work-around (a.k.a. hack) to prevent pages
1385 * with __GFP_COMP being passed to split_page() which cannot
1386 * handle them. The real problem is that this flag probably
1387 * should be 0 on ARM as it is not supported on this
1388 * platform; see CONFIG_HUGETLBFS.
1390 gfp &= ~(__GFP_COMP);
1392 pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
1396 *handle = __iommu_create_mapping(dev, pages, size);
1397 if (*handle == DMA_ERROR_CODE)
1400 if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
1403 addr = __iommu_alloc_remap(pages, size, gfp, prot,
1404 __builtin_return_address(0));
1411 __iommu_remove_mapping(dev, *handle, size);
1413 __iommu_free_buffer(dev, pages, size, attrs);
1417 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1418 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1419 struct dma_attrs *attrs)
1421 unsigned long uaddr = vma->vm_start;
1422 unsigned long usize = vma->vm_end - vma->vm_start;
1423 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1425 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1431 int ret = vm_insert_page(vma, uaddr, *pages++);
1433 pr_err("Remapping memory failed: %d\n", ret);
1438 } while (usize > 0);
1444 * free a page as defined by the above mapping.
1445 * Must not be called with IRQs disabled.
1447 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1448 dma_addr_t handle, struct dma_attrs *attrs)
1450 struct page **pages;
1451 size = PAGE_ALIGN(size);
1453 if (__in_atomic_pool(cpu_addr, size)) {
1454 __iommu_free_atomic(dev, cpu_addr, handle, size);
1458 pages = __iommu_get_pages(cpu_addr, attrs);
1460 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
1464 if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
1465 dma_common_free_remap(cpu_addr, size,
1466 VM_ARM_DMA_CONSISTENT | VM_USERMAP);
1469 __iommu_remove_mapping(dev, handle, size);
1470 __iommu_free_buffer(dev, pages, size, attrs);
1473 static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
1474 void *cpu_addr, dma_addr_t dma_addr,
1475 size_t size, struct dma_attrs *attrs)
1477 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1478 struct page **pages = __iommu_get_pages(cpu_addr, attrs);
1483 return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
1487 static int __dma_direction_to_prot(enum dma_data_direction dir)
1492 case DMA_BIDIRECTIONAL:
1493 prot = IOMMU_READ | IOMMU_WRITE;
1498 case DMA_FROM_DEVICE:
1509 * Map a part of the scatter-gather list into contiguous io address space
1511 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1512 size_t size, dma_addr_t *handle,
1513 enum dma_data_direction dir, struct dma_attrs *attrs,
1516 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1517 dma_addr_t iova, iova_base;
1520 struct scatterlist *s;
1523 size = PAGE_ALIGN(size);
1524 *handle = DMA_ERROR_CODE;
1526 iova_base = iova = __alloc_iova(mapping, size);
1527 if (iova == DMA_ERROR_CODE)
1530 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1531 phys_addr_t phys = page_to_phys(sg_page(s));
1532 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1535 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1536 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1538 prot = __dma_direction_to_prot(dir);
1540 ret = iommu_map(mapping->domain, iova, phys, len, prot);
1543 count += len >> PAGE_SHIFT;
1546 *handle = iova_base;
1550 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1551 __free_iova(mapping, iova_base, size);
1555 static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1556 enum dma_data_direction dir, struct dma_attrs *attrs,
1559 struct scatterlist *s = sg, *dma = sg, *start = sg;
1561 unsigned int offset = s->offset;
1562 unsigned int size = s->offset + s->length;
1563 unsigned int max = dma_get_max_seg_size(dev);
1565 for (i = 1; i < nents; i++) {
1568 s->dma_address = DMA_ERROR_CODE;
1571 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1572 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1573 dir, attrs, is_coherent) < 0)
1576 dma->dma_address += offset;
1577 dma->dma_length = size - offset;
1579 size = offset = s->offset;
1586 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
1590 dma->dma_address += offset;
1591 dma->dma_length = size - offset;
1596 for_each_sg(sg, s, count, i)
1597 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1602 * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1603 * @dev: valid struct device pointer
1604 * @sg: list of buffers
1605 * @nents: number of buffers to map
1606 * @dir: DMA transfer direction
1608 * Map a set of i/o coherent buffers described by scatterlist in streaming
1609 * mode for DMA. The scatter gather list elements are merged together (if
1610 * possible) and tagged with the appropriate dma address and length. They are
1611 * obtained via sg_dma_{address,length}.
1613 int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1614 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1616 return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
1620 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1621 * @dev: valid struct device pointer
1622 * @sg: list of buffers
1623 * @nents: number of buffers to map
1624 * @dir: DMA transfer direction
1626 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1627 * The scatter gather list elements are merged together (if possible) and
1628 * tagged with the appropriate dma address and length. They are obtained via
1629 * sg_dma_{address,length}.
1631 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
1632 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1634 return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
1637 static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1638 int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
1641 struct scatterlist *s;
1644 for_each_sg(sg, s, nents, i) {
1646 __iommu_remove_mapping(dev, sg_dma_address(s),
1649 !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1650 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1656 * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1657 * @dev: valid struct device pointer
1658 * @sg: list of buffers
1659 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1660 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1662 * Unmap a set of streaming mode DMA translations. Again, CPU access
1663 * rules concerning calls here are the same as for dma_unmap_single().
1665 void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
1666 int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
1668 __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
1672 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1673 * @dev: valid struct device pointer
1674 * @sg: list of buffers
1675 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1676 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1678 * Unmap a set of streaming mode DMA translations. Again, CPU access
1679 * rules concerning calls here are the same as for dma_unmap_single().
1681 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1682 enum dma_data_direction dir, struct dma_attrs *attrs)
1684 __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
1688 * arm_iommu_sync_sg_for_cpu
1689 * @dev: valid struct device pointer
1690 * @sg: list of buffers
1691 * @nents: number of buffers to map (returned from dma_map_sg)
1692 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1694 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1695 int nents, enum dma_data_direction dir)
1697 struct scatterlist *s;
1700 for_each_sg(sg, s, nents, i)
1701 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1706 * arm_iommu_sync_sg_for_device
1707 * @dev: valid struct device pointer
1708 * @sg: list of buffers
1709 * @nents: number of buffers to map (returned from dma_map_sg)
1710 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1712 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1713 int nents, enum dma_data_direction dir)
1715 struct scatterlist *s;
1718 for_each_sg(sg, s, nents, i)
1719 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1724 * arm_coherent_iommu_map_page
1725 * @dev: valid struct device pointer
1726 * @page: page that buffer resides in
1727 * @offset: offset into page for start of buffer
1728 * @size: size of buffer to map
1729 * @dir: DMA transfer direction
1731 * Coherent IOMMU aware version of arm_dma_map_page()
1733 static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
1734 unsigned long offset, size_t size, enum dma_data_direction dir,
1735 struct dma_attrs *attrs)
1737 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1738 dma_addr_t dma_addr;
1739 int ret, prot, len = PAGE_ALIGN(size + offset);
1741 dma_addr = __alloc_iova(mapping, len);
1742 if (dma_addr == DMA_ERROR_CODE)
1745 prot = __dma_direction_to_prot(dir);
1747 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
1751 return dma_addr + offset;
1753 __free_iova(mapping, dma_addr, len);
1754 return DMA_ERROR_CODE;
1758 * arm_iommu_map_page
1759 * @dev: valid struct device pointer
1760 * @page: page that buffer resides in
1761 * @offset: offset into page for start of buffer
1762 * @size: size of buffer to map
1763 * @dir: DMA transfer direction
1765 * IOMMU aware version of arm_dma_map_page()
1767 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1768 unsigned long offset, size_t size, enum dma_data_direction dir,
1769 struct dma_attrs *attrs)
1771 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1772 __dma_page_cpu_to_dev(page, offset, size, dir);
1774 return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
1778 * arm_coherent_iommu_unmap_page
1779 * @dev: valid struct device pointer
1780 * @handle: DMA address of buffer
1781 * @size: size of buffer (same as passed to dma_map_page)
1782 * @dir: DMA transfer direction (same as passed to dma_map_page)
1784 * Coherent IOMMU aware version of arm_dma_unmap_page()
1786 static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1787 size_t size, enum dma_data_direction dir,
1788 struct dma_attrs *attrs)
1790 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1791 dma_addr_t iova = handle & PAGE_MASK;
1792 int offset = handle & ~PAGE_MASK;
1793 int len = PAGE_ALIGN(size + offset);
1798 iommu_unmap(mapping->domain, iova, len);
1799 __free_iova(mapping, iova, len);
1803 * arm_iommu_unmap_page
1804 * @dev: valid struct device pointer
1805 * @handle: DMA address of buffer
1806 * @size: size of buffer (same as passed to dma_map_page)
1807 * @dir: DMA transfer direction (same as passed to dma_map_page)
1809 * IOMMU aware version of arm_dma_unmap_page()
1811 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1812 size_t size, enum dma_data_direction dir,
1813 struct dma_attrs *attrs)
1815 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1816 dma_addr_t iova = handle & PAGE_MASK;
1817 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1818 int offset = handle & ~PAGE_MASK;
1819 int len = PAGE_ALIGN(size + offset);
1824 if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
1825 __dma_page_dev_to_cpu(page, offset, size, dir);
1827 iommu_unmap(mapping->domain, iova, len);
1828 __free_iova(mapping, iova, len);
1831 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1832 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1834 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1835 dma_addr_t iova = handle & PAGE_MASK;
1836 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1837 unsigned int offset = handle & ~PAGE_MASK;
1842 __dma_page_dev_to_cpu(page, offset, size, dir);
1845 static void arm_iommu_sync_single_for_device(struct device *dev,
1846 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1848 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1849 dma_addr_t iova = handle & PAGE_MASK;
1850 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1851 unsigned int offset = handle & ~PAGE_MASK;
1856 __dma_page_cpu_to_dev(page, offset, size, dir);
1859 struct dma_map_ops iommu_ops = {
1860 .alloc = arm_iommu_alloc_attrs,
1861 .free = arm_iommu_free_attrs,
1862 .mmap = arm_iommu_mmap_attrs,
1863 .get_sgtable = arm_iommu_get_sgtable,
1865 .map_page = arm_iommu_map_page,
1866 .unmap_page = arm_iommu_unmap_page,
1867 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1868 .sync_single_for_device = arm_iommu_sync_single_for_device,
1870 .map_sg = arm_iommu_map_sg,
1871 .unmap_sg = arm_iommu_unmap_sg,
1872 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1873 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1875 .set_dma_mask = arm_dma_set_mask,
1878 struct dma_map_ops iommu_coherent_ops = {
1879 .alloc = arm_iommu_alloc_attrs,
1880 .free = arm_iommu_free_attrs,
1881 .mmap = arm_iommu_mmap_attrs,
1882 .get_sgtable = arm_iommu_get_sgtable,
1884 .map_page = arm_coherent_iommu_map_page,
1885 .unmap_page = arm_coherent_iommu_unmap_page,
1887 .map_sg = arm_coherent_iommu_map_sg,
1888 .unmap_sg = arm_coherent_iommu_unmap_sg,
1890 .set_dma_mask = arm_dma_set_mask,
1894 * arm_iommu_create_mapping
1895 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1896 * @base: start address of the valid IO address space
1897 * @size: maximum size of the valid IO address space
1899 * Creates a mapping structure which holds information about used/unused
1900 * IO address ranges, which is required to perform memory allocation and
1901 * mapping with IOMMU aware functions.
1903 * The client device need to be attached to the mapping with
1904 * arm_iommu_attach_device function.
1906 struct dma_iommu_mapping *
1907 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
1909 unsigned int bits = size >> PAGE_SHIFT;
1910 unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long);
1911 struct dma_iommu_mapping *mapping;
1916 return ERR_PTR(-EINVAL);
1918 if (bitmap_size > PAGE_SIZE) {
1919 extensions = bitmap_size / PAGE_SIZE;
1920 bitmap_size = PAGE_SIZE;
1923 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1927 mapping->bitmap_size = bitmap_size;
1928 mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *),
1930 if (!mapping->bitmaps)
1933 mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL);
1934 if (!mapping->bitmaps[0])
1937 mapping->nr_bitmaps = 1;
1938 mapping->extensions = extensions;
1939 mapping->base = base;
1940 mapping->bits = BITS_PER_BYTE * bitmap_size;
1942 spin_lock_init(&mapping->lock);
1944 mapping->domain = iommu_domain_alloc(bus);
1945 if (!mapping->domain)
1948 kref_init(&mapping->kref);
1951 kfree(mapping->bitmaps[0]);
1953 kfree(mapping->bitmaps);
1957 return ERR_PTR(err);
1959 EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
1961 static void release_iommu_mapping(struct kref *kref)
1964 struct dma_iommu_mapping *mapping =
1965 container_of(kref, struct dma_iommu_mapping, kref);
1967 iommu_domain_free(mapping->domain);
1968 for (i = 0; i < mapping->nr_bitmaps; i++)
1969 kfree(mapping->bitmaps[i]);
1970 kfree(mapping->bitmaps);
1974 static int extend_iommu_mapping(struct dma_iommu_mapping *mapping)
1978 if (mapping->nr_bitmaps > mapping->extensions)
1981 next_bitmap = mapping->nr_bitmaps;
1982 mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size,
1984 if (!mapping->bitmaps[next_bitmap])
1987 mapping->nr_bitmaps++;
1992 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1995 kref_put(&mapping->kref, release_iommu_mapping);
1997 EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
2000 * arm_iommu_attach_device
2001 * @dev: valid struct device pointer
2002 * @mapping: io address space mapping structure (returned from
2003 * arm_iommu_create_mapping)
2005 * Attaches specified io address space mapping to the provided device,
2006 * this replaces the dma operations (dma_map_ops pointer) with the
2007 * IOMMU aware version. More than one client might be attached to
2008 * the same io address space mapping.
2010 int arm_iommu_attach_device(struct device *dev,
2011 struct dma_iommu_mapping *mapping)
2015 err = iommu_attach_device(mapping->domain, dev);
2019 kref_get(&mapping->kref);
2020 dev->archdata.mapping = mapping;
2021 set_dma_ops(dev, &iommu_ops);
2023 pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
2026 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
2029 * arm_iommu_detach_device
2030 * @dev: valid struct device pointer
2032 * Detaches the provided device from a previously attached map.
2033 * This voids the dma operations (dma_map_ops pointer)
2035 void arm_iommu_detach_device(struct device *dev)
2037 struct dma_iommu_mapping *mapping;
2039 mapping = to_dma_iommu_mapping(dev);
2041 dev_warn(dev, "Not attached\n");
2045 iommu_detach_device(mapping->domain, dev);
2046 kref_put(&mapping->kref, release_iommu_mapping);
2047 dev->archdata.mapping = NULL;
2048 set_dma_ops(dev, NULL);
2050 pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
2052 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);