2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 * These are the low level assembler for performing cache and TLB
28 * functions on the arm925.
30 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
32 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
34 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
35 * entry mode" must be 0 to flush the entries in both segments
36 * at once. This is the default value. See TRM 2-20 and 2-24 for
39 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
40 * like the "Transparent mode" must be on for partial cache flushes
41 * to work in this mode. This mode only works with 16-bit external
42 * memory. See TRM 2-24 for more information.
44 * NOTE3: Write-back cache flushing seems to be flakey with devices using
45 * direct memory access, such as USB OHCI. The workaround is to use
46 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
47 * the default for OMAP-1510).
50 #include <linux/linkage.h>
51 #include <linux/config.h>
52 #include <linux/init.h>
53 #include <asm/assembler.h>
54 #include <asm/pgtable.h>
55 #include <asm/procinfo.h>
57 #include <asm/ptrace.h>
58 #include "proc-macros.S"
61 * The size of one data cache line.
63 #define CACHE_DLINESIZE 16
66 * The number of data cache segments.
68 #define CACHE_DSEGMENTS 2
71 * The number of lines in a cache segment.
73 #define CACHE_DENTRIES 256
76 * This is the size at which it becomes more efficient to
77 * clean the whole cache, rather than using the individual
78 * cache line maintainence instructions.
80 #define CACHE_DLIMIT 8192
84 * cpu_arm925_proc_init()
86 ENTRY(cpu_arm925_proc_init)
90 * cpu_arm925_proc_fin()
92 ENTRY(cpu_arm925_proc_fin)
94 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
96 bl arm925_flush_kern_cache_all
97 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
98 bic r0, r0, #0x1000 @ ...i............
99 bic r0, r0, #0x000e @ ............wca.
100 mcr p15, 0, r0, c1, c0, 0 @ disable caches
104 * cpu_arm925_reset(loc)
106 * Perform a soft reset of the system. Put the CPU into the
107 * same state as it would be if it had been reset, and branch
108 * to what would be the reset vector.
110 * loc: location to jump to for soft reset
113 ENTRY(cpu_arm925_reset)
114 /* Send software reset to MPU and DSP */
116 orr ip, ip, #0x00fe0000
117 orr ip, ip, #0x0000ce00
122 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
123 mcr p15, 0, ip, c7, c10, 4 @ drain WB
124 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
125 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
126 bic ip, ip, #0x000f @ ............wcam
127 bic ip, ip, #0x1100 @ ...i...s........
128 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
132 * cpu_arm925_do_idle()
134 * Called with IRQs disabled
137 ENTRY(cpu_arm925_do_idle)
139 mrc p15, 0, r1, c1, c0, 0 @ Read control register
140 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
142 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
143 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
148 * flush_user_cache_all()
150 * Clean and invalidate all cache entries in a particular
153 ENTRY(arm925_flush_user_cache_all)
157 * flush_kern_cache_all()
159 * Clean and invalidate the entire cache.
161 ENTRY(arm925_flush_kern_cache_all)
165 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
168 /* Flush entries in both segments at once, see NOTE1 above */
169 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
172 bcs 2b @ entries 255 to 0
175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
180 * flush_user_cache_range(start, end, flags)
182 * Clean and invalidate a range of cache entries in the
183 * specified address range.
185 * - start - start address (inclusive)
186 * - end - end address (exclusive)
187 * - flags - vm_flags describing address space
189 ENTRY(arm925_flush_user_cache_range)
191 sub r3, r1, r0 @ calculate total size
192 cmp r3, #CACHE_DLIMIT
193 bgt __flush_whole_cache
195 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
198 add r0, r0, #CACHE_DLINESIZE
199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
201 add r0, r0, #CACHE_DLINESIZE
203 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
204 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
205 add r0, r0, #CACHE_DLINESIZE
206 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
207 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
208 add r0, r0, #CACHE_DLINESIZE
213 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
217 * coherent_kern_range(start, end)
219 * Ensure coherency between the Icache and the Dcache in the
220 * region described by start, end. If you have non-snooping
221 * Harvard caches, you need to implement this function.
223 * - start - virtual start address
224 * - end - virtual end address
226 ENTRY(arm925_coherent_kern_range)
230 * coherent_user_range(start, end)
232 * Ensure coherency between the Icache and the Dcache in the
233 * region described by start, end. If you have non-snooping
234 * Harvard caches, you need to implement this function.
236 * - start - virtual start address
237 * - end - virtual end address
239 ENTRY(arm925_coherent_user_range)
240 bic r0, r0, #CACHE_DLINESIZE - 1
241 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
242 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
243 add r0, r0, #CACHE_DLINESIZE
246 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 * flush_kern_dcache_page(void *page)
252 * Ensure no D cache aliasing occurs, either with itself or
255 * - addr - page aligned address
257 ENTRY(arm925_flush_kern_dcache_page)
259 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
260 add r0, r0, #CACHE_DLINESIZE
264 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
265 mcr p15, 0, r0, c7, c10, 4 @ drain WB
269 * dma_inv_range(start, end)
271 * Invalidate (discard) the specified virtual address range.
272 * May not write back any entries. If 'start' or 'end'
273 * are not cache line aligned, those lines must be written
276 * - start - virtual start address
277 * - end - virtual end address
281 ENTRY(arm925_dma_inv_range)
282 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
283 tst r0, #CACHE_DLINESIZE - 1
284 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
285 tst r1, #CACHE_DLINESIZE - 1
286 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
288 bic r0, r0, #CACHE_DLINESIZE - 1
289 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
290 add r0, r0, #CACHE_DLINESIZE
293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
297 * dma_clean_range(start, end)
299 * Clean the specified virtual address range.
301 * - start - virtual start address
302 * - end - virtual end address
306 ENTRY(arm925_dma_clean_range)
307 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
308 bic r0, r0, #CACHE_DLINESIZE - 1
309 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
310 add r0, r0, #CACHE_DLINESIZE
314 mcr p15, 0, r0, c7, c10, 4 @ drain WB
318 * dma_flush_range(start, end)
320 * Clean and invalidate the specified virtual address range.
322 * - start - virtual start address
323 * - end - virtual end address
325 ENTRY(arm925_dma_flush_range)
326 bic r0, r0, #CACHE_DLINESIZE - 1
328 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
329 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
331 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
333 add r0, r0, #CACHE_DLINESIZE
336 mcr p15, 0, r0, c7, c10, 4 @ drain WB
339 ENTRY(arm925_cache_fns)
340 .long arm925_flush_kern_cache_all
341 .long arm925_flush_user_cache_all
342 .long arm925_flush_user_cache_range
343 .long arm925_coherent_kern_range
344 .long arm925_coherent_user_range
345 .long arm925_flush_kern_dcache_page
346 .long arm925_dma_inv_range
347 .long arm925_dma_clean_range
348 .long arm925_dma_flush_range
350 ENTRY(cpu_arm925_dcache_clean_area)
351 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
352 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 add r0, r0, #CACHE_DLINESIZE
354 subs r1, r1, #CACHE_DLINESIZE
357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
360 /* =============================== PageTable ============================== */
363 * cpu_arm925_switch_mm(pgd)
365 * Set the translation base pointer to be as described by pgd.
367 * pgd: new page tables
370 ENTRY(cpu_arm925_switch_mm)
372 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
373 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
375 /* Flush entries in bothe segments at once, see NOTE1 above */
376 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
377 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
379 bcs 2b @ entries 255 to 0
381 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
382 mcr p15, 0, ip, c7, c10, 4 @ drain WB
383 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
384 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
388 * cpu_arm925_set_pte(ptep, pte)
390 * Set a PTE and flush it out
393 ENTRY(cpu_arm925_set_pte)
394 str r1, [r0], #-2048 @ linux version
396 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
398 bic r2, r1, #PTE_SMALL_AP_MASK
399 bic r2, r2, #PTE_TYPE_MASK
400 orr r2, r2, #PTE_TYPE_SMALL
402 tst r1, #L_PTE_USER @ User?
403 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
405 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
406 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
408 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
411 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
412 eor r3, r2, #0x0a @ C & small page?
416 str r2, [r0] @ hardware version
418 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
419 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
421 mcr p15, 0, r0, c7, c10, 4 @ drain WB
426 .type __arm925_setup, #function
429 #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
433 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
434 orr r0,r0,#1 << 1 @ transparent mode on
435 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
438 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
439 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
440 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
442 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
443 mov r0, #4 @ disable write-back on caches explicitly
444 mcr p15, 7, r0, c15, c0, 0
447 mrc p15, 0, r0, c1, c0 @ get control register v4
448 ldr r5, arm925_cr1_clear
450 ldr r5, arm925_cr1_set
452 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
453 orr r0, r0, #0x4000 @ .1.. .... .... ....
456 .size __arm925_setup, . - __arm925_setup
460 * .RVI ZFRS BLDP WCAM
461 * .011 0001 ..11 1101
464 .type arm925_cr1_clear, #object
465 .type arm925_cr1_set, #object
474 * Purpose : Function pointers used to access above functions - all calls
477 .type arm925_processor_functions, #object
478 arm925_processor_functions:
479 .word v4t_early_abort
480 .word cpu_arm925_proc_init
481 .word cpu_arm925_proc_fin
482 .word cpu_arm925_reset
483 .word cpu_arm925_do_idle
484 .word cpu_arm925_dcache_clean_area
485 .word cpu_arm925_switch_mm
486 .word cpu_arm925_set_pte
487 .size arm925_processor_functions, . - arm925_processor_functions
491 .type cpu_arch_name, #object
494 .size cpu_arch_name, . - cpu_arch_name
496 .type cpu_elf_name, #object
499 .size cpu_elf_name, . - cpu_elf_name
501 .type cpu_arm925_name, #object
504 #ifndef CONFIG_CPU_ICACHE_DISABLE
507 #ifndef CONFIG_CPU_DCACHE_DISABLE
509 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
514 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
519 .size cpu_arm925_name, . - cpu_arm925_name
523 .section ".proc.info.init", #alloc, #execinstr
525 .type __arm925_proc_info,#object
529 .long PMD_TYPE_SECT | \
531 PMD_SECT_AP_WRITE | \
536 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
537 .long cpu_arm925_name
538 .long arm925_processor_functions
541 .long arm925_cache_fns
542 .size __arm925_proc_info, . - __arm925_proc_info
544 .type __arm915_proc_info,#object
548 .long PMD_TYPE_SECT | \
550 PMD_SECT_AP_WRITE | \
555 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
556 .long cpu_arm925_name
557 .long arm925_processor_functions
560 .long arm925_cache_fns
561 .size __arm925_proc_info, . - __arm925_proc_info