2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #define TTB_S (1 << 1)
23 #define TTB_RGN_NC (0 << 3)
24 #define TTB_RGN_OC_WBWA (1 << 3)
25 #define TTB_RGN_OC_WT (2 << 3)
26 #define TTB_RGN_OC_WB (3 << 3)
27 #define TTB_NOS (1 << 5)
28 #define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29 #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30 #define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31 #define TTB_IRGN_WB ((1 << 0) | (1 << 6))
33 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34 #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
35 #define PMD_FLAGS_UP PMD_SECT_WB
37 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38 #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39 #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
41 ENTRY(cpu_v7_proc_init)
43 ENDPROC(cpu_v7_proc_init)
45 ENTRY(cpu_v7_proc_fin)
46 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
47 bic r0, r0, #0x1000 @ ...i............
48 bic r0, r0, #0x0006 @ .............ca.
49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 ENDPROC(cpu_v7_proc_fin)
56 * Perform a soft reset of the system. Put the CPU into the
57 * same state as it would be if it had been reset, and branch
58 * to what would be the reset vector.
60 * - loc - location to jump to for soft reset
70 * Idle the processor (eg, wait for interrupt).
72 * IRQs are already disabled.
75 dsb @ WFI may enter a low-power mode
78 ENDPROC(cpu_v7_do_idle)
80 ENTRY(cpu_v7_dcache_clean_area)
81 #ifndef TLB_CAN_READ_FROM_L1_CACHE
82 dcache_line_size r2, r3
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
90 ENDPROC(cpu_v7_dcache_clean_area)
93 * cpu_v7_switch_mm(pgd_phys, tsk)
95 * Set the translation table base pointer to be pgd_phys
97 * - pgd_phys - physical address of new TTB
100 * - we are not using split page tables
102 ENTRY(cpu_v7_switch_mm)
105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
108 #ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
113 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
115 mcr p15, 0, r1, c13, c0, 1 @ set context ID
119 ENDPROC(cpu_v7_switch_mm)
122 * cpu_v7_set_pte_ext(ptep, pte)
124 * Set a level 2 translation table entry.
126 * - ptep - pointer to level 2 translation table entry
127 * (hardware version is stored at +2048 bytes)
128 * - pte - PTE value to store
129 * - ext - value for extended PTE bits
131 ENTRY(cpu_v7_set_pte_ext)
133 str r1, [r0] @ linux version
135 bic r3, r1, #0x000003f0
136 bic r3, r3, #PTE_TYPE_MASK
138 orr r3, r3, #PTE_EXT_AP0 | 2
141 orrne r3, r3, #PTE_EXT_TEX(1)
143 eor r1, r1, #L_PTE_DIRTY
144 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
145 orrne r3, r3, #PTE_EXT_APX
148 orrne r3, r3, #PTE_EXT_AP1
149 #ifdef CONFIG_CPU_USE_DOMAINS
150 @ allow kernel read/write access to read-only user pages
151 tstne r3, #PTE_EXT_APX
152 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
156 orrne r3, r3, #PTE_EXT_XN
159 tstne r1, #L_PTE_PRESENT
163 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
166 ENDPROC(cpu_v7_set_pte_ext)
169 .ascii "ARMv7 Processor"
177 * Initialise TLB, Caches, and MMU state ready to switch the MMU
178 * on. Return in r0 the new CP15 C1 control register setting.
180 * We automatically detect if we have a Harvard cache, and use the
181 * Harvard cache control instructions insead of the unified cache
182 * control instructions.
184 * This should be able to cover all ARMv7 cores.
186 * It is assumed that:
187 * - cache type register is implemented
191 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
192 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
193 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
194 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
195 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
198 adr r12, __v7_setup_stack @ the local stack
199 stmia r12, {r0-r5, r7, r9, r11, lr}
200 bl v7_flush_dcache_all
201 ldmia r12, {r0-r5, r7, r9, r11, lr}
203 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
204 and r10, r0, #0xff000000 @ ARM?
207 and r5, r0, #0x00f00000 @ variant
208 and r6, r0, #0x0000000f @ revision
209 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
210 ubfx r0, r0, #4, #12 @ primary part number
212 /* Cortex-A8 Errata */
213 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
216 #ifdef CONFIG_ARM_ERRATA_430973
217 teq r5, #0x00100000 @ only present in r1p*
218 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
219 orreq r10, r10, #(1 << 6) @ set IBE to 1
220 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
222 #ifdef CONFIG_ARM_ERRATA_458693
223 teq r6, #0x20 @ only present in r2p0
224 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
225 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
226 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
227 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
229 #ifdef CONFIG_ARM_ERRATA_460075
230 teq r6, #0x20 @ only present in r2p0
231 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
233 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
234 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
238 /* Cortex-A9 Errata */
239 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
242 #ifdef CONFIG_ARM_ERRATA_742230
243 cmp r6, #0x22 @ only present up to r2p2
244 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
245 orrle r10, r10, #1 << 4 @ set bit #4
246 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
248 #ifdef CONFIG_ARM_ERRATA_742231
249 teq r6, #0x20 @ present in r2p0
250 teqne r6, #0x21 @ present in r2p1
251 teqne r6, #0x22 @ present in r2p2
252 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
253 orreq r10, r10, #1 << 12 @ set bit #12
254 orreq r10, r10, #1 << 22 @ set bit #22
255 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
257 #ifdef CONFIG_ARM_ERRATA_743622
258 teq r6, #0x20 @ present in r2p0
259 teqne r6, #0x21 @ present in r2p1
260 teqne r6, #0x22 @ present in r2p2
261 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
262 orreq r10, r10, #1 << 6 @ set bit #6
263 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
268 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
272 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
273 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
274 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
275 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
276 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
278 * Memory region attributes with SCTLR.TRE=1
281 * TR = PRRR[2n+1:2n] - memory type
282 * IR = NMRR[2n+1:2n] - inner cacheable property
283 * OR = NMRR[2n+17:2n+16] - outer cacheable property
287 * BUFFERABLE 001 10 00 00
288 * WRITETHROUGH 010 10 10 10
289 * WRITEBACK 011 10 11 11
291 * WRITEALLOC 111 10 01 01
293 * DEV_NONSHARED 100 01
299 * DS0 = PRRR[16] = 0 - device shareable property
300 * DS1 = PRRR[17] = 1 - device shareable property
301 * NS0 = PRRR[18] = 0 - normal shareable property
302 * NS1 = PRRR[19] = 1 - normal shareable property
303 * NOS = PRRR[24+n] = 1 - not outer shareable
305 ldr r5, =0xff0a81a8 @ PRRR
306 ldr r6, =0x40e040e0 @ NMRR
307 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
308 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
312 #ifdef CONFIG_CPU_ENDIAN_BE8
313 orr r6, r6, #1 << 25 @ big-endian page tables
315 #ifdef CONFIG_SWP_EMULATE
316 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
317 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
319 mrc p15, 0, r0, c1, c0, 0 @ read control register
320 bic r0, r0, r5 @ clear bits them
321 orr r0, r0, r6 @ set them
322 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
323 mov pc, lr @ return to head.S:__ret
327 * TFR EV X F I D LR S
328 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
329 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
330 * 1 0 110 0011 1100 .111 1101 < we want
332 .type v7_crval, #object
334 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
337 .space 4 * 11 @ 11 registers
341 .type v7_processor_functions, #object
342 ENTRY(v7_processor_functions)
345 .word cpu_v7_proc_init
346 .word cpu_v7_proc_fin
349 .word cpu_v7_dcache_clean_area
350 .word cpu_v7_switch_mm
351 .word cpu_v7_set_pte_ext
352 .size v7_processor_functions, . - v7_processor_functions
356 .type cpu_arch_name, #object
359 .size cpu_arch_name, . - cpu_arch_name
361 .type cpu_elf_name, #object
364 .size cpu_elf_name, . - cpu_elf_name
367 .section ".proc.info.init", #alloc, #execinstr
369 .type __v7_ca9mp_proc_info, #object
370 __v7_ca9mp_proc_info:
371 .long 0x410fc090 @ Required ID value
372 .long 0xff0ffff0 @ Mask for ID
375 PMD_SECT_AP_WRITE | \
380 PMD_SECT_AP_WRITE | \
383 .long PMD_TYPE_SECT | \
385 PMD_SECT_AP_WRITE | \
387 W(b) __v7_ca9mp_setup
390 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
392 .long v7_processor_functions
396 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
399 * Match any ARMv7 processor core.
401 .type __v7_proc_info, #object
403 .long 0x000f0000 @ Required ID value
404 .long 0x000f0000 @ Mask for ID
407 PMD_SECT_AP_WRITE | \
412 PMD_SECT_AP_WRITE | \
415 .long PMD_TYPE_SECT | \
417 PMD_SECT_AP_WRITE | \
422 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
424 .long v7_processor_functions
428 .size __v7_proc_info, . - __v7_proc_info