1 // include/asm-arm/mach-omap/usb.h
3 #ifndef __ASM_ARCH_OMAP_USB_H
4 #define __ASM_ARCH_OMAP_USB_H
7 #include <linux/usb/musb.h>
9 #define OMAP3_HS_USB_PORTS 3
11 enum usbhs_omap_port_mode {
12 OMAP_USBHS_PORT_MODE_UNUSED,
13 OMAP_EHCI_PORT_MODE_PHY,
14 OMAP_EHCI_PORT_MODE_TLL,
15 OMAP_EHCI_PORT_MODE_HSIC,
16 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
17 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
18 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
19 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
20 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
21 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
22 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
23 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
24 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
25 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
28 struct usbhs_omap_board_data {
29 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
31 /* have to be valid if phy_reset is true and portx is in phy mode */
32 int reset_gpio_port[OMAP3_HS_USB_PORTS];
34 /* Set this to true for ES2.x silicon */
35 unsigned es2_compatibility:1;
40 * Regulators for USB PHYs.
41 * Each PHY can have a separate regulator.
43 struct regulator *regulator[OMAP3_HS_USB_PORTS];
46 #ifdef CONFIG_ARCH_OMAP2PLUS
48 struct ehci_hcd_omap_platform_data {
49 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
50 int reset_gpio_port[OMAP3_HS_USB_PORTS];
51 struct regulator *regulator[OMAP3_HS_USB_PORTS];
55 struct ohci_hcd_omap_platform_data {
56 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
57 unsigned es2_compatibility:1;
60 struct usbhs_omap_platform_data {
61 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
63 struct ehci_hcd_omap_platform_data *ehci_data;
64 struct ohci_hcd_omap_platform_data *ohci_data;
66 /*-------------------------------------------------------------------------*/
68 struct omap_musb_board_data {
73 void (*set_phy_power)(u8 on);
74 void (*clear_irq)(void);
75 void (*set_mode)(u8 mode);
79 enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
81 extern void usb_musb_init(struct omap_musb_board_data *board_data);
83 extern void usbhs_init(const struct usbhs_omap_board_data *pdata);
85 extern int omap4430_phy_power(struct device *dev, int ID, int on);
86 extern int omap4430_phy_set_clk(struct device *dev, int on);
87 extern int omap4430_phy_init(struct device *dev);
88 extern int omap4430_phy_exit(struct device *dev);
89 extern int omap4430_phy_suspend(struct device *dev, int suspend);
93 extern void am35x_musb_reset(void);
94 extern void am35x_musb_phy_power(u8 on);
95 extern void am35x_musb_clear_irq(void);
96 extern void am35x_set_mode(u8 musb_mode);
97 extern void ti81xx_musb_phy_power(u8 on);
100 /* USB 2.0 PHY Control */
101 #define CONF2_PHY_GPIOMODE (1 << 23)
102 #define CONF2_OTGMODE (3 << 14)
103 #define CONF2_NO_OVERRIDE (0 << 14)
104 #define CONF2_FORCE_HOST (1 << 14)
105 #define CONF2_FORCE_DEVICE (2 << 14)
106 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
107 #define CONF2_SESENDEN (1 << 13)
108 #define CONF2_VBDTCTEN (1 << 12)
109 #define CONF2_REFFREQ_24MHZ (2 << 8)
110 #define CONF2_REFFREQ_26MHZ (7 << 8)
111 #define CONF2_REFFREQ_13MHZ (6 << 8)
112 #define CONF2_REFFREQ (0xf << 8)
113 #define CONF2_PHYCLKGD (1 << 7)
114 #define CONF2_VBUSSENSE (1 << 6)
115 #define CONF2_PHY_PLLON (1 << 5)
116 #define CONF2_RESET (1 << 4)
117 #define CONF2_PHYPWRDN (1 << 3)
118 #define CONF2_OTGPWRDN (1 << 2)
119 #define CONF2_DATPOL (1 << 1)
121 /* TI81XX specific definitions */
122 #define USBCTRL0 0x620
123 #define USBSTAT0 0x624
125 /* TI816X PHY controls bits */
126 #define TI816X_USBPHY0_NORMAL_MODE (1 << 0)
127 #define TI816X_USBPHY_REFCLK_OSC (1 << 8)
129 /* TI814X PHY controls bits */
130 #define USBPHY_CM_PWRDN (1 << 0)
131 #define USBPHY_OTG_PWRDN (1 << 1)
132 #define USBPHY_CHGDET_DIS (1 << 2)
133 #define USBPHY_CHGDET_RSTRT (1 << 3)
134 #define USBPHY_SRCONDM (1 << 4)
135 #define USBPHY_SINKONDP (1 << 5)
136 #define USBPHY_CHGISINK_EN (1 << 6)
137 #define USBPHY_CHGVSRC_EN (1 << 7)
138 #define USBPHY_DMPULLUP (1 << 8)
139 #define USBPHY_DPPULLUP (1 << 9)
140 #define USBPHY_CDET_EXTCTL (1 << 10)
141 #define USBPHY_GPIO_MODE (1 << 12)
142 #define USBPHY_DPOPBUFCTL (1 << 13)
143 #define USBPHY_DMOPBUFCTL (1 << 14)
144 #define USBPHY_DPINPUT (1 << 15)
145 #define USBPHY_DMINPUT (1 << 16)
146 #define USBPHY_DPGPIO_PD (1 << 17)
147 #define USBPHY_DMGPIO_PD (1 << 18)
148 #define USBPHY_OTGVDET_EN (1 << 19)
149 #define USBPHY_OTGSESSEND_EN (1 << 20)
150 #define USBPHY_DATA_POLARITY (1 << 23)
152 #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
153 u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
154 u32 omap1_usb1_init(unsigned nwires);
155 u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
157 static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
161 static inline u32 omap1_usb1_init(unsigned nwires)
166 static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
172 #endif /* __ASM_ARCH_OMAP_USB_H */